UCC3941D-3

UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ application INFO available 1V Synchronous Boost Converter FEATURES DESCRIPTION • 1V Input Voltage Operation Startup Guaranteed Under Full Load on Main Output With Operation Down to 0.4V The UCC3941 family of low input voltage single inductor boost converters are optimized to operate from a single or dual alkaline cell, and step up to a 3.3V, 5V, or an adjustable output at 500mW. The UCC3941 family also provides an auxiliary 9V 100mW output, primarily for the gate drive supply, which can be used for applications requiring an auxiliary output such as a 5V supply by linear regulating. The primary output will start up under full load at input voltages typically as low as 0.8V, with a guaranteed maximum of 1V, and will operate down to 0.4V once the converter is operating, maximizing battery utilization. • Input Voltage Range of 1V to VOUT + 0.5V • 500mW Output Power at Battery Voltages as Low as 0.8V • Secondary 9V Supply From a Single Inductor • • • • Demanding applications such as Pagers and PDA’s require high efficiency Adjustable Output Power Limit Control from several milli-watts to several hundred milli-watts, and the UCC3941 family accommodates these applications with >80% typical efficiencies Output Fully Disconnected in over the wide range of operation. The high efficiency at low output current Shutdown is achieved by optimizing switching and conduction losses along with low quiescent current. At higher output current the 0.25Ω switch, and 0.4Ω synAdaptive Current Mode Control for chronous rectifier, along with continuous mode conduction, provide high efOptimum Efficiency ficiency. The wide input voltage range on the UCC3941 family can 8µA Shutdown Supply Current accommodate other power sources such as NiCd and NiMH. Other features include maximum power control and shutdown control. Packages available are the 8-pin SOIC (D) and 8-pin DIP (N or J). SIMPLIFIED BLOCK DIAGRAM AND APPLICATION CIRCUIT + 10µF 22µH VIN 0.8V TO VOUT +0.5V SW UCC3941-3 = 3.3V UCC3941-5 = 5.0V UCC3941-ADJ = 1.30V TO 6V VOUT 8 3 8V VGD 0.4Ω 2 10µF STARTUP CIRCUITRY 1 0.25Ω PLIM 5 SD 4 *SGND/FB OPEN=SD – + UCC3941-ADJ 6 1.25V *FOR UCC3941-ADJ ONLY: PIN 7 = SGND & PGND, PIN 6 = OUTPUT SENSE FEEDBACK, FB. FOR UCC3941-ADJ ONLY 100µF MODULATOR CONTROL CIRCUIT SYNCHRONOUS RECTIFICATION CIRCUITRY ANTI-CROSS CONDUCTION STARTUP MULTIPLEXING LOGIC MAXIMUM INPUT POWER CONTROL ADAPTIVE CURRENT CONTROL PGND 7 UDG-98147 SLUS242 - JULY 1999 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS DIL-8, SOIC-8 (Top View) N or J Package, D Package VIN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V SD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VIN PLIM Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V VGD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V SW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V VOUT Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Pin 6 is FB for UCC3941-ADJ. ELECTRICAL CHARACTERISTICS: Unless otherwise specified, for UCC3941, TA = 0°C to 70°C; for UCC2941, TA = –40°C to 85°C; VIN = 1.25V, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIN Section Minimum Startup Voltage No External VGD Load, TJ = 25°C, IOUT = 100mA (Note 1) 0.8 1.0 V Minimum Start Voltage No External VGD Load, IOUT = 100mA, TJ = 0° C to 85° C (Note 1) 0.9 1.1 V Minimum Startup Voltage No External VGD Load, TJ = –40°C to 0° C 0.9 Minimum Dropout Voltage No External VGD Load, IOUT = 100mA, VGD = 6.3V (Note 1) Input Voltage Range 1 1.5 V 0.5 V VOUT +0.5 V Quiescent Supply Current (Note 2) 13 25 µA Supply Current at Shutdown SD = Open 8 20 µA Quiescent Supply Current (Note 2) 32 80 µA Supply Current at Shutdown SD = Open 6 15 µA Regulation Voltage (UCC3941-3) 1V < VIN < 3V 3.18 3.25 3.37 V 1V < VIN < 3V, 0mA < IOUT < 150mA (Note 1) 3.17 3.30 3.43 V 1V < VIN < 5V 4.85 5.00 5.15 V 1V < VIN < 5V, 0mA < IOUT 100mA (Note 1) 4.8 5.0 5.2 V 1.212 1.250 1.288 V Output Section Regulation Voltage (UCC3941-5) FB Voltage (UCC3941-ADJ) 1V < VIN < 3V VGD Output Section Quiescent Supply Current (Note 2) 25 60 µA Supply Current at Shutdown SD = Open 8 20 µA Regulation Voltage 1V < VIN < 3V 7.5 8.7 9.2 V 1V < VIN < 3V, 0mA < IOUT < 10mA (Note 1) 7.4 8.7 9.3 V 0.50 0.85 A Inductor Charging Section (L = 22µH) Peak Discontinuous Current Peak Continuous Current Over Operating Range RPLIM = 6.2Ω, UCC3941-3 and UCC3941-5 0.5 0.8 1.1 A UCC3941-ADJ 0.6 0.9 1.3 A 2 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ ELECTRICAL CHARACTERISTICS: Unless otherwise specified, for UCC3941, TA = 0°C to 70°C; for UCC2941, TA = –40°C to 85°C; VIN = 1.25V, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Inductor Charging Section Charge Switch RDS(on) N and D Package, I = 200mA Current Limit Delay (Note 1) 0.25 0.4 50 Ω ns Synchronous Rectifier Section Rectifier RDS(on) N and D Package, I = 200mA, UCC3941-ADJ VOUT = 3.3V and UCC3941–3 0.35 0.6 Ω N and D Package, I = 200mA, UCC3941-5 0.5 0.8 Ω Shutdown Section Shutdown Bias Current –10 –7 µA Note 1: Performance from application circuit shown in Figures 3 - 5 guaranteed by design and alternate testing methods, but not 100% tested as shown in production. Note 2: For the UCC3941-3, VOUT = 3.47V and VGD = 9.3V. For the UCC3941-5, VOUT = 5.25V, VGD = 9.3V. For the UCC3941ADJ, FB = 1.315V, VGD = 9.3V. PIN DESCRIPTIONS FB: Feedback control pin used in the UCC3941-ADJ version only. The internal reference for this comparator is 1.25V and external resistors provide the gain to the output voltage. SGND: Signal ground of the IC. For the UCC3941-ADJ signal ground and power ground lines are tied to a common pin. SW: An inductor is connected between this node and VIN. The VGD (Gate Drive Supply) flyback diode is also connected to this pin. When servicing the 3.3V supply, this pin will go low charging the inductor, then shut off, dumping the energy through the synchronous rectifier to the output. When servicing the VGD supply, the internal synchronous rectifier stays off, and the energy is diverted to VGD through the flyback diode. During discontinuous portions of the inductor current a MOSFET resistively connects VIN to SW damping excess circulating energy to eliminate undesired high frequency ringing. PGND: Power ground of the IC. The inductor charging current flows through this pin. For the UCC3941-ADJ signal ground and power ground lines are tied to a common pin. PLIM: This pin is programmed to set the maximum input power for the converter. For example a 1A current limit at 1V would have a 333mA limit at 3V input keeping the input power constant at 1W. The peak current at VIN = 1V is programmed to 1.5A (1.5W) when this pin is grounded. The power limit is given by: PL(W ) = VGD: The VGD pin which is coarsely regulated around 9V and is primarily used for the gate drive supply for the power switches in the IC. This pin can be loaded with up to 10mA as long as it does not present a load at voltages below 2V. This ensures proper startup of the IC. The VGD supply can go as low as 7.5V without interfering with the servicing of the 3.3V output. Below 7.5V, VGD will have the highest priority, although practically the voltage should not decay to that level if the output capacitor is sized properly. 11.8 • n +V (0 . 26 ) RPL + 6.7 IN where RPL is equal to the external resistor from the PLIM pin to ground and n is the expected efficiency of the converter. The peak current limit is given by: IPK ( A) = 11.8 • n VIN • (RPL + 6.7) + 0 . 26 Constant power gives several advantages over constant current such as lower output ripple. VIN: Input voltage to supply the IC during startup. After the output is running the IC draws power from VOUT or VGD. SD: When this pin is open, the built in 7µA current source pulls up on the pin and programs the IC to go into shutdown mode. This pin requires an open circuit for shutdown and will not operate correctly when driven to a logic level high with TTL or CMOS logic. When this pin is connected to ground, (either directly or with a transistor) the IC is enabled and both output voltages will regulate. VOUT: Main output voltage (3.3V, 5V or adjustable) which has highest priority in the multiplexing scheme, as long as VGD is above the critical level of 7.5V. Loads over 150mA are achievable at 1V input voltage. This output will startup with 1V input at full load. 3 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ APPLICATION INFORMATION A detailed block diagram of the UCC3941 is shown in Fig. 1. Unique control circuitry provides high efficiency power conversion for both light and heavy loads by transitioning between discontinuous and continuous conduction based on load conditions. Fig. 2 depicts converter VIN waveforms for the application circuit shown in Fig. 3. A single 22µH inductor provides the energy pulses required for a highly efficient 3.3V converter at up to 500mW output power. SW 3 8 ANTI-RINGING SWITCH 1 VGD VGD ZERO DETECT 200kHz STARTUP OSCILATOR AND CONTROL VGD 2 VGD + – – + 1.7µS OFF TIME CONTROLLER + 5V VOUT VOUT ZERO DETECT – VGD FROM SD RECTIFIER CONTROL FROM SD 1.4A 5Ω MAX PLIM 5 CLK CURRENT LIMIT D 50mV MAXIMUM – R VSAT SD SD 4 50mV VIN Q L1 + VIN ON TIME CONTROLLER 11µSEC TON= VIN Q SD BOOST LATCH 6 – + Q * R VGD – SD + 6 ** THERMAL SHUTDOWN ** 8.7V FOR UCC3941-3 9.6V FOR UCC3941-5/-ADJ Note: Switches are shown in the logic low state. SGND FOR UCC3941-3/-5 VGD – + * 3.3V FOR UCC3941-3 5.0V FOR UCC3941-5 1.25V FOR UCC3941-ADJ FB FOR UCC3941-ADJ ONLY *** 7 PGND *** 7.7V FOR UCC3941-3 8.8V FOR UCC3941-5/-ADJ UDG-98146 Figure 1. 1V Synchronous boost. 4 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ APPLICATION INFORMATION (cont.) UDG-96117 Figure 2. Inductor current and output ripple waveforms. At time t1, the 3.3V output drops below its lower threshold, and the inductor is charged with an on time determined by: TON = Time t6, represents a transition between light and heavy load. A single energy pulse is not sufficient to force the output voltage above its upper threshold before the minimum off time has expired, and a second charge cycle is commanded. Since the inductor current does not reach zero in this case, the peak current is greater than 0.5A at the end of the next charge on time. The result is a ratcheting of inductor current until either the output voltage is satisfied, or the converter reaches its programmed current limit. At time t7, the gate drive voltage has dropped below its threshold but the converter continues to service the output because it has highest priority, unless VGD drops below 7.5V. 12 µ s VIN For a 1.25V input, and a 22µH inductor, the resulting peak current is approximately 500mA. At time t2, the inductor begins to discharge with a minimum off time of 1.7µs. Under lightly loaded conditions, the amount of energy delivered in this single pulse would satisfy the voltage control loop, and the converter would not command any more energy pulses until the output again drops below the lower voltage threshold. Between t7 and t8, the converter reaches its peak current limit which is determined by RPL and VIN. Once the limit is reached, the converter operates in continuous mode with approximately 200mA of ripple current. At time t8, the output voltage is satisfied, and the converter can service VGD, which occurs at t9. At time t3, the VGD supply has dropped below its lower threshold, but the output voltage is still above its threshold point. This results in an energy pulse to the gate drive supply at t4. However, while the gate drive is being serviced, the output voltage has dropped below its lower threshold, so the state machine commands an energy pulse to the output as soon as the gate drive pulse is completed. 5 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ APPLICATION INFORMATION (cont.) delivered to the load will be less than the peak current set by the power limit function due to current ripple. However, if the ripple component of the current is kept low, the power limit equation can be used as an adequate estimate of input power. Furthermore, since an initial efficiency estimate was required, sufficient margin can be built into this estimate to insure proper converter operation. The 6.2Ω external power limit resister in Fig. 3-5 will result in approximately 700mW of power capability with a Programming the Power Limit The UCC3941 incorporates an adaptive power limit control which modifies the converter current limit as a function of input voltage. In order to program the function, the user simply determines the output power requirements and makes an initial converter efficiency estimate. The programming resistor is chosen by: RPL = POUT 11.8 • n – 6 .7 – 0.26 • n • VBAT Where n is the initial efficiency estimate. For 500mW of output power, with a 1.0V input, and an efficiency estimate of 0.75: RPL = 11.8 (0 .75) 0 .5 – 0 . 26 (0 .75)(1.0) 10µF 8V 2 For decreasing values of RPL, the power limit increases. Therefore, to insure that the converter can supply 500mW of output power, a power limiting resistor of less than 22Ω must be chosen. PL = VBAT MMSZ5240BT1 3 SW 2 VGD VOUT 5.0V AT 500mW 1 UCC3941-5 SD PLIM 5 ADJ 6 PGND 7 RPL 6.2Ω WCR0805-6R207 UDG-98159 Figure 4. Dual output synchronous boost 5V version. +1V TO 3.5V 10µF 3.3V AT 500mW 10V DT3316P-223 22µH MMSZ5240BT1 2 3 8 VIN SW VGD VOUT +1V TO VOUT + 0.5V VOUT=1.25(1+ R1 ) R2 3.3V AT 500mW 1 1 10SN100M 100µF 10µF 10SN100M 100µF 10µF UCC3941-3 R1 UCC3941-3 4 OPEN = SD VOUT VGD OPEN = SD 8 VIN 8V 8 SW 10SN100M 100µF 4 This power limiting setting will support 0.5W of output power. It should be noted that the power limit equation contains an approximation which results in slightly less actual input power than the equation predicts. This discrepancy results from the fact that the average current DT3316P-223 22µH 3 VIN 10µF 11.8 • IL = +1.0 (0 .26) = 0.67W 22 + 6.7 10µF MMSZ5240BT1 – 6 .7 = 22 Ω +1V TO 5.5V DT3316P-223 22µH SD PLIM 4 5 RPL 6.2Ω WCR0805-6R207 SGND 6 PGND 7 OPEN = SD UDG-98163 SD SGND 6 PLIM 5 PGND 7 RPL 6.2Ω WCR0805-6R207 R2 UDG-98164 Figure 5. Dual output synchronous boost ADJ version. Figure 3. Dual output synchronous boost 3.3V version. 6 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ APPLICATION INFORMATION (cont.) (ICL ) • L ∆V = + ICL • CESR 2 • C • (VO − VI ) 2 1.0V input. Inductor Section An inductor value of 22µH will work well in most applications, but values between 10µH and 100µH are also acceptable. Lower value inductors typically offer lower ESR and smaller physical size. Due to the nature of the “bang-bang” controllers, larger inductor values will typically result in larger overall voltage ripple, because once the output voltage level is satisfied the converter goes discontinuous, resulting in the residual energy of inductor causing overshoot.  Power Limit  ICL = the peak inductor current ICL =  VIN   ∆V = output ripple VO = output voltage VI = input voltage CESR = ESR of the output capacitor A Sanyo OS-CON series surface mount capacitor (10SN100M) is one recommendation. This part has an ESR rating of 90mΩ at 100µF. Other potential capacitor sources are shown in Table 2. It is recommended to keep the ESR of the inductor below 0.15Ω for 500mW applications. A Coilcraft DT3316P-223 surface mount inductor is one choice since it has a current rating of 1.5A and an ESR of 84mΩ. Other choices Table 2. Capacitor Suppliers MANUFACTURER Sanyo Video Components San Diego, California Tel: 619-661-6322 Fax: 619-661-1055 AVX Sanford, Maine Tel: 207-282-5111 Fax: 207-283-1941 Sprague Concord, New Hampshire Tel: 603-224-1961 Table 1. Inductor Suppliers MANUFACTURER Coilcraft Cary, Illinois Tel: 708-639-2361 Fax: 708-639-1469 Coiltronics Boca Raton, Florida Tel: 407-241-7876 where PART NUMBERS DT Series CTX Series PART NUMBER OS-CON Series TPS Series 695D Series for surface mount inductors are shown in Table 1. Output Capacitor Selection Input Capacitor Selection Once the inductor value is selected the capacitor value will determine the ripple of the converter. The worst case peak to peak ripple of a cycle is determined by two components, one is due to the charge storage characteristic, and the other is the ESR of the capacitor. The worst case ripple occurs when the inductor is operating at maximum current and is expressed as follows: Since the UCC3941 family does not require a large decoupling capacitor on the input voltage to operate properly, a 10µF capacitor is sufficient for most applications. Optimum efficiency will occur when the capacitor value is large enough to decouple the source impedance. This usually occurs for capacitor values in excess of 100µF. 7 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ VIN = 1.25V VIN = 1.5V VIN= 2V 90 100 80 90 70 80 EFFICIENCY (%) EFFICIENCY (%) VIN = 1V 60 50 40 30 20 VIN= 3V 70 60 50 40 30 20 10 10 0 0 0.1 1 10 0.1 100 IOUT (mA) Figure 6. UCC3941 Efficiency vs. IOUT, VOUT = 3.3V. T0: T 1: T 2: T 3: T 4: VIN= 2.5V 1 IOUT (mA) 10 100 Figure 7. UCC3941 Efficiency vs. IOUT, VOUT = 3.3V. 200kHz startup oscillator starts VGD rising. VGD gets to a sufficient voltage (5V) to run IC in normal operating mode. VGD has reached a sufficient voltage (7.5V) to get VOUT started. VOUT is serviced and starting up. VOUT has reached a sufficient voltage and VGD is serviced until it reaches = 8.5V. Figure 8. Startup characteristics. 8 UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ APPLICATION INFORMATION (cont.) T 1: T 2: T 3: T 4: T 5: VOUT is service and inductor current goes continuous. VGD is serviced with discontinuous operation and reaches 1st threshold (7.5V). VOUT requires servicing so since VGD has at least reached its first threshold of 7.5V the VOUT has priority. VOUT is satisfied and VGD is serviced until 2nd threshold is reached. Both outputs are satisfied. Figure 9. Dual output example. VOUT RIPPLE 20mV/DIV IINDUCTOR CURRENT 0.2A/DIV L = 22 H C = 100 F CVGD = 22 H 20 s/DIV Figure 10. Pseudo continuous mode operation. 9 RPL = 6 VIN = 1.25 IOUT = 100mA UCC2941-3/-5/-ADJ UCC3941-3/-5/-ADJ 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 VSTART (V) VBAT at DROPOUT (V) APPLICATION INFORMATION (cont.) 0 50 100 1.2 1.16 1.12 1.08 1.04 1 0.96 0.92 0.88 0.84 0.8 0 150 50 Figure 11. UCC3941-3 Dropout vs. IOUT. 1V 2.100 1.25V 1.5V 1.75V 2V 3V 1.500 ILIM (A) ILIM (A) 1.700 1.300 1.100 0.900 0.700 0.500 0.300 IL(Rp ) = 2 11.5 4 6 ((6 .1+ RP ) • VBAT ) 8 10 12 RP(Ω) 14 150 Figure 12. Minimum start voltage vs. IOUT. 1.900 0 100 IOUT (mA) IOUT (mA) 16 18 20 1V 2.100 1.900 1.700 1.500 1.300 1.100 0.900 0.700 0.500 0.300 0 IL(Rp ) = +0.2 Figure 13. UCC3941-ADJ ILIM vs. RP (J package only). 1.25V 2 11.8 4 1.5V 6 ((6 .7 + RP ) • VBAT ) 8 1.75V 10 12 RP(Ω) 2V 14 16 + 0 . 26 Figure 14. UCC3941-ADJ ILIM vs. RP (all other packages). UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 Figure 15. VIN startup vs. temp. 10 3V 18 20 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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