Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
UCC53x0 3kVRMS 隔离式单通道栅极驱动器
•
•
•
•
•
•
•
•
•
•
3V 至 15V 输入电源电压
13.2V 至 33V 输出驱动器电源电压
特性选项
– 分离输出（UCC5320S 和 UCC5390S）
– IGBT 发射极采用 UVLO（UCC5320E 和
UCC5390E）
– 米勒钳位选项（UCC5310M 和 UCC5350M）
输入引脚具有负 5V 电压处理能力
UCC5320S、UCC5320E 和 UCC5310M 具有
60ns 传播延迟（典型值）
UCC5390S、UCC5390E 和 UCC5350M 具有
65ns 传播延迟（典型值）
100kV/μs 最小共模瞬态抗扰度 (CMTI)
可承受的隔离浪涌电压：4242VPK
安全相关认证：
– 符合 DIN V VDE V 0884-10 和 DIN EN 610101 标准的 4242 VPK 隔离（计划）
– 符合 UL 1577 标准且长达 1 分钟的 3000 VRMS
隔离（计划）
– CSA 组件验收通知 5A，IEC 60950-1 和 IEC
61010-1 终端设备标准（计划）
– 符合 GB4943.1-2011 标准的 CQC 认证（计
划）
针对所有引脚的 4kV ESD
CMOS 输入
8 引脚窄体 SOIC 封装
工作温度范围：–40°C 至 +125°C 环境
2 应用
•
•
•
•
•
工业电机控制驱动
工业用电源
太阳能逆变器
混合动力汽车 (HEV) 和电动车 (EV) 电源模块
感应加热
3 说明
UCC53x0 是一系列紧凑型单通道隔离式 IGBT、SiC
和 MOSFET 栅极驱动器，具有出色的隔离等级和型
号，适用于引脚排列配置和驱动强度。
UCC53x0 采用 8 引脚 SOIC (D) 封装。该封装具有
4mm 的爬电和余隙，可以支持高达 3kVRMS 的隔离电
压，很适合 需要 基本隔离的应用。基于这些各种不同
的选项和宽电源范围，UCC53x0 系列十分适合电机驱
动和工业电源。
UCC53x0S 选项提供分离输出，可以用于控制驱动器
的上升和下降时间。UCC53x0M 选项将晶体管的栅极
连接到内部钳位，以防止米勒电流造成假接通。
UCC53x0E 选项的 UVLO2 以 GND2 为基准，方便了
双极供电。
与光耦合器不同，UCC53x0 系列的部件间偏移更低，
传播延迟更小，工作温度更高，并且 CMTI 更大。
器件信息(1)
最低拉电流和灌
电流
说明
UCC5310M
2.4A 和 1.1A
米勒钳位
UCC5320S
2.4A 和 2.2A
分离输出
UCC5320E
2.4A 和 2.2A
UVLO 以 IGBT 发射极为基
准
UCC5350M
5A 和 5A
米勒钳位
UCC5390S
10A 和 10A
分离输出
UCC5390E
10A 和 10A
UVLO 以 IGBT 发射极为基
准
器件型号
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 有关器件的详细比较，请参见
器件比较表
功能框图（S 版本）
5V
VCC2
VCC1
15 V
VCC2
IN+
IN±
GND1
UVLO
and
Input
Logic
BARRIER
•
•
•
1
ISOLATION
1 特性
Rest of
Circuit
UVLO,
Level
Shift
and
text
Control
Logic
VOUTH
VOUTL
VEE2
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSER8
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics........................................... 9
Switching Characteristics ...................................... 10
Insulation Characteristics Curves ......................... 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 15
8.1 Propagation Delay, Inverting, and Noninverting
Configuration............................................................ 15
9
Detailed Description ............................................ 18
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
20
24
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ............................................... 27
11 Power Supply Recommendations ..................... 33
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 Layout Example .................................................... 35
12.3 PCB Material ......................................................... 37
13 器件和文档支持 ..................................................... 38
13.1
13.2
13.3
13.4
13.5
13.6
13.7
文档支持................................................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
38
38
38
38
38
38
38
14 机械、封装和可订购信息 ....................................... 39
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2017) to Revision B
Page
•
已更改 最低环境工作温度为 -55°C 至 -40°C .......................................................................................................................... 1
•
已添加 将 UCC5350 和 UCC5390 器件添加到了数据表 ........................................................................................................ 1
Changes from Original (June 2017) to Revision A
Page
•
已删除 从标题中删除了可用于未来 10A 器件的 17A 规格...................................................................................................... 1
2
Copyright © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
5 Device Comparison Table
DEVICE OPTION (1)
MINIMUM SOURCE
CURRENT
MINIMUM SINK
CURRENT
PIN CONFIGURATION
ISOLATION RATING (2)
UCC5310M
2.4 A
1.1 A
Miller clamp
3 kVRMS
UCC5320E
2.4 A
2.2 A
UVLO with reference to GND2
3 kVRMS
UCC5320S
2.4 A
2.2 A
Split output
3 kVRMS
UCC5350M
5A
5A
Miller clamp
3 kVRMS
UCC5390E
10 A
10 A
UVLO with reference to GND2
3 kVRMS
UCC5390S
10 A
10 A
Split output
3 kVRMS
(1)
(2)
The S, E, and M suffixes are part of the orderable part number. See the 机械、封装和可订购信息 section for the full orderable part
number.
For detailed isolation ratings, see the Insulation Specifications table.
Copyright © 2017, Texas Instruments Incorporated
3
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
6 Pin Configuration and Function
UCC5320S and UCC5390S D Package
8-Pin SOIC
Top View
UCC5310M and UCC5350M D Package
8-Pin SOIC
Top View
VCC1
1
8
VEE2
OUTL
IN+
2
7
CLAMP
6
OUTH
IN±
3
6
OUT
5
VCC2
GND1
4
5
VCC2
VCC1
1
8
VEE2
IN+
2
7
IN±
3
GND1
4
Not to scale
Not to scale
UCC5320E and UCC5390E D Package
8-Pin SOIC
Top View
VCC1
1
8
VEE2
IN+
2
7
GND2
IN±
3
6
OUT
GND1
4
5
VCC2
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
UCC53x0S
UCC53x0M
UCC53x0E
CLAMP
—
7
—
I
Active Miller-clamp input found on the UCC5310M and UCC5350M used to
prevent false turnon of the power switches.
GND1
4
4
4
G
Input ground. All signals on the input side are referenced to this ground.
GND2
—
—
7
G
Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO
referenced to GND2 in the UCC5320E and UCC5390E variations.
IN+
2
2
2
I
Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS
input threshold. This pin is pulled low internally if left open. Use 表 4 to
understand the input and output logic of these devices.
IN–
3
3
3
I
Inverting gate-drive voltage control input. The IN– pin has a CMOS input
threshold. This pin is pulled high internally if left open. Use 表 4 to
understand the input and output logic of these devices.
OUT
—
6
6
O
Gate-drive output for E and M versions.
OUTH
6
—
—
O
Gate-drive pullup output found on the UCC5320S and UCC5390S.
OUTL
7
—
—
O
Gate-drive pulldown output found on the UCC5320S and UCC5390S.
VCC1
1
1
1
P
Input supply voltage. Connect a locally decoupled capacitor to GND. Use a
low-ESR or ESL capacitor located as close to the device as possible.
VCC2
5
5
5
P
Positive output supply rail. Connect a locally decoupled capacitor to VEE2.
Use a low-ESR or ESL capacitor located as close to the device as possible.
VEE2
8
8
8
P
Negative output supply rail for E version, and GND for S and M versions.
Connect a locally decoupled capacitor to GND2 for E version. Use a lowESR or ESL capacitor located as close to the device as possible.
(1)
4
P = Power, G = Ground, I = Input, O = Output
Copyright © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
GND1 – 0.3
18
V
VCC2 – VEE2
–0.3
35
V
VEE2 – GND2
–17.5
0.3
V
VOUTH – VEE2, VOUTL – VEE2, VOUT – VEE2, VCLAMP – VEE2
VEE2 – 0.3
VCC2 + 0.3
V
VIN+ – GND1, VIN– – GND1
GND1 – 5
VCC1 + 0.3
V
–40
150
°C
150
°C
Input bias pin supply voltage
VCC1 – GND1
Driver bias supply
VEE2 bipolar supply voltage for
E version
Output signal voltage
Input signal voltage
Junction temperature, TJ (2)
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS–001
(1)
UNIT
±4000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC1
Supply voltage, input side
3
15
V
VCC2
Positive supply voltage output side (VCC2 – VEE2)
13.2
33
V
VEE2
Bipolar supply voltage for E version (VEE2 – GND2)
–16
0
V
VSUP2
Total supply voltage output side (VCC2 – VEE2)
13.2
33
V
TA
Ambient temperature
–40
125
°C
Copyright © 2017, Texas Instruments Incorporated
5
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
7.4 Thermal Information
UCC53x0
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction–to-ambient thermal resistance
109.5
°C/W
RθJC(top)
Junction–to-case (top) thermal resistance
43.1
°C/W
RθJB
Junction–to-board thermal resistance
51.2
°C/W
ΨJT
Junction–to-top characterization parameter
18.3
°C/W
ΨJB
Junction–to-board characterization parameter
50.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
MAX
UNIT
PD
VCC1 = 5 V, VCC2 = 15 V, IN+ = 3.3 V,
Maximum power dissipation on input and
IN– = GND1, 687-kHz, 50% duty cycle,
output
square wave, 2.4-nF load
1.14
W
PD1
Maximum input power dissipation
VCC1 = 5 V, VCC2 = 15 V, IN+ = 3.3 V,
IN– = GND1, 687-kHz, 50% duty cycle,
square wave, 2.4-nF load
0.05
W
PD2
Maximum output power dissipation
VCC1 = 5 V, VCC2 = 15 V, IN+ = 3.3 V,
IN– = GND1, 687-kHz, 50% duty cycle,
square wave, 2.4-nF load
1.09
W
6
TEST CONDITIONS
MIN
TYP
Copyright © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
7.6 Insulation Specifications
PARAMETER
VALUE
UNIT
Shortest pin–to-pin distance through air
TEST CONDITIONS
4
mm
Shortest pin–to-pin distance across the package
surface
4
mm
Minimum internal gap (internal clearance)
> 21
µm
DIN EN 60112 (VDE 0303–11); IEC 60112
> 600
V
CLR
External Clearance (1)
CPG
External Creepage
(1)
DTI
Distance through the insulation
CTI
Comparative tracking index
Material Group
According to IEC 60664–1
Overvoltage category per IEC 60664-1
I
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
DIN V VDE 0884–10 (VDE V 0884–10): 2016–2012 (2)
VIORM
Maximum repetitive peak isolation
voltage
AC voltage (bipolar)
990
VPK
VIOWM
Maximum isolation working voltage
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test
700
VRMS
990
VDC
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM
t = 60 s (qualification)
t = 1 s (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM (qualification)
4242
VPK
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Isolation resistance, input to output (5)
RIO
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.3 × VIORM, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM, tm = 1 s
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
1.2
VIO = 500 V, TA = 25°C
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V, TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO= 3000 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3600 VRMS , t = 1 s
(100% production)
3000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
Copyright © 2017, Texas Instruments Incorporated
7
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to DIN V VDE
V 0884–10 (VDE V
0884–10):2006–12 and DIN EN
61010-1 (VDE 0411-1):2011-07
Plan to certify according CSA
Component Acceptance Notice
5A, IEC 60950–1 and IEC
61010-1
Plan to certify according to UL
1577 Component Recognition
Program
Plan to certify according to GB
4943.1–2011
Basic Insulation Maximum
Transient isolation Overvoltage,
4242 VPK;
Maximum Repetitive Peak
Voltage, 990 VPK;
Maximum Surge Isolation
Voltage, 4242 VPK
Basic insulation and Reinforced
insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd
Ed.+A1+A2; Basic insulation
working voltage per CSA 610101-12 and IEC 61010-1 3rd Ed.
Single protection, 3000 VRMS
Basic Insulation, Altitude ≤ 5000
m, Tropical Climate, 250V RMS
maximum working voltage
Certification planned
Certification planned
Certification planned
Certification planned
7.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
D PACKAGE
IS
PS
TS
(1)
8
Safety output supply
current
Safety output supply
power
Maximum safety
temperature
RθJA = 109.5°C/W, VCC2 = 15 V, TJ = 150°C, TA = 25°C,
see 图 1
Output side
76
RθJA = 109.5°C/W, VCC2 = 30 V, TJ = 150°C, TA = 25°C,
see 图 1
Output side
38
RθJA = 109.5°C/W, TJ = 150°C, TA = 25°C, see 图 2
mA
Input side
0.05
Output side
1.09
Total
1.14
150
W
°C
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
Copyright © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
7.9 Electrical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA = –40°C to
+125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCC1
Input supply quiescent current
IN+ and IN- left floating
1.67
2.4
mA
IVCC2
Output supply quiescent
current
IN+ and IN- left floating
1.1
1.8
mA
2.6
2.8
V
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1)
VCC1 Positive-going UVLO
threshold voltage
VIT– (UVLO1)
VCC1 Negative-going UVLO
threshold voltage
Vhys(UVLO1)
2.4
2.5
V
VCC1 UVLO threshold
hysteresis
0.1
V
VIT+(UVLO2)
VCC2 Positive-going UVLO
threshold voltage
12
VIT–(UVLO2)
VCC2 Negative-going UVLO
threshold voltage
Vhys(UVLO2)
VCC2 UVLO threshold voltage
hysteresis
10.3
13
V
11
V
1
V
LOGIC I/O
VIT+(IN)
Positive-going input threshold
voltage (IN+, IN–)
VIT–(IN)
Negative-going input threshold
voltage (IN+, IN–)
Vhys(IN)
Input hysteresis voltage (IN+,
IN–)
IIH
High-level input leakage at IN+ IN+ = VCC1
IIL
Low-level input leakage at IN–
0.3 × VCC1
0.55 × VCC1 0.7 × VCC1
V
0.45 × VCC1
V
0.1 × VCC1
V
40
IN– = GND1
–240
–40
IN– = GND1 – 5 V
–310
–80
VCC2 – 0.1
VCC2 – 0.24
9.4
13
17
26
2
3
5
7
UCC5320S and UCC5320E,
IN+ = high, IN– = low
2.4
4.3
UCC5310M, IN+ = high, IN– = low
2.4
4.3
UCC5390S and UCC5390E,
IN+ = high, IN– = low
10
17
5
10
240
µA
µA
GATE DRIVER STAGE
VOH
High-level output voltage
(OUT and OUTH)
IOUT = –20 mA
UCC5320S and UCC5320E,
IN+ = low, IN– = high; IO = 20 mA
VOL
UCC5310M,
Low level output voltage (OUT IN+ = low, IN– = high; IO = 20 mA
and OUTL)
UCC5390S and UCC5390E,
IN+ = low, IN– = high; IO = 20 mA
UCC5350M,
IN+ = low, IN– = high; IO = 20 mA
IOH
Peak source current
UCC5350M,
IN+ = high, IN– = low
Copyright © 2017, Texas Instruments Incorporated
V
mV
A
9
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Electrical Characteristics (continued)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA = –40°C to
+125°C, (unless otherwise noted)
PARAMETER
IOL
Peak sink current
MIN
TYP
UCC5320S and UCC5320E,
IN+ = low, IN– = high
TEST CONDITIONS
2.2
4.4
UCC5310M, IN+ = low, IN– = high
1.1
2.2
UCC5390S and UCC5390E,
IN+ = low, IN– = high
10
17
5
10
UCC5350M,
IN+ = low, IN– = high
MAX
UNIT
A
ACTIVE MILLER CLAMP (UCC53xxM only)
UCC5310M, ICLAMP = 20 mA
26
50
UCC5350M, ICLAMP = 20 mA
7
10
VCLAMP
Low-level clamp voltage
ICLAMP
Clamp low-level current
ICLAMP(L)
Clamp low-level current for
low output voltage
VCLAMP-TH
Clamp threshold voltage
UCC3510M and UCC5350M
UCC5310M, VCLAMP = VEE2 + 15 V
1.1
2.2
UCC5350M, VCLAMP = VEE2 + 15 V
5
10
UCC5310M, VCLAMP = VEE2 + 2 V
0.7
1.5
UCC5350M, VCLAMP = VEE2 + 2 V
5
10
mV
A
A
2.1
2.3
V
IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUTH or IOUT= 500 mA
1
1.3
V
IN+ = low, IN– = high, tCLAMP = 10 µs,
ICLAMP or IOUTL = –500 mA
1.5
IN+ = low, IN– = high,
ICLAMP or IOUTL = –20 mA
0.9
1
UCC5320S, UCC5320E, and UCC5310M
IOUTL or IOUT = 0.1 × IOUTL(typ), VCC2 =
open
1.8
2.5
SHORT CIRCUIT CLAMPING
VCLP-OUT
Clamping voltage
(VOUTH – VCC2 or VOUT –VCC2)
VCLP-OUT
Clamping voltage
(VEE2 – VOUTL or VEE2 –
VCLAMP or VEE2 – VOUT)
V
ACTIVE PULLDOWN
VOUTSD
Active pulldown voltage on
OUTL, CLAMP, OUT
V
7.10 Switching Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA = –40°C to
+125°C, (unless otherwise noted)
PARAMETER
tr
tf
tPLH
tPHL
Output-signal rise time
Output-signal fall time
Propagation delay
(default versions), high
Propagation delay
(default versions), low
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UCC5320S, UCC5320E, and UCC5310M,
CLOAD = 1 nF
12
28
ns
UCC5390S, UCC5390E, and UCC5350M,
CLOAD = 1 nF
10
26
ns
UCC5320S and UCC5320E, CLOAD = 1 nF
10
25
ns
UCC5310M, CLOAD = 1 nF
10
26
ns
UCC5390S, UCC5390E, and UCC5350M,
CLOAD = 1 nF
10
22
ns
UCC5320S and UCC5320E, CLOAD = 100 pF
60
72
ns
UCC5310M, CLOAD = 100 pF
60
75
ns
UCC5390S, UCC5390E, and UCC5350M,
CLOAD = 100 pF
65
100
ns
UCC5320S and UCC5320E, CLOAD = 100 pF
60
75
ns
UCC5310M, CLOAD = 100 pF
60
75
ns
UCC5390S, UCC5390E, and UCC5350M,
CLOAD = 100 pF
65
100
ns
tUVLO1_rec
UVLO recovery delay of VCC1
30
µs
tUVLO2_rec
UVLO recovery delay of VCC2
50
µs
10
Copyright © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Switching Characteristics (continued)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA = –40°C to
+125°C, (unless otherwise noted)
PARAMETER
Pulse width distortion
|tPHL – tPLH|
tPWD
Part-to-part skew (1)
tsk(pp)
Common-mode transient
immunity
CMTI
(1)
TYP
MAX
UCC5320S and UCC5320E, CLOAD = 100 pF
TEST CONDITIONS
MIN
1
20
ns
UCC5310M, CLOAD = 100 pF
1
20
ns
UCC5390S and UCC5390E, CLOAD = 100 pF
1
20
ns
UCC5350M, CLOAD = 100 pF
1
20
ns
UCC5320S and UCC5320E, CLOAD = 100 pF
1
25
ns
UCC5310M, CLOAD = 100 pF
1
25
ns
UCC5390S and UCC5390E, CLOAD = 100 pF
1
25
ns
UCC5350M, CLOAD = 100 pF
1
25
ns
PWM is tied to GND or VCC1, VCM = 1200 V
100
120
UNIT
kV/µs
tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.
7.11 Insulation Characteristics Curves
105
1600
VCC2 = 15 V
VCC2 = 30 V
1400
Safety Limiting Power (mW)
Safety Limiting Current (mA)
90
75
60
45
30
15
1200
1000
800
600
400
200
0
0
50
100
150
Ambient Temperature (°C)
200
250
D001
图 1. Thermal Derating Curve for Limiting Current per VDE
版权 © 2017, Texas Instruments Incorporated
0
0
50
100
150
Ambient Temperature (°C)
200
250
图 2. Thermal Derating Curve for Limiting Power per VDE
11
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
7.12 Typical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA =
–40°C to +125°C, (unless otherwise noted)
24
8
UCC5320S
UCC5310M
UCC5320E
7.2
UCC5390S
UCC5350M
UCC5390E
22
Output-High Drive Current (A)
Output-High Drive Current (A)
7.6
6.8
6.4
6
5.6
5.2
4.8
20
18
16
14
12
10
4.4
4
14
16
18
20
22
24
26
28
30
Output-Side Supply Voltage (V)
32
8
14
34
16
18
D010
20
22
24
26
28
30
Output-Side Supply Voltage (V)
CLOAD = 150 nF
34
D019
CLOAD = 150 nF
图 3. Output-High Drive Current vs Output Voltage
图 4. Output-High Drive Current vs Output Voltage
24
8.5
7.5
Output-Low Drive Current (A)
UCC5320S
UCC5310M
UCC5320E
8
Output-Low Drive Current (A)
32
7
6.5
6
5.5
5
4.5
4
UCC5390S
UCC5350M
UCC5390E
22
20
18
16
14
12
3.5
3
14
16
18
20
22
24
26
28
30
Output-Side Supply Voltage (V)
32
10
14
34
16
18
D011
20
22
24
26
28
30
Output-Side Supply Voltage (V)
CLOAD = 150 nF
图 5. Output-Low Drive Current vs Output Voltage
图 6. Output-Low Drive Current vs Output Voltage
2.275
Input-Side Supply Current (mA)
Input-Side Supply Current (mA)
UCC5320S
UCC5320E
UCC5310M
1.18
1.16
1.14
1.12
1.1
2.25
UCC5320S
UCC5320E
UCC5310M
2.225
2.2
2.175
2.15
2.125
2.1
2.075
-40
-20
IN+ = L
0
20
40
60
80
Temperature (qC)
100
120
IN– = H
图 7. ICC1 Supply Current vs Temperature
12
D020
2.3
1.2
1.08
-60
34
CLOAD = 150 nF
1.24
1.22
32
140
2.05
-60
-40
-20
D004
IN+ = H
0
20
40
60
80
Temperature (qC)
100
120
140
D005
IN– = L
图 8. ICC1 Supply Current vs Temperature
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Typical Characteristics (接
接下页)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA =
–40°C to +125°C, (unless otherwise noted)
1.685
1.25
Output-Side Supply Current (mA)
Input-Side Supply Current (mA)
1.68
1.675
1.67
UCC5320S
UCC5320E
UCC5310M
1.665
1.66
1.655
1.65
1.645
1.64
1.635
1.63
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (MHz)
Duty Cycle = 50%
0.8
0.9
1.2
1.15
1.1
1.05
1
0.95
0.9
0.85
-60
1
T = 25°C
-20
Duty Cycle = 50%
0
20
40
60
80
Temperature (qC)
100
120
140
D007
IN+ = L
IN– = H
图 10. ICC2 Supply Current vs Temperature
1.14
1.45
UCC5320S
UCC5320E
UCC5310M
1.4
1.35
Output-Side Supply Current (mA)
Output-Side Supply Current (mA)
-40
D006
图 9. ICC1 Supply Current vs Input Frequency
1.3
1.25
1.2
1.15
1.1
1.05
1
-60
-40
-20
0
Duty Cycle = 50%
20
40
60
80
Temperature (qC)
100
120
UCC5320S
UCC5320E
UCC5310M
1.12
1.1
1.08
1.06
1.04
0.1
140
0.2
0.3
D008
IN+ = H
0.4
0.5
0.6
0.7
Frequency (MHz)
0.8
0.9
1
D009
IN– = L
图 11. ICC2 Supply Current vs Input Frequency
图 12. ICC2 Supply Current vs Input Frequency
18
1.375
UCC5320S
UCC5310M
UCC5320E
1.35
1.325
16
14
1.3
1.275
Rise Time (ns)
Output-Side Supply Current (mA)
UCC5320S
UCC5320E
UCC5310M
1.25
1.225
1.2
1.175
12
10
8
6
1.15
1.125
UCC5320S
UCC5310M
UCC5320E
4
1.1
2
1.075
0
1
2
3
4
5
6
7
Load Capacitance (nF)
8
9
fSW = 1 kHz
图 13. ICC2 Supply Current vs Load Capacitance
版权 © 2017, Texas Instruments Incorporated
10
0
0.1
0.2
D014
fSW = 1 kHz
0.3 0.4 0.5 0.6 0.7
Load Capacitance (nF)
0.8
0.9
RGH = 0 Ω
1
D012
RGL = 0 Ω
图 14. Rise Time vs Load Capacitance
13
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Typical Characteristics (接
接下页)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA =
–40°C to +125°C, (unless otherwise noted)
18
28
16
26
12
Rise Time (ns)
Fall Time (ns)
14
10
8
6
4
UCC5320S
UCC5310M
UCC5320E
2
24
22
20
UCC5320S
UCC5310M
UCC5320E
18
0
16
0
0.1
0.2
fSW = 1 kHz
0.3 0.4 0.5 0.6 0.7
Load Capacitance (nF)
0.8
0.9
1
0
0.1
0.2
D013
RGH = 0 Ω
RGL = 0 Ω
0.3 0.4 0.5 0.6 0.7
Load Capacitance (nF)
fSW = 1 kHz
图 15. Fall Time vs Load Capacitance
RGH = 11 Ω
0.8
0.9
1
D016
RGL = 11 Ω
图 16. Rise Time vs Load Capacitance
18.8
UCC5320S
UCC5310M
UCC5320E
18.6
18.4
Fall Time (ns)
18.2
18
17.8
17.6
17.4
17.2
17
16.8
16.6
0
0.1
0.2
fSW = 1-kHz
0.3 0.4 0.5 0.6 0.7
Load Capacitance (nF)
RGH = 11 Ω
0.8
0.9
1
D018
RGL = 11 Ω
图 17. Fall Time vs Load Capacitance
14
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
8 Parameter Measurement Information
8.1 Propagation Delay, Inverting, and Noninverting Configuration
图 18 shows the propagation delay OUTH and OUTL for noninverting configurations. 图 19 shows the
propagation delay with the inverting configuration. These figures also demonstrate the method used to measure
the rise (tr) and fall (tf) times.
0V
IN±
50%
tf
tr
IN+
90%
50%
OUTH
OUTL
10%
tPLH
tPHL
图 18. OUTH and OUTL Propagation Delay, Noninverting Configuration
IN±
50%
IN+
tf
tr
90%
50%
OUTH
OUTL
10%
tPLH
tPHL
图 19. OUTH and OUTL Propagation Delay, Inverting Configuration
版权 © 2017, Texas Instruments Incorporated
15
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Propagation Delay, Inverting, and Noninverting Configuration (接
接下页)
8.1.1 CMTI Testing
图 20, 图 21, and 图 22 are simplified diagrams of the CMTI testing configuration used for each device type.
15 V
5V
VCC2
VCC1
C2
GND1
PWM
C3
ISOLATION BARRIER
C1
IN+
C4
OUTH
OUTL
IN±
VEE2
+
VCM
±
Copyright © 2017, Texas Instruments Incorporated
图 20. CMTI Test Circuit for UCC5320S and UCC5390S
15 V
5V
VCC2
VCC1
C2
GND1
PWM
C3
ISOLATION BARRIER
C1
IN+
C4
OUT
CLAMP
IN±
VEE2
+
VCM
±
Copyright © 2017, Texas Instruments Incorporated
图 21. CMTI Test Circuit for UCC5310M and UCC5350M
16
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Propagation Delay, Inverting, and Noninverting Configuration (接
接下页)
15 V
5V
VCC2
VCC1
C2
GND1
PWM
C3
ISOLATION BARRIER
C1
IN+
C4
OUT
GND2
IN±
VEE2
+
VCM
±
Copyright © 2017, Texas Instruments Incorporated
图 22. CMTI Test Circuit for UCC5320E and UCC5390E
版权 © 2017, Texas Instruments Incorporated
17
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
9 Detailed Description
9.1 Overview
The UCC53x0 family of isolated gate drivers with variations for built-in split output, Miller clamp, and UVLO2
referenced to GND2 (see Device Comparison Table). The isolation inside the UCC53x0 family of devices is
implemented with high-voltage SiO2-based capacitors. The signal across the isolation has an on-off keying
(OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier (see 图 24).
The transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no
signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning
and produces the output through a buffer stage. The UCC53x0 devices also incorporate advanced circuit
techniques to maximize the CMTI performance and minimize the radiated emissions from the high frequency
carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图 23, shows a
functional block diagram of a typical channel. 图 24 shows a conceptual detail of how the OOK scheme works.
图 23 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK) and
signal conditioning. 图 24 shows the OOK-based modulation scheme.
9.2 Functional Block Diagram
Transmitter
TX IN
Receiver
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2017, Texas Instruments Incorporated
图 23. Conceptual Block Diagram of a Capacitive Data Channel
TX IN
Carrier signal through
isolation barrier
RX OUT
图 24. On-Off Keying (OOK) Based Modulation Scheme
18
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Functional Block Diagram (接
接下页)
IN+
VCC2
UVLO2
UVLO1
VCC2
BARRIER
VCC1
Level
Shifting
and
Control
Logic
OUTH
ISOLATION
OUTL
IN±
GND1
VEE2
图 25. Functional Block Diagram—UCC5320S and UCC5390S Split Outputs
VCC2
Level
Shifting
and
Control
Logic
OUT
ISOLATION
IN+
VCC2
UVLO2
UVLO1
BARRIER
VCC1
IN±
CLAMP
2V
GND1
VEE2
图 26. Functional Block Diagram—UCC5310M and UCC5350 Miller Clamp
版权 © 2017, Texas Instruments Incorporated
19
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Functional Block Diagram (接
接下页)
VCC1
BARRIER
VCC2
Level
Shifting
and
Control
Logic
ISOLATION
IN+
VCC2
UVLO2
UVLO1
IN±
OUT
GND2
GND1
VEE2
图 27. Functional Block Diagram—UCC5320E and UCC5390E UVLO With Respect to GND2
9.3 Feature Description
9.3.1 Power Supply
The VCC1 input power supply supports a wide voltage range from 3 V to 15 V and the VCC2 output supply
supports a voltage range from 13.2 V to 33 V. For operation with bipolar supplies, the power device is turned off
with a negative voltage on the gate with respect to the emitter or source. This configuration prevents the power
device from unintentionally turning on because of current induced from the Miller effect. The typical values of the
VCC2 and VEE2 output supplies for bipolar operation are 15 V and –8 V with respect to GND2 for IGBTs, and 20 V
and –5 V for SiC MOSFETs.
For operation with unipolar supply, the VCC2 supply is connected to 15 V with respect to GND2 for IGBTs, and 20
V for SiC MOSFETs. The VEE2 supply is connected to 0 V. In this use case, the UCC53x0 device with Miller
clamping function (UCC53x0M) can be used. The Miller clamping function is implemented by adding a low
impedance path between the gate of the power device and the VEE2 supply. Miller current can sink and the gate
voltage is clamped to be lower than the turnon threshold value for the gate.
9.3.2 Input Stage
The input pins (IN+ and IN–) of UCC53x0 family are based on CMOS-compatible input-threshold logic that is
completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals
(such as those from 3.3-V microcontrollers) because the UCC53x0 family has a typical high threshold (VIT+(IN)) of
0.56 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good
noise immunity and stable operation. If any of the inputs are left open, 128 kΩ of internal pulldown resistance
forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding
an input if it is not being used for improved noise immunity.
Because the input side of the UCC53x0 family is isolated from the output driver, the input signal amplitude can
be larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows
greater flexibility when integrating the gate-driver with control signal sources, and allows the user to choose the
most efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a
voltage higher than VCC1.
20
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Feature Description (接
接下页)
9.3.3 Output Stage
The output stages of the UCC53x0 family feature a pullup structure that delivers the highest peak-source current
when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the
power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a Pchannel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turnon. Fast turnon is
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing
states from low to high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 4.5 Ω when
activated. 表 1 lists the typical internal-resistance values of the pullup and pulldown structure.
表 1. UCC53x0 On-Resistance
DEVICE OPTION
RNMOS
ROH
ROL
RCLAMP
UNIT
UCC5320S and UCC5320E
4.5
12
0.65
Not applicable
Ω
UCC5310M
4.5
12
1.3
1.3
Ω
UCC5390S and UCC5390E
0.76
12
0.13
Not applicable
Ω
UCC5350M
1.54
12
0.26
0.26
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device
only. This parameter is only for the P-channel device because the pullup N-channel device is held in the OFF
state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.
Therefore, the effective resistance of the UCC53x0 pullup stage during this brief turnon phase is much lower than
what is represented by the ROH parameter, yielding a faster turnon. The turnon-phase output resistance is the
parallel combination ROH || RNMOS.
The pulldown structure in the UCC53x0 S and E versions is simply composed of an N-channel MOSFET. For the
M version, an additional FET is connected in parallel with the pulldown structure when the CLAMP and OUT pins
are connected to the gate of the IGBT or MOSFET. The output of the UCC53x0 family is capable of delivering, or
sinking, 2-A, 5-A and 10-A peak current pulses. The output voltage swing between VCC2 and VEE2 provides railto-rail operation because of the MOS-out stage which delivers very low dropout.
UVLO2
Level
Shifting
and
Control
Logic
VCC2
ROH
RNMOS
OUTH
OUTL
ROL
VEE2
图 28. Output Stage—S Version
版权 © 2017, Texas Instruments Incorporated
21
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
UVLO2
VCC2
ROH
Level
Shifting
and
Control
Logic
RNMOS
OUT
ROL
GND2
VEE2
图 29. Output Stage—E Version
UVLO2
VCC2
ROH
Level
Shifting
and
Control
Logic
RNMOS
OUT
ROL
CLAMP
2V
VEE2
图 30. Output Stage—M Version
9.3.4 Protection Features
9.3.4.1 Undervoltage Lockout (UVLO)
UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2
and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO)
at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected
output low, regardless of the input pins (IN+ and IN–) as shown in 表 4. The VCC1 UVLO protection has a
hysteresis feature (Vhys(UVLO1)). This hysteresis prevents chatter when the power supply produces ground noise
which allows the device to permit small drops in bias voltage, which occurs when the device starts switching and
operating current consumption increases suddenly. 图 31 shows the UVLO functions.
表 2. UCC53x0 VCC1 UVLO Logic
CONDITION
VCC1 – GND1 < VIT+(UVLO1) during device start-up
22
INPUTS
OUTPUTS
IN+
IN–
OUT, OUTH
OUTL
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
表 2. UCC53x0 VCC1 UVLO Logic (接
接下页)
INPUTS
CONDITION
IN+
VCC1 – GND1 < VIT–(UVLO1) during device start-up
OUTPUTS
IN–
OUT, OUTH
OUTL
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
IN–
OUT, OUTH
OUTL
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
表 3. UCC53x0 VCC2 UVLO Logic
INPUTS
CONDITION
IN+
VCC2 – VEE2 < VIT+(UVLO2) during device start-up
VCC2 – VEE2 < VIT–(UVLO2) during device start-up
OUTPUTS
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is
resistively held off by a pullup resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ
resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device
which is typically less than 1.5 V when no bias power is available.
When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the
output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. 图 31 and 图 32 show this delay.
IN+
VCC1
IN+
VIT±(UVLO1)
VIT+ (UVLO1)
VCC1
VCC2
VCC2
tUVLO1_rec
VIT+ (UVLO2)
VIT± (UVLO2)
tUVLO2_rec
VOUT
VOUT
图 31. UVLO1 Functions
图 32. UVLO2 Functions
版权 © 2017, Texas Instruments Incorporated
23
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
9.3.4.2 Active Pulldown
The active pulldown function is used to pull the IGBT or MOSFET gate to the low state when no power is
connected to the VCC2 supply. This feature prevents false IGBT and MOSFET turnon on the OUT, OUTL, and
CLAMP pins by clamping the output to approximately 2 V.
9.3.4.3 Short-Circuit Clamping
The short-circuit clamping function is used to clamp voltages at the driver output and pull the active Miller clamp
pins slightly higher than the VCC2 voltage during short-circuit conditions. The short-circuit clamping function helps
protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping
function is implemented by adding a diode connection between the dedicated pins and the VCC2 pin inside the
driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of
20 mA. Use external Schottky diodes to improve current conduction capability as needed.
9.3.4.4 Active Miller Clamp (UCC53x0M)
The active Miller-clamp function is used to prevent false turnon of the power switches caused by Miller current in
applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding a
low impedance path between the power-switch gate terminal and ground (VEE2) to sink the Miller current. With
the Miller-clamp function, the power-switch gate voltage is clamped to less than 2 V during the off state. 图 36
shows a typical application circuit of UCC5310M and UCC5350M.
9.4 Device Functional Modes
表 4 lists the functional modes for the UCC53x0 devices.
表 4. Function Table (1)
(1)
24
VCC1
VCC2
IN+
IN–
OUTH, OUTL
PU
PD
X
X
Low
PD
PU
X
X
Low
PU
PU
Low
X
Low
PU
PU
X
High
Low
PU
PU
High
Low
High
PU = Powered up (VCC1 ≥ 2.8 V or VCC2 ≥ 13 V); PD = Powered down (VCC1 ≤ 2.4 V or VCC2 ≤ 10.3 V); X = Irrelevant
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
9.4.1 Device I/O
图 33 shows the input and output structure of the UCC53x0 family of isolated gate drivers.
Input
VCC1
VCC1
VCC1
VCC1
1.5 M
985
INx
Output
VCC2
~20
OUTx
图 33. Device Input and Output Structure
版权 © 2017, Texas Instruments Incorporated
25
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
9.4.2 ESD Structure
图 34 shows the multiple diodes involved in the ESD protection components of the UCC53x0 family. This
provides pictorial representation of the absolute maximum rating for the device.
IN+
2
IN±
3
VCC1
VCC2
1
5
20 V
6
OUT
OUTH
7
OUTL
GND2
CLAMP
40 V
5.5 V
4
8
GND1
VEE2
图 34. ESD Structure
26
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCC53x0 is a family of simple, isolated gate drivers for power semiconductor devices, such as MOSFETs,
IGBTs, or SiC MOSFETs. The family of devices is intended for use in applications such as motor control,
industrial inverters, and switched-mode power supplies.
The UCC53x0 family of devices has three pinout configurations, featuring split outputs, Miller clamp, and UVLO
with reference to GND2. The UCC5320S and UCC5390S has two outputs, which are OUTH and OUTL. The two
outputs can be used to separately decouple the power transistor turnon and turnoff commutations. The
UCC5310M and UCC5350M feature active Miller clamping, which can be used to prevent false turnon of the
power transistors induced by the Miller current. The UCC5320E and UCC5390E offer true UVLO protection by
monitoring the voltage between the VCC2 and GND2 pins to prevent the power transistors from operating in a
saturation region. The UCC53x0 family of devices comes in an 8-pin D package option and has a creepage, or
clearance, of 4 mm, which is suitable for applications where basic isolation is required. Different drive strengths
enable a simple driver platform to be used for applications demanding power transistors with different power
ratings. Specifically, the UCC5390 device offers a 10-A drive current which can help remove the external current
buffer used to drive high power transistors.
10.2 Typical Application
The circuits in 图 35, 图 36, and 图 37 show a typical application for driving IGBTs.
15 V
VCC2
5V
C3
VCC1
C1
C4
C2
GND1
RGON
OUTH
PWM
RGOFF
IN+
Signal Emitter
OUTL
IN±
VEE2
Power Emitter
Copyright © 2017, Texas Instruments Incorporated
图 35. Typical Application Circuit for UCC5320S and UCC5390S to Drive IGBT
版权 © 2017, Texas Instruments Incorporated
27
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Typical Application (接
接下页)
15 V
VCC2
5V
VCC1
C1
C3
C4
C2
GND1
RG
OUT
PWM
Signal Emitter
CLAMP
IN+
IN±
VEE2
Power Emitter
Copyright © 2017, Texas Instruments Incorporated
图 36. Typical Application Circuit for UCC5310M and UCC5350M to Drive IGBT
15 V
VCC2
5V
VCC1
C1
C3
C4
C2
GND1
RG
OUT
PWM
Signal Emitter
IN+
GND2
±8 V
IN±
VEE2
Power Emitter
Copyright © 2017, Texas Instruments Incorporated
图 37. Typical Application Circuit for UCC5320E and UCC5390E to Drive IGBT
10.2.1 Design Requirements
表 5 lists the recommended conditions to observe the input and output of the UCC5320S split-output gate driver
with the IN– pin tied to the GND1 pin.
表 5. UCC5320S Design Requirements
PARAMETER
VALUE
UNIT
VCC1
5
V
VCC2
20
V
IN+
5
VPP
IN–
GND1
V
1
kHz
Switching frequency
28
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
10.2.2 Detailed Design Procedure
10.2.2.1 Designing IN+ and IN– Input Filter
TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the
signal at the output. However, a small input filter, RIN-CIN, can be used to filter out the ringing introduced by
nonideal layout or long PCB traces.
Such a filter should use an RIN resistor with a value from 0 Ω to 100 Ω and a CIN capacitor with a value from 10
pF to 100 pF. In the example, the selected value for RIN is 51 Ω and CIN is 33 pF, with a corner frequency of
approximately 100 MHz.
When selecting these components, pay attention to the trade-off between good noise immunity and propagation
delay.
10.2.2.2 Gate-Driver Output Resistor
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)
The UCC53x0 devices have similar pullup structures but S and E variations have different pulldown circuits than
the M version as described in the Output Stage section. The output stage has a pullup structure consisting of a
P-channel MOSFET and an N-channel MOSFET in parallel. The combined peak source current is 4.3 A for the
UCC5320 family and 17 A for the UCC5390 family. Use 公式 1 to estimate the peak source current using the
UCC5320S as an example.
§
·
VCC2
IOH min ¨ 4.3 A,
¸
¨
RNMOS || ROH RON RGFET _ Int ¹¸
©
where
•
•
•
RON is the external turnon resistance.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet.
IOH is the peak source current which is the minimum value between 4.3 A, the gate-driver peak source current,
and the calculated value based on the gate-drive loop resistance.
(1)
In this example, the peak source current is approximately 1.7 A as calculated in 公式 2.
VCC2
20 V
IOH
| 1.7 A
RNMOS || ROH RON RGFET _ Int 4.5 : || 12 : 2.2 : 1.5 :
(2)
Similarly, use 公式 3 to calculate the peak sink current.
§
·
VCC2
IOL min ¨ 4.4 A,
¸
¨
ROL R OFF RGFET _ Int ¸¹
©
where
•
•
ROFF is the external turnoff resistance.
IOL is the peak sink current which is the minimum value between 4.4 A, the gate-driver peak sink current, and
the calculated value based on the gate-drive loop resistance.
(3)
In this example, the peak sink current is the minimum of 公式 4 and 4.4 A.
VCC2
20 V
IOL
| 9.3 A
ROL ROFF RGFET _Int 0.65 : 0 : 1.5 :
版权 © 2017, Texas Instruments Incorporated
(4)
29
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
注
The estimated peak current is also influenced by PCB layout and load capacitance.
Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and
introduce overshoot and undershoot. Therefore, TI strongly recommends that the gatedriver loop should be minimized. Conversely, the peak source and sink current is
dominated by loop parasitics when the load capacitance (CISS) of the power transistor is
very small (typically less than 1 nF) because the rising and falling time is too small and
close to the parasitic ringing period.
10.2.2.3 Estimate Gate-Driver Power Loss
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC53x0 device and the
power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC53x0 device,
and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is
measured on the bench with no load connected to the OUT or OUTH and OUTL pins at a given VCC1, VCC2,
switching frequency, and ambient temperature. In this example, VCC1 is 5 V and VCC2 is 20 V. The current on
each power supply, with PWM switching from 0 V to 3.3 V at 1 kHz, is measured to be ICC1 = 1.67 mA and ICC2 =
1.11 mA. Therefore, use 公式 5 to calculate PGDQ.
PGDQ VCC1 u IVCC1 VCC2 u ICC2 | 31 mW
(5)
The second component is the switching operation loss, PGDO, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Use 公式 6 to calculate the total dynamic loss from
load switching, PGSW.
PGSW 2 u VCC2 u QG u fSW
where
•
QG is the gate charge of the power transistor at VCC2.
(6)
If a split rail is used for turn-on and turnoff, then VCC2 is the total difference between the positive rail to the
negative rail.
So, for this example application the total dynamic loss from load switching is approximately 4 mW as calculated
in 公式 7.
PGSW 2 u 20 V u 100 nC u 1 kHz 4 mW
(7)
QG represents the total gate charge of the power transistor switching 400 V at 14 A, and is subject to change
with different testing conditions. The UCC5320S gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO
is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the
gate driver-loss will be dissipated inside the UCC5320S. If an external turnon and turnoff resistance exists, the
total loss is distributed between the gate driver pullup and pulldown resistance, external gate resistance, and
power-transistor internal resistance.
注
The pullup or pulldown resistance is a linear and fixed resistance if the source or sink
current is not saturated to 4.3 A or 4.4 A (respectively), however, the resistance is
nonlinear if the source or sink current is saturated. Therefore, PGDO is different in these
two cases as follows.
Use 公式 8 to calculate the linear pullup or pulldown resistor for case 1.
PGDO
PGSW
2
§
ROH || RNMOS
¨
¨ ROH || RNMOS RON RGFET _ Int
©
ROL
ROL
ROFF
RGFET _ Int
·
¸
¸
¹
(8)
In this design example, all the predicted source and sink currents are less than 4.3 A and 4.4 A, therefore, use 公
式 9 to estimate the UCC53x0 gate-driver loss.
30
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
4 mW §
12 : || 4.5 :
¨
2 © 12 : || 4.5 : 2.2 : 1.5 :
PGDO
·
0.65 :
¸ |1.5 mW
0.65 : 0 : 1.5 : ¹
(9)
Use 公式 10 to calculate the nonlinear pullup or pulldown resistor for case 2.
PGDO 2 u fSW
TR _ Sys
ª
«
VCC2
u 4.3 A u
«
0
«¬
³
TF _ Sys
VOUTH (t) dt 4.4 A u
³
0
º
VOUTL (t)dt »
»
»¼
where
•
VOUTH/L(t) is the gate-driver OUTH and OUTL pin voltage during the turnon and turnoff period. In cases where
the output is saturated for some time, this value can be simplified as a constant-current source (4.3 A at turnon
and 4.4 A at turnoff) charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and
the TR_Sys and TF_Sys can be easily predicted.
(10)
For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is
a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based
on this discussion.
Use 公式 11 to calculate the total gate-driver loss dissipated in the UCC53x0 gate driver, PGD.
PGD PGDQ PGDO 31 mW 1.5 mW 32.5 mW
(11)
10.2.2.4 Estimating Junction Temperature
Use 公式 12 to estimate the junction temperature (TJ) of the UCC53x0 family.
TJ TC < JT u PGD
where
•
•
TC is the UCC53x0 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the Thermal Information table.
(12)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming
that the amount of energy leaving through the top of the IC will be similar in both the testing environment and the
application environment. As long as the recommended layout guidelines are observed, junction temperature
estimations can be made accurately to within a few degrees Celsius.
10.2.3 Selecting VCC1 and VCC2 Capacitors
Bypass capacitors for the VCC1 and VCC2 supplies are essential for achieving reliable performance. TI
recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients, and capacitance tolerances.
注
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,
1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.
10.2.3.1 Selecting a VCC1 Capacitor
A bypass capacitor connected to the VCC1 pin supports the transient current required for the primary logic and the
total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is
recommended for this application. If the bias power-supply output is located a relatively long distance from the
VCC1 pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the
MLCC.
版权 © 2017, Texas Instruments Incorporated
31
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
10.2.3.2 Selecting a VCC2 Capacitor
A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC2 capacitor. If the bias power supply
output is located a relatively long distance from the VCC2 pin, a tantalum or electrolytic capacitor with a value
greater than 10 μF should be used in parallel with CVCC2.
10.2.3.3 Application Circuits With Output Stage Negative Bias
When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220
and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turnon and shoot-through
could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the
threshold. A few examples of implementing negative gate-drive bias follow.
图 38 shows the first example with negative bias turnoff on the output using a Zener diode on the isolated powersupply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply is equal to
25 V, the turnoff voltage is –5.1 V and the turnon voltage is 25 V – 5.1 V ≈ 20 V.
25 V
VCC2
C3
VCC1
CA1
RZ
GND1
RGON
OUTH
RGOFF
IN+
OUTL
IN±
VEE2
Signal Emitter
CA2
Copyright © 2017, Texas Instruments Incorporated
图 38. Negative Bias With Zener Diode on Iso-Bias Power-Supply Output (UCC5320S and UCC5390S)
图 39 shows another example which uses two supplies (or single-input, double-output power supply). The power
supply across VCC2 and GND2 determines the positive drive output voltage and the power supply across VEE2
and GND2 determines the negative turnoff voltage. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
VCC2
VCC1
CA1
+
±
GND1
RG
OUT
IN+
Signal Emitter
GND2
+
CA2
±
IN±
VEE2
Copyright © 2017, Texas Instruments Incorporated
图 39. Negative Bias With Two Iso-Bias Power Supplies (UCC5320E and UCC5390E)
32
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
10.2.4 Application Curve
VCC2 = 20 V
VEE2 = GND fSW = 10 kHz
图 40. PWM Input And Gate Voltage Waveform
11 Power Supply Recommendations
The recommended input supply voltage (VCC1) for the UCC53x0 device is from 3 V to 15 V. The lower limit of the
range of output bias-supply voltage (VCC2) is determined by the internal UVLO protection feature of the device.
The VCC1 and VCC2 voltages should not fall below their respective UVLO thresholds for normal operation, or else
the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature. For more
information on UVLO, see the Undervoltage Lockout (UVLO) section. The higher limit of the VCC2 range depends
on the maximum gate voltage of the power device that is driven by the UCC53x0 device, and should not exceed
the recommended maximum VCC2 of 33 V. A local bypass capacitor should be placed between the VCC2 and VEE2
pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100-nF capacitor in
parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as
close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended. Similarly, a
bypass capacitor should also be placed between the VCC1 and GND1 pins. Given the small amount of current
drawn by the logic circuitry within the input side of the UCC53x0 device, this bypass capacitor has a minimum
recommended value of 100 nF.
If only a single, primary-side power supply is available in an application, isolated power can be generated for the
secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet.
版权 © 2017, Texas Instruments Incorporated
33
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC53x0. Some key
guidelines are:
• Component placement:
– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1
pins and between the VCC2 and VEE2 pins to bypass noise and to support high peak currents when turning
on the external power transistor.
– To avoid large negative transients on the VEE2 pins connected to the switch node, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• Grounding considerations:
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
• High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. PCB cutting or scoring beneath the IC are not recommended because
this can severely exacerbate board warping and twisting issues.
• Thermal considerations:
– A large amount of power may be dissipated by the UCC53x0 if the driving voltage is high, the load is
heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss
section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-toboard thermal impedance (θJB).
– Increasing the PCB copper connecting to the VCC2, GND1, and VEE2 pins is recommended, with priority on
maximizing the connection to VEE2. However, the previously mentioned high-voltage PCB considerations
must be maintained.
– If the system has multiple layers, TI also recommends connecting the VCC2 and VEE2 pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the
IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different
high voltage planes are overlapping.
34
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
12.2 Layout Example
图 41 shows a PCB layout example with the signals and key components labeled.
(1)
No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
图 41. Layout Example
版权 © 2017, Texas Instruments Incorporated
35
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
Layout Example (接
接下页)
图 42 and 图 43 show the top and bottom layer traces and copper.
图 42. Top-Layer Traces and Copper
图 43. Bottom-Layer Traces and Copper (Flipped)
36
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
Layout Example (接
接下页)
图 44 shows the 3D layout of the top view of the PCB.
(1)
The location of the PCB cutout between primary side and secondary sides ensures isolation performance.
图 44. 3-D PCB View
12.3 PCB Material
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the selfextinguishing flammability-characteristics.
图 45 shows the recommended layer stack.
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图 45. Recommended Layer Stack
版权 © 2017, Texas Instruments Incorporated
37
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
• 德州仪器 (TI)，数字隔离器设计指南
• 德州仪器 (TI)，隔离相关术语
• 德州仪器 (TI)，《SN6501 用于隔离式电源的变压器驱动器》数据表
• 德州仪器 (TI)，《SN6505A 用于隔离式电源的低噪声 1A 变压器驱动器》数据表
• 德州仪器 (TI)，UCC53x0xD 评估模块用户指南
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 6. 相关链接
器件
产品文件夹
立即订购
技术文档
工具和软件
支持和社区
UCC5310
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
UCC5320
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
UCC5350
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
UCC5390
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
13.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
14 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
39
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
40
版权 © 2017, Texas Instruments Incorporated
UCC5310, UCC5320, UCC5350, UCC5390
www.ti.com.cn
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2017, Texas Instruments Incorporated
41
UCC5310, UCC5320, UCC5350, UCC5390
ZHCSGC2B – JUNE 2017 – REVISED AUGUST 2017
www.ti.com.cn
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
42
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC5310MCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5310M
UCC5310MCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5310M
UCC5320ECD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5320E
UCC5320ECDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5320E
UCC5320SCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5320S
UCC5320SCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5320S
UCC5350MCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5350M
UCC5350MCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
5350M
UCC5390ECD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
53X0E
UCC5390ECDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
53X0E
UCC5390SCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
53X0S
UCC5390SCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
53X0S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2017
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
