UCD3138ARJAT

Product Folder Order Now Technical Documents Tools & Software Support & Community UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 UCD3138A Highly-Integrated Digital Controller for Isolated Power 1 Device Overview 1.1 Features 1 • Digital Control of up to 3 Independent Feedback Loops – Dedicated PID-Based Hardware – 2-Pole, 2-Zero Configurable – Nonlinear Control • Soft-Start and Soft-Stop with and without Prebias • Fast Input Voltage Feed Forward Hardware • Synchronous Rectifier Dead Time Optimization Peripheral to Use with UCD7138 Synchronous Rectifier Driver • Up to 16 MHz Error Analog-to-Digital Converter (EADC) – Configurable Resolution as Small as 1 mV/LSB – Automatic Resolution Selection – Up to 8× Oversampling – Hardware-Based Averaging (up to 8×) – 10-Bit Effective DAC With 4 Bits of Dither – Adaptive Sample Trigger Positioning • Up to 8 High-Resolution Digital Pulse Width Modulated (DPWM) Outputs – 250-ps Pulse Width Resolution – 4-ns Frequency and Phase Resolution – Adjustable Phase-Shift Between Outputs – Adjustable Dead-band Between Pairs – Cycle-by-Cycle Duty Cycle Matching – Up to 2-MHz Switching Frequency • Configurable PWM Edge Movement – Trailing Modulation – Leading Modulation – Triangular Modulation • Configurable Feedback Control – Voltage Mode – Average Current Mode – Peak Current Mode Control – Constant Current – Constant Power • Configurable Modulation Methods – Frequency Modulation – Phase-Shift Modulation – Pulse Width Modulation • Fast, Automatic, and Smooth Mode Switching – Frequency Modulation and PWM – Phase-Shift Modulation and PWM – Frequency Modulation and Phase-Shift Modulation • High Efficiency and Light Load Management – Burst Mode – Ideal Diode Emulation – Synchronous Rectifier Soft On/Off – Low IC Standby Power • Primary Side Voltage Sensing • Copper Trace Current Sensing • Flux and Phase Current Balancing • Current Share Bus Support – Average or Master and Slave • Feature Rich Fault Protection Options – 7 High-Speed Analog Comparators – Cycle-by-Cycle Current Limiting – Programmable Fault – External Fault Capability – 10 Digital Comparators – Programmable Blanking Time • Synchronization of DPWM Waveforms Between Multiple UCD3138A devices • 14-Channel, 12-Bit, 267-ksps General-Purpose ADC – Programmable Averaging Filters – Dual Sample and Hold • Internal Temperature Sensor • Fully Programmable High-Performance 31.25MHz, 32-Bit ARM7TDMI-S™ Processor – 32 KB of Program Flash – 2 KB of Data Flash with ECC – 4 KB of Data RAM – Firmware Boot-Load in the Field via PMBus or UART • Communication Peripherals – PMBus – 1 UART • UART Auto-baud Rate Adjustment • Timer Capture with Selectable Input Pins • Up to 5 Additional General Purpose Timers • Built In Watchdog: BOD and POR • 64-Pin QFN and 40-Pin QFN Package • Operating Temperature: –40°C to +125°C • Debug Interface – Code Composer Studio™ with JTAG Interface – Fusion Digital Power™ Designer GUI Support 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 1.2 • • www.ti.com Applications Power Supplies and Telecom Rectifiers Power Factor Correction 1.3 • Isolated DC-DC Modules Description The UCD3138A is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single-chip solution. The flexible nature of the UCD3138A makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC-DC and isolated DC-DC applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138A controller is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customers' development effort by offering best-in-class development tools, including application firmware, Code Composer Studio™ software development environment, and TI’s power development GUI which lets customers configure and monitor key system parameters. At the core of the UCD3138A controller are the digital control loop peripherals, also known as Digital Power Peripherals (DPPs). Each DPP implements a high-speed digital control loop consisting of a dedicated error analog-to-digital converter (EADC), a PID-based 2-pole-2-zero digital compensator and DPWM outputs with 250-ps pulse width resolution. The device also contains a 12-bit, 267-ksps generalpurpose ADC with up to 14 channels, timers, interrupt control, PMBus, and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals, and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on-chip RAM and ROM. In addition to the DPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, automatic mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high-resolution current sharing, hardware-configurable soft-start operation with pre-bias, as well as several other features. The device optimizes topology support for voltage mode and peak current mode controlled phase-shifted full bridge, single and dual phase PFC, bridge-less PFC, hard-switched full bridge and half bridge, and LLC half bridge and full bridge. The UCD3139A is a functional variant of the UCD3138A Digital Power Controller that includes significant improvements over the UCD3138 device For a description of the complete changes made in the UCD3138A, refer to UCD3138A Migration Guide. Device Information(1) DEVICE NUMBER UCD3138A PACKAGE DRAWING PACKAGE TYPE BODY SIZE RGC VQFN (64) 9.00 mm × 9.00 mm RJA VQFN (40)(3) 6.00 mm × 6.00 mm RMH WQFN (40) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. (2) 40-pin 6 x 6 x 0.75 mm ultra-thin QFN with corner anchors optimized for IPC9592A Temperature Cycle Testing. (3) Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability (BLR). 2 Device Overview Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 1.4 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Functional Block Diagram Figure 1-1 shows a functional block diagram of the device. Loop MUX DPWM0A EAP0 Front End 0 PID Based Filter 0 DPWM0 DPWM0B EAN0 DPWM1A EAP1 PID Based Filter 1 Front End 1 DPWM1 DPWM1B EAN1 DPWM2A Front End 2 PID Based Filter 2 DPWM2 AFE 2 EAP2 DPWM2B 23-AFE AFE DPWM3 DPWM3B Front End Averaging EADC X EAN2 DPWM3A Constant Power Constant Current SYNC Avg() Digital Comparators SAR/Prebias DAC0 Ramp A0 Input Voltage Feed Forward Filter x CPCC Value Dither Abs() Peak Current Mode Control Comparator Advanced Power Control Mode Switching, Burst Mode, IDE, Synchronous Rectification soft on & off PMBUS_ALERT ADC12 Control Sequencing, Averaging, Digital Compare, Dual Sample and hold PMBUS_CTRL PMBus ADC12 PMBUS_DATA AD00 PMBUS_CLK AD01 Internal Temperature Sensor PWM0 Timers 4 ± 16 bit (PWM) 1 ± 24 bit AD02 AGND Current Share Analog, Average, Master/Slave AD13 PWM1 TCAP Oscillator SCI_TX0 UART0 AD02 ARM7TDMI-S 32 bit, 31.25 MHz Analog Comparators SCI_RX0 SCI_TX1 UART1 A SCI_RX1 AD03 Memory PFLASH 64 kB DFLASH 2 kB RAM 4 kB ROM 4 kB B EXT_INT FAULT0 C AD04 D V33D AD13 E V33DIO VREG DGND V33A Power and 1.8 V Voltage Regulator AD06 F GPIO Control Fault MUX & Control Cycle by Cycle Current Limit FAULT1 FAULT2 Power On Reset FAULT3 /RESET Brown Out Detection Digital Comparators TCK JTAG TMS AD07 G TDI(DTC0) DTC TDO(DTC1) AGND Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Functional Block Diagram Device Overview Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 3 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Rising edge optimization control UCD3138A UCD7138 6 CTRL 5 VD SR1 IN 1 DTC 2 VCC 4 SR1DPWM SR2DPWM 3 DPWM module OUT Dead-time control computation engine Rising edge optimization control DTC0 UCD7138 6 CTRL 5 VD 4 OUT SR2 IN 1 DTC 2 VCC 3 DTC1 Decoder Copyright © 2016, Texas Instruments Incorporated Figure 1-2. Synchronous Rectifier Peripheral Use with Synchronous Rectifier Driver 4 Device Overview Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Table of Contents 1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Functional Block Diagram ............................ 3 2 3 Revision History ......................................... 6 Device Comparison ..................................... 7 4 Pin Configuration and Functions ..................... 8 3.1 6 7 ............................. 7 Overview 30 7.2 ARM Processor 30 30 32 34 51 57 57 58 ........................... 8 4.2 UCD3138A RMH Package .......................... 10 4.3 UCD3138A RJA Package ........................... 12 Specifications ........................................... 14 5.1 Absolute Maximum Ratings ......................... 14 5.2 ESD Ratings ........................................ 14 5.3 Recommended Operating Conditions ............... 14 5.4 Thermal Information ................................. 14 5.5 Electrical Characteristics ............................ 15 5.6 PMBus/SMBus/I2C Timing .......................... 19 5.7 Peripherals .......................................... 20 5.8 Typical Temperature Characteristics................ 28 Parametric Measurements Information ............ 29 9 6.1 12 Mechanical Packaging and Orderable Information .............................................. 74 4.1 5 Product Selection Matrix 8 ............................................ ..................................... 7.3 Memory .............................................. 7.4 System Module ...................................... 7.5 Feature Description ................................. 7.1 Device Functional Modes ........................... Application and Implementation .................... 8.2 Application Information .............................. 8.3 Typical Application .................................. Power Supply Recommendations .................. 9.1 Power Supply Decoupling and Bulk Capacitors .... Layout .................................................... 10.1 Layout Guidelines ................................... 10.2 Layout Example ..................................... Device and Documentation Support ............... 11.1 Device Support ...................................... 11.2 Documentation Support ............................. 11.3 Receiving Notification of Documentation Updates .. 11.4 Community Resources .............................. 11.5 Trademarks.......................................... 11.6 Electrostatic Discharge Caution ..................... 11.7 Glossary ............................................. 7.1 UCD3138A RGC Package Power-On Reset (POR) and Brown-Out Reset (BOR)................................................ 29 Detailed Description ................................... 30 10 11 12.1 Packaging Information .............................. Table of Contents Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 69 69 69 69 70 72 72 74 74 74 74 74 74 74 5 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2016) to Revision E • • • Added two temperature ranges to the Internal oscillator frequency section. ................................................ 16 Added updated V33 slew rate values in the Device Grounding and Layout Guidelines section. ......................... 69 Changed Layout Example images. ............................................................................................... 70 Changes from Revision C (September 2016) to Revision D • • • • • • Page Added the VQFN (40) pin package to the Device Information table. .......................................................... 2 Added WQFN (40) note, Recommended for new 40-pin designs with advanced BLR performance. ..................... 2 Added the UCD3138A 40 PIN (RJA) column to the Product Selection Matrix table ......................................... 7 Added the UCD3138A RJA Package section ................................................................................... 12 Added the RJA package to the Thermal Information table ................................................................... 14 Changes from Revision A (April 2015) to Revision B • Changed Figure 7-3 image and following notes • • • • • • 6 Page ................................................................................ Changes from Original (March 2015) to Revision A • • • Page Added "64-Pin QFN and" to 40-Pin QFN Package bullet. ....................................................................... 1 Deleted ICP9592A T/C Qualification bullet. ...................................................................................... 1 Added PACKAGE DRAWING column to the Device Information table. ....................................................... 2 Changed Note 2 from "Recommended for new 40-pin designs with advance BLR performance" to "Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability (BLR)." ....................................................................................................... 2 Deleted Note 2, "40-pin 6 x 6 x 0.75 mm ultra-thin QFN with corner anchors optimized for IPC9592A Temperature Cycle Testing. " ...................................................................................................... 2 Deleted note, "These features help to improve solder-joint reliability". ...................................................... 10 Changes from Revision B (May 2015) to Revision C • • • • • Page 54 Page Changed the device status From: Product Preview To: Production ........................................................... 1 Changed Feature From: "4KB of Boot ROM Enables Firmware Boot-Load.." To: "Firmware Boot-Load..." ............. 1 Changed Note 2 of the Device Information table From: "for passing IPC9592A Temperature Cycle Qualification" To: "for IPC9592A Temperature Cycle Testing." ................................................................................. 2 Changed Figure 5-7 ................................................................................................................ 26 Added Figure 6-1 ................................................................................................................... 29 Changed Table 7-4 PRIORITY 19 From: CAPTURE_1_INT To: DTC_FLT_INT........................................... 33 Changed Figure 7-1 to include DTC Adjustment ............................................................................... 52 Changed Figure 7-2 to include DTC Adjustment ............................................................................... 53 Changed Figure 7-3 to include DTC Adjustment ............................................................................... 54 Revision History Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 3 Device Comparison 3.1 Product Selection Matrix FEATURE ARM7TDMI-S core processor UCD3138A 64 PIN (RGC) UCD3138A 40 PIN (RMH) UCD3138A 40 PIN (RJA) 31.25 MHz 31.25 MHz 31.25 MHz High resolution DPWM outputs (250-ps resolution) 8 8 8 Number of high speed independent feedback loops (number of regulated output voltages) 3 3 3 12-bit, 267-ksps, general-purpose ADC channels 14 7 7 Digital comparators at ADC outputs 4 4 4 Flash memory (program) 32 kB 32 kB 32 kB Flash memory (data) 2 kB 2 kB 2 kB √ √ √ 4 kB 4 kB 4 kB DPWM switching frequency up to 2 MHz up to 2 MHz up to 2 MHz Programmable fault inputs 4 1+2 1+2 7 (1) 6 (1) 6 (1) UART (SCI) 2 1 1 PMBus √ √ √ Timers 4 (16 bit) and 1 (24 bit) 4 (16 bit) and 1 (24 bit) 4 (16 bit) and 1 (24 bit) Timer PWM outputs 2 1 1 Timer capture inputs 1 1 1 Watchdog √ √ √ On-chip oscillator √ √ √ Power-on reset and brown-out reset √ √ √ 64 Pin VQFN (9 mm × 9 mm) 40 Pin WQFN (6 mm × 6 mm) 40 Pin WQFN (6 mm × 6 mm) Sync IN and sync OUT functions √ √ √ Total GPIO (includes all pins with multiplexed functions such as, DPWM, fault inputs, SCI, and so forth) 30 18 18 External interruptions 1 0 0 Flash security RAM High speed analog comparators with cycle-by-cycle current limiting Package offering (1) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin. Device Comparison Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 7 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 4 Pin Configuration and Functions 4.1 UCD3138A RGC Package AD11 AD09 AD08 AD05 AD02 AD01 AD00 V33A AGND EAN2 EAP2 EAN1 EAP1 EAN0 EAP0 AGND 64 VQFN Package Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 43 FAULT3 AD04 7 42 FAULT2 AD03 8 41 TCAP V33DIO 9 40 TMS DGND 10 39 TDI/SCI_RX0/PMBUS_CTRL/FAULT1/DTC0 /RESET 11 38 TDO/SCI_TX0/PMBUS_ALERT/FAULT0/DTC1 ADC_EXT_TRIG/TCAP/SYNC/PWM0 12 37 TCK/TCAP/SYNC/PWM0/DTC0 SCI_RX0 13 36 FAULT1 SCI_TX0 14 35 FAULT0 PMBUS_CLK/SCI_TX0 15 34 INT_EXT PMBUS_DATA/SCI_RX0 16 33 DGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM1 6 PWM0 DGND AD06 SCI_RX1/PMBUS_CTRL 44 SCI_TX1/PMBUS_ALERT 5 PMBUS_CTRL V33DIO AD07 PMBUS_ALERT 45 SYNC/TCAP/ADC_EXT_TRIG/PWM0/DTC1 4 DGND BP18 AD10 DPWM3B 46 DPWM3A 3 DPWM2B V33D AD12 DPWM2A 47 DPWM1B AGND 2 DPWM1A 48 AD13 DPWM0B 1 DPWM0A AGND UCD3138A RGC Pin Functions ALTERNATE ASSIGNMENT PIN NO. NAME PRIMARY ASSIGNMENT NO. 1 8 1 AGND Analog ground 2 AD13 12-bit ADC, Ch 13, comparator E, I-share 3 AD12 12-bit ADC, Ch 12 4 AD10 12-bit ADC, Ch 10 5 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference to comparator G DAC output 6 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output 7 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output 8 AD03 12-bit ADC, Ch 3, Connected to comparator B and C NO. 2 NO. 3 SYNC PWM0 NO. 4 CONFIGURABLE AS A GPIO? DAC output 9 V33DIO Digital I/O 3.3V core supply 10 DGND Digital ground 11 RESET Device Reset Input, active low 12 ADC_EXT_TRIG ADC conversion external trigger input 13 SCI_RX0 SCI RX 0 14 SCI_TX0 SCI TX 0 15 PMBUS_CLK PMBUS Clock (Open Drain) SCI TX 0 Yes 16 PMBUS_DATA PMBus data (Open Drain) SCI RX 0 Yes 17 DPWM0A DPWM 0A output TCAP Yes Yes Yes Yes Pin Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 UCD3138A RGC Pin Functions (continued) ALTERNATE ASSIGNMENT PIN NO. NAME PRIMARY ASSIGNMENT NO. 1 NO. 2 NO. 3 NO. 4 CONFIGURABLE AS A GPIO? 18 DPWM0B DPWM 0B output Yes 19 DPWM1A DPWM 1A output Yes 20 DPWM1B DPWM 1B output Yes 21 DPWM2A DPWM 2A output Yes 22 DPWM2B DPWM 2B output Yes 23 DPWM3A DPWM 3A output Yes 24 DPWM3B DPWM 3B output Yes 25 DGND Digital ground 26 SYNC DPWM Synchronize pin 27 PMBUS_ALERT PMBus Alert (Open Drain) 28 PMBUS_CTRL PMBus Control (Open Drain) 29 SCI_TX1 SCI TX 1 PMBUS_ALERT Yes 30 SCI_RX1 SCI RX 1 PMBUS_CTRL Yes 31 PWM0 General purpose PWM 0 Yes 32 PWM1 General purpose PWM 1 Yes 33 DGND Digital ground 34 INT_EXT External Interrupt Yes 35 FAULT0 External fault input 0 Yes 36 FAULT1 External fault input 1 37 TCK JTAG TCK TCAP SYNC PWM0 DTC0 Yes 38 TDO JTAG TDO SCI_TX0 PMBUS_ALERT FAULT0 DTC1 Yes 39 TDI JTAG TDI SCI_RX0 PMBUS_CTRL FAULT1 DTC0 Yes 40 TMS JTAG TMS Yes 41 TCAP Timer capture input Yes 42 FAULT2 External fault input 2 Yes 43 FAULT3 External fault input 3 Yes 44 DGND Digital ground 45 V33DIO Digital I/O 3.3V core supply 46 BP18 1.8V Bypass 47 V33D Digital 3.3V core supply 48 AGND Substrate analog ground 49 AGND Analog ground 50 EAP0 Channel 0, differential analog voltage, positive input 51 EAN0 Channel 0, differential analog voltage, negative input 52 EAP1 Channel 1, differential analog voltage, positive input 53 EAN1 Channel 1, differential analog voltage, negative input 54 EAP2 Channel 2, differential analog voltage, positive input (Recommended for peak currrent mode control) 55 EAN2 Channel #2, differential analog voltage, negative input 56 AGND Analog ground 57 V33A Analog 3.3-V supply 58 AD00 12-bit ADC, Ch 0, Connected to current source 59 AD01 12-bit ADC, Ch 1, Connected to current source 60 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share 61 AD05 12-bit ADC, Ch 5 62 AD08 12-bit ADC, Ch 8 63 AD09 12-bit ADC, Ch 9 64 AD11 12-bit ADC, Ch 11 TCAP ADC_EXT_TRIG PWM0 DTC1 Yes Yes Yes Yes Pin Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 9 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 4.2 www.ti.com UCD3138A RMH Package 40 39 38 36 35 33 32 EAP0 EAN0 EAN1 34 EAP1 EAP2 V33A 37 AGND AD00 AD01 AD02 40 WQFN Package With Corner Anchors Pin Attributes Top View 31 28 BP18 AD04 4 27 V33D AD03 5 26 DGND DGND 6 25 FAULT2 /RESET 7 24 TMS ADC_EXT_TRIG/TCAP/SYNC/PWM0 8 23 TDI/SCI_RX0/PMBUS_CTRL/FAULT1/DTC0 PMBUS_CLK/SCI_TX0 9 22 TDO/SCI_TX0/PMBUS_ALERT/FAULT0/DTC1 PMBUS_DATA/SCI_RX0 10 21 TCK/TCAP/SYNC/PWM0/DTC0 13 14 15 16 17 18 19 20 PMBUS_CTRL 12 PMBUS_ALERT DPWM0A 11 DPWM3B AD06 DPWM3A AGND DPWM2B 29 3 DPWM2A AD13 DPWM1B AGND DPWM1A 30 2 DPWM0B AGND 1 There are four corner pins on the RMH package. The corner anchor pins and thermal pad should be soldered for robust mechanical performance and should be tied to the appropriate ground signal. UCD3138A RMH Pin Functions ALTERNATE ASSIGNMENT PIN NO. 10 NAME PRIMARY ASSIGNMENT NO. 1 NO. 2 NO. 3 TCAP SYNC PWM0 NO. 4 CONFIGURABLE AS A GPIO? 1 AGND Analog ground 2 AD13 12-bit ADC, Ch 13, Connected to comparator E, I-share 3 AD06 12-bit ADC, Ch 6, Connected to comparator F 4 AD04 12-bit ADC, Ch 4, Connected to comparator D 5 AD03 12-bit ADC, Ch 3, Connected to comparator B and C 6 DGND Digital ground 7 RESET Device Reset Input, active low 8 ADC_EXT_TRIG ADC conversion external trigger input 9 PMBUS_CLK PMBUS Clock (Open Drain) SCI_TX0 Yes 10 PMBUS_DATA PMBus data (Open Drain) SCI_RX0 Yes 11 DPWM0A DPWM 0A output Yes 12 DPWM0B DPWM 0B output Yes 13 DPWM1A DPWM 1A output Yes 14 DPWM1B DPWM 1B output Yes 15 DPWM2A DPWM 2A output Yes 16 DPWM2B DPWM 2B output Yes 17 DWPM3A DPWM 3A output Yes 18 DPWM3B DPWM 3B output Yes 19 PMBUS_ALERT PMBus Alert (Open Drain) Yes 20 PMBUS_CTRL PMBus Control (Open Drain) 21 TCK JTAG TCK TCAP SYNC PWM0 DTC0 Yes 22 TDO JTAG TDO SCI_TX0 PMBUS_ALERT FAULT0 DTC1 Yes Yes Yes Pin Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 UCD3138A RMH Pin Functions (continued) ALTERNATE ASSIGNMENT PIN NO. NAME NO. 1 NO. 2 NO. 3 NO. 4 CONFIGURABLE AS A GPIO? SCI_RX0 PMBUS_CTRL FAULT1 DTC0 Yes PRIMARY ASSIGNMENT 23 TDI JTAG TDI 24 TMS JTAG TMS Yes 25 FAULT2 External fault input 2 Yes 26 DGND Digital ground 27 V33D Digital 3.3V core supply 28 BP18 1.8V Bypass 29 AGND Substrate analog ground 30 AGND Analog ground 31 EAP0 Channel 0, differential analog voltage, positive input 32 EAN0 Channel 0, differential analog voltage, negative input 33 EAP1 Channel 1, differential analog voltage, positive input 34 EAN1 Channel 1, differential analog voltage, negative input 35 EAP2 Channel 2, differential analog voltage, positive input (Recommended for peak currrent mode control) 36 AGND Analog ground 37 V33A Analog 3.3-V supply 38 AD00 12-bit ADC, Ch 0, Connected to current source 39 AD01 12-bit ADC, Ch 1, Connected to current source 40 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share Corner anchor pin All four anchors should be soldered and tied to GND Corner NA Pin Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 11 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 4.3 www.ti.com UCD3138A RJA Package 40 39 38 36 35 33 32 EAP0 EAN0 EAN1 34 EAP1 EAP2 V33A 37 AGND AD00 AD01 AD02 40 VQFN Package With Corner Anchors Pin Attributes Top View 31 28 BP18 AD04 4 27 V33D AD03 5 26 DGND DGND 6 25 FAULT2 /RESET 7 24 TMS ADC_EXT_TRIG/TCAP/SYNC/PWM0 8 23 TDI/SCI_RX0/PMBUS_CTRL/FAULT1/DTC0 PMBUS_CLK/SCI_TX0 9 22 TDO/SCI_TX0/PMBUS_ALERT/FAULT0/DTC1 PMBUS_DATA/SCI_RX0 10 21 TCK/TCAP/SYNC/PWM0/DTC0 13 14 15 16 17 18 19 20 PMBUS_CTRL 12 PMBUS_ALERT 11 DPWM3B 3 DPWM3A AGND AD06 DPWM2B 29 DPWM2A 2 DPWM1B AGND AD13 DPWM1A 30 DPWM0B 1 DPWM0A AGND The RJA package has thicker package height compared to the RMH package. There are four corner pins on the RJA package. These features help to improve solder-joint reliability. The corner anchor pins and thermal pad should be soldered for robust mechanical performance and should be tied to the appropriate ground signal. UCD3138A RJA Pin Functions ALTERNATE ASSIGNMENT PIN NO. 12 NAME PRIMARY ASSIGNMENT NO. 1 NO. 2 NO. 3 TCAP SYNC PWM0 NO. 4 CONFIGURABLE AS A GPIO? 1 AGND Analog ground 2 AD13 12-bit ADC, Ch 13, Connected to comparator E, I-share 3 AD06 12-bit ADC, Ch 6, Connected to comparator F 4 AD04 12-bit ADC, Ch 4, Connected to comparator D 5 AD03 12-bit ADC, Ch 3, Connected to comparator B and C 6 DGND Digital ground 7 RESET Device Reset Input, active low 8 ADC_EXT_TRIG ADC conversion external trigger input 9 PMBUS_CLK PMBUS Clock (Open Drain) SCI_TX0 Yes 10 PMBUS_DATA PMBus data (Open Drain) SCI_RX0 Yes 11 DPWM0A DPWM 0A output Yes 12 DPWM0B DPWM 0B output Yes 13 DPWM1A DPWM 1A output Yes 14 DPWM1B DPWM 1B output Yes 15 DPWM2A DPWM 2A output Yes 16 DPWM2B DPWM 2B output Yes 17 DWPM3A DPWM 3A output Yes 18 DPWM3B DPWM 3B output Yes 19 PMBUS_ALERT PMBus Alert (Open Drain) Yes 20 PMBUS_CTRL PMBus Control (Open Drain) 21 TCK JTAG TCK Yes Yes TCAP Pin Configuration and Functions SYNC PWM0 DTC0 Yes Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 UCD3138A RJA Pin Functions (continued) ALTERNATE ASSIGNMENT PIN NO. NAME NO. 1 NO. 2 NO. 3 NO. 4 CONFIGURABLE AS A GPIO? PRIMARY ASSIGNMENT 22 TDO JTAG TDO SCI_TX0 PMBUS_ALERT FAULT0 DTC1 Yes 23 TDI JTAG TDI SCI_RX0 PMBUS_CTRL FAULT1 DTC0 Yes 24 TMS JTAG TMS Yes 25 FAULT2 External fault input 2 Yes 26 DGND Digital ground 27 V33D Digital 3.3V core supply 28 BP18 1.8V Bypass 29 AGND Substrate analog ground 30 AGND Analog ground 31 EAP0 Channel 0, differential analog voltage, positive input 32 EAN0 Channel 0, differential analog voltage, negative input 33 EAP1 Channel 1, differential analog voltage, positive input 34 EAN1 Channel 1, differential analog voltage, negative input 35 EAP2 Channel 2, differential analog voltage, positive input (Recommended for peak currrent mode control) 36 AGND Analog ground 37 V33A Analog 3.3-V supply 38 AD00 12-bit ADC, Ch 0, Connected to current source 39 AD01 12-bit ADC, Ch 1, Connected to current source 40 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share Corner anchor pin All four anchors should be soldered and tied to GND Corner NA Pin Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 13 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 5 Specifications Absolute Maximum Ratings (1) 5.1 over operating free-air temperature range (unless otherwise noted) Input voltage MIN MAX UNIT V33D to DGND –0.3 3.8 V V33DIO to DGND –0.3 3.8 V V33A to AGND –0.3 3.8 V BP18 to DGND –0.3 2.5 V 0.3 V Ground difference, |DGND – AGND| Applied to all pins, excluding AGND (2) –0.3 3.8 V Junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Referenced to DGND 5.2 ESD Ratings VALUE (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Electrostatic discharge V(ESD) (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) UNIT V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VV33D Digital power 3 3.3 3.6 UNIT V VV33DIO Digital I/O power 3 3.3 3.6 V VV33A Analog power 3 3.3 3.6 V VBP18 1.8-V digital power 1.6 1.8 TJ Junction temperature –40 5.4 Thermal Information 2 V 125 °C UCD3138A THERMAL METRIC (1) 64 PIN 40 PIN 40 PIN VQFN (RGC) WQFN (RMH) VQFN (RJA) UNIT RθJA Junction-to-ambient thermal resistance 25.1 31.0 30.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.5 16.5 13.5 °C/W RθJB Junction-to-board thermal resistance 4.6 6.3 4.9 °C/W ψJT Junction-to-top characterization parameter 0.2 0.2 0.2 °C/W ψJB Junction-to-board characterization parameter 4.6 6.3 4.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.1 0.7 °C/W (1) 14 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 5.5 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Electrical Characteristics 3 V ≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT II33A Analog 3.3-V supply current Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA I33DIO Digital I/O 3.3-V core supply current All GPIO and communication pins are open 0.35 mA I33D Digital I/O 3.3-V core supply current I33 Total supply current ROM program execution 60 Flash programming in ROM mode Operating in ROM mode with all DPWMs enabled and switching at 2 MHz. DPWMs all unloaded. mA 70 mA 105 mA ERROR ADC INPUTS EAP, EAN EAP – AGND –0.15 1.998 –0.256 1.848 AFE = 0 –256 248 AFE = 3 0.8 1 1.20 AFE = 2 1.7 2 2.30 AFE = 1 3.55 4 4.45 AFE = 0 6.90 8 9.10 EAP – EAN Typical error range EAP – EAN Error voltage digital resolution REA Input impedance (See Figure 5-3) IOFFSET Input offset current (See Figure 5-3) EADC offset AGND reference 0.5 5 Input voltage = 0 V at AFE = 0 –2 2 Input voltage = 0 V at AFE = 1 –2.5 2.5 Input voltage = 0 V at AFE = 2 –3 -3 Input voltage = 0 V at AFE = 3 –4 4 Sample rate Gain 16 A0 100 See Figure 5-4 V mV mV MΩ –5 Analog front end amplifier bandwidth V LSB MHz MHz 1 Minimum output voltage μA V/V 30 mV EADC DAC DAC range 0 VREF DAC reference resolution 10 bit, No dithering enabled VREF DAC reference resolution With 4 bit dithering enabled INL DNL Does not include MSB transition 97.6 Settling time μV 3.0 LSB –2.1 1.6 LSB –1.4 DAC reference voltage V mV –3.0 DNL at MSB transition τ 1.6 1.56 1.58 From 10% to 90% LSB 1.61 250 V ns ADC12 IBIAS Bias current for PMBus address pins Measurement range for voltage monitoring Internal ADC reference voltage Change in Internal ADC reference from 25°C reference voltage (1) (1) 9.5 10.5 μA 0 2.5 V 2.525 V 2.475 2.500 –40°C ≤ TA ≤ 25°C –1.2 25°C ≤ TA ≤ 125°C –2.6 mV Specified by design. Not production tested. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 15 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Electrical Characteristics (continued) 3 V ≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITION ADC12 INL integral nonlinearity, end point (2) (See Figure 6-1) ADC12 INL integral nonlinearity, best fit (2) (See Figure 6-1) ADC12 DNL differential nonlinearity (2) ADC_SAMPLINGSEL = 0 to 6 for all ADC12 data ADC Zero Scale Error TYP MAX UNIT –3.9 ±2 4.5 LSB –2.3 ±1.5 2.6 LSB –0.8/+2.4 –7 ADC Full Scale Error –35 Input bias Input leakage resistance MIN VADC12 = 2.5 V ADC_SAMPLINGSEL = 0 or ADC_SAMPLINGSEL = 6 (1) Input Capacitance (1) ADC single sample conversion time (1) ADC_SAMPLINGSEL = 0 or ADC_SAMPLINGSEL = 6 LSB 7 mV 35 mV 400 nA 1 MΩ 10 pF 3.9 μs DIGITAL INPUTS/OUTPUTS (3) (4) VOL Low-level output voltage (5) VOH High-level output voltage VIH High-level input voltage VV33DIO = 3 V VIL Low-level input voltage VV33DIO = 3 V IOH Output sinking current IOL Output sourcing current (5) DGND + 0.25 IOH = 4 mA, VV33DIO = 3 V IOH = –4 mA, VV33DIO = 3 V V33DIO – 0.6 V V 2.1 V 1.1 4 –4 V mA mA SYSTEM PERFORMANCE TWD Watchdog time out range Total time is: TWD × (WDCTRL.PERIOD + 1) 14.6 Time to disable DPWM output based on High level on FAULT pin active FAULT pin signal Digital compensator delay (6) t(reset) Pulse width needed at reset (1) Retention period of flash content (data retention and program) f(PCLK) (2) (3) (4) (5) (6) 16 ns 31.25 (1 clock = 32 ns) TJ = 25°C ms MHz 6 clocks 10 µs 100 years Program time to erase one page or block in data flash or program flash 20 ms Program time to write one word in data flash or program flash 20 µs Internal oscillator frequency Sync-in or sync-out pulse width ISHARE 20.5 70 Processor master clock (MCLK) tDelay 17 –40°C to +125°C 240 250 260 MHz –5°C to +85°C 245 250 255 MHz SYNC pin 256 ns Flash read 1 MCLKs Flash rrite 20 μs Current share current source (See Figure 7-16) 238 259 μA Minimum and maximum values are specified by design and characterization data. DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset. On the 40-pin package V33DIO is connected to V33D internally. The maximum total current, IOH(max) and IOL(max) for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH. Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Electrical Characteristics (continued) 3 V ≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER RSHARE TEST CONDITION Current share resistor (See Figure 716) MIN 9.75 TYP MAX UNIT 10.3 kΩ Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 17 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Electrical Characteristics (continued) 3 V ≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT POWER ON RESET AND BROWN OUT (V33D pin, See Figure 6-2) VGH Voltage good high 2.7 V VGL Voltage good low 2.5 V Vres Voltage at which IRESET signal is valid 0.8 V tPOR Time delay after power is good or RESET relinquished Internal signal warning of brownout conditions Brownout TEMPERATURE SENSOR 1 ms 2.9 V (7) VTEMP Voltage range of sensor Voltage resolution V/°C Temperature resolution °C per bit 1.46 Accuracy (7) (8) –10 Temperature range –40 2.44 V 5.9 mV/ºC 0.1034 ºC/LSB ±5 10 125 ºC ºC ITEMP Current draw of sensor when active 30 μA tON Turn on time, settling time of sensor 100 μs VAMB Ambient temperature 1.85 V Trimmed 25°C reading ANALOG COMPARATOR DAC Reference DAC range 0 Reference voltage 2.478 Bits V V 7 bits –0.42 0.21 LSB DNL (7) 0.06 0.12 LSB Offset –5.5 19.5 mV 150 ns Reference DAC buffered output load (9) 18 2.5 2.513 INL (7) Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator. (1) (7) (8) (9) 2.5 0.5 1 mA Buffer offset (–0.5 mA) 0.3 V < VDAC < 2.17 V 0 10 mV Buffer offset (1.0 mA) 0.3 V < VDAC < 2.17 V –10 0 mV Specified by design. Not production tested. Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy. Available from reference DACs for comparators D, E, F, and G. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 PMBus/SMBus/I2C Timing 5.6 The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Section 5.6, Figure 5-1, and Figure 5-2. The values in Section 5.6 describe device functional during 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz). Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted) TYP MAX UNIT fSMB SMBus/PMBus operating frequency PARAMETER Slave mode, SMBC 50% duty cycle 100 400 kHz fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 400 kHz t(BUF) Bus free time between start and stop (1) 1.3 µs t(HD:STA) Hold time after (repeated) start (1) 0.6 µs t(SU:STA) Repeated start setup time (1) 0.6 µs t(SU:STO) Stop setup time (1) 0.6 µs t(HD:DAT) Data hold time 0 ns t(SU:DAT) Data setup time t(TIMEOUT) Error signal/detect (2) t(LOW) Clock low period 1.3 t(HIGH) Clock high period (3) 0.6 t(LOW:SEXT) Cumulative clock low slave extend time (4) tf Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) tr Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) Cb Total capacitance of one bus line (1) (2) (3) (4) (5) TEST CONDITIONS MIN Receive mode 100 ns 35 ms µs µs 25 ms 20 + 0.1 Cb (5) 300 ns 20 + 0.1 Cb (5) 300 ns 400 pF Fast mode, 400 kHz The device times out when any clock low exceeds t(TIMEOUT). t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0). t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. Cb (pF) Figure 5-1. I2C/SMBus/PMBus Timing Diagram Figure 5-2. Bus Timing in Extended Mode Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 19 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 5.7 www.ti.com Peripherals 5.7.1 Digital Power Peripherals (DPPs) At the core of the UCD3138A controller are three DDPs. Each DPP can be configured to drive from one to eight DPWM outputs. Each DPP consists of: • Differential input error ADC (EADC) with sophisticated controls • Hardware accelerated digital 2-pole/2-zero PID based compensator • Digital PWM module with support for a variety of topologies These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constant power, and so on. The simplest configuration is shown in the following figure: EAP EAN 5.7.1.1 DPWMA Error ADC (Front End) Filter Digital PWM DPWMB Front End Figure 5-3 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog-to-digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition each EADC has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so on. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error. It is possible to operate the controller in a peak current mode control configuration; an EADC is recommended for implementing peak current mode control. In this mode, topologies like a phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in Section 5.5. 20 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 EAP IOFFSET REA + AGND Front-end differential amplifier EAN IOFFSET REA AGND Figure 5-3. Input Stage of EADC Module AFE_GAIN 2 EAP0 3-AFE_GAIN 6 bit ADC 8 mV/LSB EAN0 2 AFE_GAIN EADC X Signed 9 bit result (error) 1 mV /LSB Averaging SAR/Prebias Ramp A0 Filter x DAC0 10 bit DAC 1.5625 mV/LSB CPCC S Value Dither 4 bit dithering gives 14 bits of effective resolution 97.65625 µV/LSB effective resolution Absolute Value Calculation 10 bit result 1.5625 mV/LSB Peak Current Detected Peak Current Mode Comparator Figure 5-4. Front End Module (Front End 2 Recommended for Peak Current Mode Control) 5.7.1.2 DPWM Module The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138A system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations. The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the duty ratio as a 24bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 21 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple power stages can be tightly controlled. The DPWM logic is probably the most complex of the Digital Peripherals. It receives the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section. Each DPWM module supports the following features: • Dedicated 14 bit time-base with period and frequency control • Shadow period register for end of period updates. • Quad-event control registers (A and B, rising and falling) (Events 1 to 4) – Used for on/off DPWM duty ratio updates. • Phase control relative to other DPWM modules • Sample trigger placement for output voltage sensing at any point during the DPWM cycle. • Support for two independent edge placement DPWM outputs (same frequency or period setting) • Dead-time between DPWM A and B outputs • High Resolution capabilities – 250 ps • Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps) • Active high/ active low output polarity selection • Provides events to trigger both CPU interruptions and start of ADC12 conversions. 5.7.1.3 DPWM Events Each DPWM can control the following timing events: 1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. The clock controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250 MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Oversampling can be set for 2, 4, or 8 times the sampling rate. 2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation). 3. Period – low resolution switching period count. (count of PCLK cycles) 4. Event 1 – count offset for rising DPWM A event. (PCLK cycles) 5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments. Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4. Figure 5-5 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed. 22 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Start of Period Start of Period Period Period Counter DPWM Output A Event 1 Event 2 (High Resolution) Cycle Adjust A (High Resolution) Sample Trigger 1 To Other Modules Blanking A Begin Blanking A End DPWM Output B Event 3 (High Resolution) Event 4 (High Resolution) Cycle Adjust B (High Resolution) Sample Trigger 2 Blanking B Begin To Other Modules Blanking B End Phase Trigger Events which change with DPWM mode: • DPWM A Rising Edge = Event 1 • DPWM A Falling Edge = Event 2 + Cycle Adjust A • DPWM B Rising Edge = Event 3 • DPWM B Falling Edge = Event 4 + Cycle Adjust B • Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 5-5. Multi Mode Open Loop Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 23 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 5.7.1.4 www.ti.com High Resolution DPWM Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138A DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the resolution of the clock driving the DPWM module. This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz. The high resolution section of DPWM can be enabled or disabled, and the resolution can be defined in several steps between 4 ns to 250 ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN and HIRES_SCALE inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details. 5.7.1.5 Oversampling The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X. 5.7.1.6 DPWM Interrupt Generation The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 5-1 outlines the divide ratios that can be programmed. 5.7.1.7 DPWM Interrupt Scaling/Range Table 5-1. DPWM Interrupt Divide Ratio Interrupt Divide Interrupt Divide Setting Count 24 Interrupt Divide Count (hex) Switching Period Frames (Assume 1-MHz Loop) Number of 32-MHz Processor Cycles 32 1 0 00 1 2 1 01 2 64 3 3 03 4 128 4 7 07 8 256 5 15 0F 16 512 6 31 1F 32 1024 7 47 2F 48 1536 8 63 3F 64 2048 9 79 4F 80 2560 10 95 5F 96 3072 11 127 7F 128 4096 12 159 9F 160 5120 13 191 BF 192 6144 14 223 DF 224 7168 15 255 FF 256 8192 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 5.7.1.8 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 DPWM Synchronization This section describes the register settings and hardware considerations necessary to modulate the DPWM pins with PCMC and internal slope compensation. DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to DPWM2, ½ period out of phase using these commands: Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1; LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2; // Slave to dpwm-0 // Slave to dpwm-1 // Slave to dpwm-2 If the event registers on the DPWMs are the same, the two pairs of signals are symmetrical. All code examples are taken from the PSFB EVM code, unless otherwise stated. 5.7.1.9 Synchronous Rectifier Dead-Time Optimization Peripheral The UCD3138A has an advanced dead time control interface where it can accept output signals from the UCD7138 device and optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-performance driver for secondary-side synchronous rectification (SR) with body diode conduction sensing. The device is suitable for high power high efficiency isolated converter applications where deadtime optimization is desired. The UCD7138 gate driver is a companion device to the UCD3138A highlyintegrated digital controller for isolated power. Rising edge optimization control UCD3138A UCD7138 6 CTRL 5 VD SR1 IN 1 DTC 2 VCC 4 SR1DPWM SR2DPWM 3 DPWM module OUT Dead-time control computation engine Rising edge optimization control DTC0 UCD7138 6 CTRL 5 VD 4 OUT SR2 IN 1 DTC 2 VCC 3 DTC1 Decoder Copyright © 2016, Texas Instruments Incorporated Figure 5-6. Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 25 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com DTC0 and DTC1 are received body diode conduction inputs from UCD7138. SR0_DPWM and SR1_DPWM are the DPWM waveforms for the SRs. The red and green edges are moving edges controlled by both the filter output and the DTC interface. In each cycle, right after the falling edge of the SR DPWM waveform, a body diode conduction time detection window is generated. The detection window is defined by both DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4-ns timer capture counts how long the body diode conducts. Then the DPWM turn off edge of the next cycle is adjusted accordingly. SR0_ DPWM ADJUST SR1_ DPWM DETECT DETECT ADJUST DTC0 DETECT DETECT DTC1 DETECT_ BLANK DETECT_LEN Figure 5-7. Timing Diagram of the DTC Interface Figure 5-8 shows how the turn off edge is adjusted based on the DTC measurement of the previous cycle. The A_ADJ and B_ADJ registers in DTCMONITOR are signed accumulators; default value is 0. A_CNT or B_CNT value 127 If in Manual Control Mode P = Manual Control register value P=1 TARGET_OFFSET P=0 TARGET_LOW P=-1 P = Manual Control register value Else if A_CNT or B_CNT < FLT_THRESH P = FLT_STEP Else if A_CNT or B_CNT < TARGET_LOW P=-1 Else if A_CNT or B_CNT > TARGET_LOW + TARGET_OFFSET P=1 Else P=0 FLT_THRESH P = FLT_STEP 0 Figure 5-8. DTC Interface Principle Based on the DTC measured, in the next cycle: • A_ADJ = A_ADJ + A_∆ • A_ADJ = A_ADJ + B_∆ 26 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 In each cycle, the A_ADJ and B_ADJ accumulator values are dynamically adjust the dead time. The ∆ value changes after the measured body diode conduction time. A_ADJ and B_ADJ have been measured and compared to the threshold values in automatic control mode. A_ADJ and B_ADJ can be controlled by firmware while in manual control mode. Other figures of this peripheral include negative current fault protection, consecutive fault counter, DTC input multiplexor, etc. For details, refer to the programmer's manual. Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 27 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Typical Temperature Characteristics 2.1 1.81 2 1.79 Voltage (V) EADC LSB Size (mV) 5.8 www.ti.com 1.9 1.8 1.7 1.77 1.75 Minimum Maximum Typical 1.73 1.6 −40 −20 0 20 40 60 Temperature (°C) 80 100 1.71 120 -50 0 G005a Figure 5-9. EADC LSB Size With 4X Gain (mV) vs Temperature 100 150 C001 Figure 5-10. BP18 Voltage vs Temperature ADC12 Measurement Temperature Sensor Voltage ADC12 2.5-V Reference 2.515 2.6 2.510 ADC12 Reference 2.4 Sensor Voltage (V) 50 Temperature (ƒC) 2.2 2.0 1.8 2.505 2.500 2.495 2.490 2.485 1.6 2.480 1.4 −60 −40 −20 0 20 40 60 80 Temperature (°C) 2.475 −40 100 120 140 160 Figure 5-11. ADC12 Measurement Temperature Sensor Voltage vs Temperature 8 0 20 40 60 Temperature (°C) 80 100 120 G003b Figure 5-12. ADC12 2.5-V Reference vs Temperature ADC12 Temperature Sensor Measurement Error 2.08 2-MHZ Reference (Hz) 6 ADC12 Error (LSB) −20 G006b 4 2 0 2.04 2 1.96 −2 −4 −40 −20 0 20 40 60 Temperature (°C) 80 100 120 G002b Figure 5-13. ADC12 Temperature Sensor Measurement Error vs Temperature 28 1.92 −40 −20 0 20 40 60 Temperature (°C) 80 100 120 G004b Figure 5-14. Oscillator Frequency (2-MHz Reference, Divided Down from 250 MHz) vs Temperature Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 6 Parametric Measurements Information 6.1 Power-On Reset (POR) and Brown-Out Reset (BOR) ADC Output Code INL best fit INL end point Actual ADC transfer function Best fit line Line connecting actual zero-scale point and actual full-scale point ADC Input Voltage Figure 6-1. Best Fit INL and End Point INL V33D 3.3 V Brown Out VGH VGL VRES IRESET tPOR tPOR undefined Figure 6-2. Power-On Reset (POR) and Brown-Out Reset (BOR) Table 6-1. Power-On Reset (POR) and Brown-Out Reset (BOR) Term Definitions TERM DEFINITION VGH V33D threshold where the internal power is declared good. The device exits the reset state when above this threshold. VGL V33D threshold where the internal power is declared bad. The device enters reset state when below this threshold. Vres V33D threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state. IReset The internal reset signal. When low, the device is held in reset. This is equivalent to holding the device reset pin high. tPOR The time delay from when the VGH threshold exceeded to when the device exits the reset state. Brown-out The V33D voltage threshold at which the device sets the brown out status bit. An interrupt can be triggered if enabled. Parametric Measurements Information Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 29 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 7 Detailed Description 7.1 Overview The UCD3138A family is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single chip solution. The UCD3138, in comparison to Texas Instruments UCD3138A digital power controller offers 32 kB of program Flash memory. The flexible nature of the UCD3138A family makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138A family is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customer’s development effort through offering best in class development tools, including application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power Development GUI which enables customers to configure and monitor key system parameters. 7.2 ARM Processor The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit microprocessors. The ARM architecture is based on RISC (reduced instruction set computer) principles where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the performance of the 32-bit microprocessor. The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter. 7.3 Memory The UCD3138A (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the memory modules. All of the memory module addresses are sequentially aligned along the same address range. This applies to program flash, data flash, ROM and all other peripherals. Within the UCD3138A architecture, there is a Boot ROM that contains the initial firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches to the main FLASH-program execution. UCD3138A also supports customization of the boot program by allowing an alternative boot routine to be executed from program FLASH. This feature enables assignment of a unique address to each device; therefore, enabling firmware reprogramming even when several devices are connected on the same communication bus. Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x 32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded error correction code (ECC). For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1 k x 32 bit array. 30 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.3.1 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 CPU Memory Map and interruptions When the device comes out of power-on-reset, the data memories are mapped to the processor as follows: Table 7-1. Memory Map (After Reset Operation) Address Size Module 16 X 4K Boot ROM 0x0001_0000 – 0x0001_7FFF 32K Program flash 0x0001_8800 – 0x0001_8FFF 2K Data flash 0x0001_9000 – 0x0001_9FFF 4K Data RAM 0x0000_0000 – 0x0000_FFFF In 16 repeated blocks of 4K each Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as follows: Table 7-2. Memory Map (Normal Operation) Address Size Module 0x0000_0000 – 0x0000_7FFF 32K Program flash 0x0001_0000 – 0x0001_AFFF 4K Boot ROM 0x0001_8800 – 0x0001_8FFF 2K Data flash 0x0001_9000 – 0x0001_9FFF 4K Data RAM Table 7-3. Memory Map (System and Peripherals Blocks) Address Size Module 0x0002_0000 - 0x0002_00FF 256 Loop Mux 0x0003_0000 - 0x0003_00FF 256 Fault Mux 0x0004_0000 - 0x0004_00FF 256 ADC 0x0005_0000 - 0x0005_00FF 256 DPWM 3 0x0006_0000 - 0x0006_00FF 256 Filter 2 0x0007_0000 - 0x0007_00FF 256 DPWM 2 0x0008_0000 - 0x0008_00FF 256 Front End/Ramp I/F 2 0x0009_0000 - 0x0009_00FF 256 Filter 1 0x000A_0000 - 0x000A_00FF 256 DPWM 1 0x000B_0000 – 0x000B_00FF 256 Front End/Ramp I/F 1 0x000C_0000 - 0x000C_00FF 256 Filter 0 0x000D_0000 - 0x000D_00FF 256 DPWM 0 0x000E_0000 - 0x000E_00FF 256 Front End/Ramp I/F 0 0xFFF7_EC00 - 0xFFF7_ECFF 256 UART 0 0xFFF7_ED00 - 0xFFF7_EDFF 256 UART 1 0xFFF7_F000 - 0xFFF7_F0FF 256 Miscellaneous Analog Control 0xFFF7_F600 - 0xFFF7_F6FF 256 PMBus Interface 0xFFF7_FA00 - 0xFFF7_FAFF 256 GIO 0xFFF7_FD00 - 0xFFF7_FDFF 256 Timer 0xFFFF_FD00 - 0xFFFF_FDFF 256 MMC 0xFFFF_FE00 - 0xFFFF_FEFF 256 DEC 0xFFFF_FF20 - 0xFFFF_FF37 23 CIM 0xFFFF_FF40 - 0xFFFF_FF50 16 PSA 0xFFFF_FFD0 - 0xFFFF_FFEC 28 SYS Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 31 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com The registers and bit definitions inside the system and peripheral blocks are detailed in the programmer’s guide for each peripheral. 7.3.2 Boot ROM The UCD3138A incorporates a 4k boot ROM. This boot ROM includes support for: • Program download through the PMBus • Device initialization • Examining and modifying registers and memory • Verifying and executing program FLASH automatically • Jumping to a customer defined boot program The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash. This permits full automated program memory checking, when there is no need for a custom boot program. If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface These functions can be used to read and write to all memory locations in the UCD3138A. Typically they are used to download a program to Program Flash, and to command its execution 7.3.3 Customer Boot Program It is possible to generate a user boot program using 2 kB or more of the program flash. This program can support features which the Boot ROM does not support, including: • Program download via UART. This program is useful especially for applications where the UCD3138A is isolated from the host (for example, PFC) • Encrypted download. This program is useful for code security in field updates. 7.3.4 Flash Management The UCD3138A offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware stores multiple copies of system parameters in data flash. This is minimizes the risk of losing information if programming is interrupted. 7.4 System Module The System Module contains the interface logic and configuration registers to control and configure all the memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder, memory management controller, system management unit, central interrupt unit, and clock control unit. 7.4.1 Address Decoder (DEC) The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are writable in the ARM privilege mode only to enable user mode protection. 32 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.4.2 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Memory Management Controller (MMC) The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space decoding. 7.4.3 System Management (SYS) The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available. 7.4.4 Central Interrupt Module (CIM) The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interruptions by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The request channels are maskable, allowing individual channels to be selectively disabled or enabled. Table 7-4. Interrupt Priority Table NAME MODULE COMPONENT OR REGISTER DESCRIPTION PRIORITY BRN_OUT_INT Brownout Brownout interrupt 0 (lowest) EXT_INT External interruptions Interrupt on external input pin 1 WDRST_INT Watchdog control Interrupt from watchdog exceeded (reset) 2 WDWAKE_INT Watchdog control Wakeup interrupt when watchdog equals half of set watch time 3 SCI_ERR_INT UART or SCI control UART or SCI error Interrupt. Frame, parity or overrun 4 SCI_RX_0_INT UART or SCI control UART0 RX buffer has a byte 5 SCI_TX_0_INT UART or SCI control UART0 TX buffer empty 6 SCI_RX_1_INT UART or SCI control UART1 RX buffer has a byte 7 SCI_TX_1_INT UART or SCI control UART1 TX buffer empty 8 PMBUS_INT PMBus related interrupt 9 DIG_COMP_INT 12-bit ADC control Digital comparator interrupt 10 FE0_INT Front End 0 “Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated” 11 FE1_INT Front End 1 “Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated” 12 FE2_INT Front End 2 “Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated” 13 PWM3_INT 16-bit timer PWM 3 16-bit Timer PWM3 counter overflow or compare interrupt 14 PWM2_INT 16-bit timer PWM 2 16-bit Timer PWM2 counter Overflow or compare interrupt 15 PWM1_INT 16-bit timer PWM 1 16-bit Timer PWM1 counter overflow or compare interrupt 16 PWM0_INT 16-bit timer PWM 0 16-bit Timer PWM1 counter overflow or compare interrupt 17 OVF24_INT 24-bit timer control 24-bit Timer counter overflow interrupt 18 DTC_FLT_INT DTC fault interrupt DTC module fault interrupt 19 COMP_1_INT 24-bit timer control 24-bit Timer compare 1 interrupt 20 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 33 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Table 7-4. Interrupt Priority Table (continued) NAME MODULE COMPONENT OR REGISTER DESCRIPTION CAPTURE_0_INT 24-bit timer control 24-bit Timer capture 0 interrupt 21 COMP_0_INT 24-bit timer control 24-bit Timer compare 0 interrupt 22 CPCC_INT Constant power constant current Mode switched in CPCC module Flag needs to be read for details 23 ADC_CONV_INT 12-bit ADC control ADC end of conversion interrupt 24 FAULT_INT Fault Mux interrupt Analog comparator interruptions, overvoltage detection, undervoltage detection, LLM load step detection 25 DPWM3 DPWM3 Same as DPWM1 26 DPWM2 DPWM2 Same as DPWM1 27 DPWM1 DPWM1 1) Every (1 to 256) switching cycles 2) Fault detection 3) Mode switching 28 DPWM0 DPWM0 Same as DPWM1 29 EXT_FAULT_INT External Faults Fault pin interrupt 30 SYS_SSI_INT System Software System software interrupt 7.5 PRIORITY 31 (highest) Feature Description 7.5.1 Sync FET Ramp and IDE Calculation The UCD3138A has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comes in two forms: • Sync FET ramp • Ideal Diode Emulation (IDE) calculation When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly, it may pull down the prebias voltage, causing the power supply to sink current. To avoid this, Sync FETs are not turned on until the power supply has ramped up to the nominal voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramp logic can be used to turn them on at a rate below the bandwidth of the filter. In discontinuous mode, the ideal on-time for the Sync FETs is a function of VIN, VOUT, and the primary side duty cycle (D). The IDE logic in the UCD3138A takes VIN and VOUT data from the firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync FETs. 7.5.2 Automatic Mode Switching Automatic Mode switching enables the DPWM module to switch between modes automatically. This is useful to increase efficiency and power range. The following paragraphs describe phase-shifted full bridge and LLC examples: 7.5.2.1 Phase Shifted Full Bridge Example Phase shifted full bridge topologies are shown in Figure 7-1 and Figure 7-2. 34 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 DPWM3A (QB1) DPWM3B (QT1) DPWM2A (QT2) DPWM2B (QB2) VTrans DPWM1B (QSYN1,3) DPWM0B (QSYN2,4) IPRI Figure 7-1. Phase Shifted Full Bridge Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 35 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com L1 T1 Q7 +12V Q6 VBUS C1 I_pri PRIM CURRENT RL ORING CTL Q5 T2 VOUT C2 D1 QT1 Lr R2 QT2 VA T1 QB1 Current Sensing QB2 D2 Vref Vout Duty for mode switching EADC0 CLA0 EADC1 CLA1 Load Current I_pri DPWM0B AD02/CMP0 I_SHARE Vout AD 03/CMP1/CMP2 AD04/CMP3 Iout AD05/CMP4 I_pri AD06/CMP5 DPWM1B DPWM2A PCM AD00 AD01 SYNCHRONOUS GATE DRIVE DPWM2B DPWM3A DPWM3B ISOLATED GATE Transformer EADC2 temp Primary FAULT CBC AD07/CMP6 AD08 AD09 Vin VA DPWM0B DPWM1 DPWM1B DPWM2 DPWM2A DPWM2B DPWM3 DPWM3A DPWM3B FAULT 0 ACFAIL_IN FAULT 1 ACFAIL_OUT FAULT 2 FAILURE CPCC < Iout DPWM0 ORING_CRTL GPIO2 ON/OFF GPIO3 P_GOOD WD ARM7 PMBus RST OSC UART 1 GPIO1 UART0 Memory Figure 7-2. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification 7.5.2.2 LLC Example In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC: Primary Q1T SynFET PWM Mode QSR1 fs= fr_max LLC Mode fr fs> fr fs< fr Q1B Tr= 1/fr Tr= 1/fr QSR2 I SEC (t ) 36 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 VBUS Q1T ILR(t) Transformer LRES QSR2 LK NS RLRES Q1B ILM(t) LM ISEC (t) Driver DPWM1B Oring Circuitry VOUT NP COUT1 NS RF1 COUT2 AD03 EAP0 VBUS ESR1 ESR2 RF2 QSR1 Rectifier and filter CRES VOUT(t) CF EAN0 AD04 RS Driver DPWM1A CS V CR(t) CRES RS1 RS2 Driver DPWM0B Driver DPWM0A ADC13 EAP1 Figure 7-3. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 37 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 7.5.2.3 www.ti.com Mechanism for Automatic Mode Switching The UCD3138A allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers. If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown in Figure 7-4. Automatic Mode Switching With Hysteresis Filter Duty Full Range Auto Config High High – Upper Threshold High – Lower Threshold Auto Config Mid Low – Upper Threshold Low – Lower Threshold Control Register 1 0 Figure 7-4. Automatic Mode Switching As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point. 38 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.5.3 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 DPWMC, Edge Generation, IntraMux The UCD3138A has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux. DPWMC is an auxillary signal inside the DPWM logic. It can be generated using the Blanking A begin time, and the Blanking A end time. The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can output a generated edge. The options are: 0 = DPWM(n) A Rising edge 1 = DPWM(n) A Falling edge 2 = DPWM(n) B Rising edge 3 = DPWM(n) B Falling edge 4 = DPWM(n+1) A Rising edge 5 = DPWM(n+1) A Falling edge 6 = DPWM(n+1) B Rising edge 7 = DPWM(n+1) B Falling edge Where “n" is the numerical index of the DPWM module of interest. For example n = 1 refers to DPWM1. The Edge Gen is controlled by the DPWMEDGEGEN register. The IntraMux (short for intra multiplexer) is controlled by the Auto Config registers. The IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are controlled with automatic mode switching. When disabled, DPWMA and DPWMB are driven as described in the Section 7.5.2 section. If the Intra Mux is enabled, the high-resolution feature must be disabled, and the DPWM edge resolution falls to 4 ns. The Edge Gen/Intra Mux is shown in Figure 7-5. A/B/C (N) A/B/C (N+1) C (N+2) C (N+3) INTRAMUX PWM A PWM B EDGE GEN A(N) B(N) A(N+1) B(N+1) EGEN A EGEN B B SELECT A SELECT A ON SELECT A OFF SELECT B ON SELECT B OFF SELECT Figure 7-5. Edge Gen/Intra Mux Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 39 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com A list of the IntraMux modes for DPWMA is as follows: 0 = DPWMA(n) pass through (default) 1 = Edge-gen output, DPWMA(n) 2 = DPWNC(n) 3 = DPWMB(n) (Crossover) 4 = DPWMA(n+1) 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) and for DPWMB: 0 = DPWMB(n) pass through (default) 1 = Edge-gen output, DPWMB(n) 2 = DPWNC(n) 3 = DPWMA(n) (Crossover) 4 = DPWMA(n+1) 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply: 7.5.4 DPWM(n) DPWM3 DPWM(n+1) DPWM0 DPWM(n+2) DPWM1 DPWM(n+3) DPWM2 Filter The UCD3138A filter is a PID filter with many enhancements for power supply control. Some of its features include: • Traditional PID Architecture • Programmable non-linear limits for automated modification of filter coefficients based on received EADC error • Multiple coefficient sets fully configurable by firmware • Full 24-bit precision throughout filter calculations • Programmable clamps on integrator branch and filter output • Ability to load values into internal filter registers while system is running • Ability to stall calculations on any of the individual filter branches • Ability to turn off calculations on any of the individual filter branches • Duty cycle, resonant period, or phase shift generation based on filter output. • Flux balancing • Voltage feed forward 40 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Limit Comparator Limit 6 Limit 5 ….. PID Filter Branch Stages Limit 0 Kp Coef Coefficient select EADC_DATA 16 Xn 24 9 24 X P Xn-1 Reg Ki Coef 9 Ki_yn reg 9 Optional Selected by KI_ADDER_ MODE 9 9 9 + Ki High 24 16 24 24 24 Clamp + X 24 24 I 24 Ki Low Kd alpha 9 Kd coef 16 Xn–Xn-1 - 9 24 X Kd yn_reg 32 Round 24 9 9 24 X + 24 24 24 Clamp D Figure 7-6. First Section of the Filter The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole. The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve transient response. Tthe output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits) is shown in Figure 7-7 24 P 24 I 24 D Filter Yn Clamp High Yn Scale + 26 S2.23 24 24 Saturate Yn S0.23 24 Shifter S0.23 Clamp Filter Yn S0.23 Filter Yn Clamp Low All are S0.23 Figure 7-7. Output Section of the Filter This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 41 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com The final section for the filter, which permits its output to be matched to the DPWM is shown in Figure 7-8. Filter YN S0.23 24 KCompx 14.0 DPWMx Period 14.0 X 38 S14.23 Round to 18 bits, Clamp to Positive 18 14.4 Truncate low 4 bits 14 Filter Period Bits [17:4] 14.0 14 14.0 PERIOD_MULT_SEL Figure 7-8. Final Section for the Filter This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode, the filter can be used to generate both period and duty cycle. Filter Output Clamp High Filter YN (Duty %) S0.23 24 KCompx X 38 S14.23 Round to 18 bits, Clamp to Positive 18 Clamp 14.4 18 Filter Duty 14.4 14.0 DPWMx Period 14.0 Loop_VFF 14.0 14 Filter Output Clamp Low 14.0 Resonant Duty 14.0 OUTPUT_MULT_SEL Figure 7-9. Resonant Mode 7.5.4.1 Loop Multiplexer The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and DPWM can be combined with each other in many configurations. It • • • • • also controls the following connections: DPWM to Front End Front End DAC control from Filters or Constant Current/Constant Power Module Filter Special Coefficients and Feed Forward DPWM synchronization Filter to DPWM The following control modules are configured in the Loop Mux: • Constant Power/Constant Current • Cycle Adjustment (Current and flux balancing) 42 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com • • • 7.5.4.2 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Global Period Light Load (Burst Mode) Analog Peak Current Mode Fault Multiplexer In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138A provides an extensive array of multiplexers that are united under the name Fault Mux module. The Fault Mux Module supports flexible mapping between fault sources and fault response mechanism inside each DPWM module. • Many fault sources can be mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A. • A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules. FAULT MUX CBC_PWM _AB_EN DPWM Bit 20 in DPWMCTRL0 CYCLE BY CYCLE ANALOG PCM FAULT - CBC FAULT MODULE AB FLAG DISABLE PWM A AND B CBC_FAULT_EN Bit30 in DPWMFLTCTRL FAULT - AB FAULT MODULE AB FLAG DISABLE PWM A AND B DCOMP – 4X EXT GPIO– 4X ACOMP – 7X FAULT -A FAULT -B FAULT MODULE FAULT MODULE A FLAG B FLAG ALL_FAULT_EN DPWM _EN Bit 31 in DPWMFLTCTRL Bit 0 in DPWMCTRL0 DISABLE PWM A ONLY DISABLE PWM B ONLY Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 43 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com The Fault Mux Module provides a multitude of fault protection functions within the UCD3138A high-speed loop (front end control, filter, DPWM and loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module. Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module. The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the output it affects under a fault condition. FAULT FLAG FAULT IN DPWM EN FAULT EN MAX COUNT FAULT MODULE Figure 7-10. Fault Module All fault modules are capable of detecting faults only once per DPWM switching cycle. Each one of the fault modules have a separate max_count value and the device sets the fault flag only when the sequential faults count exceeds the max_count value. After the fault flag is set, DPWMs must be disabled by DPWM_EN going low in order to clear the fault flags. NOTE All four fault modules share the same DPWM_EN control. The device clears all fault flags (output of fault modules) simultaneously. All four Fault Modules share the same global FAULT_EN as well. Therefore, a specific Fault Module cannot be enabled/ disabled separately. FAULT - CBC CYCLE BY CYCLE CLIM Figure 7-11. Cycle by Cycle Block In contrast to the fault modules, only one cycle by cycle block is available in each DPWM module. The cycle by cycle block can work in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from analog peak current mode (PCM) module. The fault Mux module supports the following basic functions: • 4 digital comparators with programmable thresholds and fault generation • Configuration for 7 high-speed analog comparators with programmable thresholds and fault generation • External GPIO detection control with programmable fault generation • Configurable DPWM fault generation for DPWM current limit fault, DPWM overvoltage detection fault, DPWM A external fault, DPWM B external fault and DPWM IDE flag • Clock failure detection for high and low frequency oscillator blocks 44 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com • SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Discontinuous conduction mode detection HFO/LFO Fail Detect DCM Detection Digital Comparator 0 Control Front End Control 0 Digital Comparator 1 Control Front End Control 1 Digital Comparator 2 Control Front End Control 2 Digital Comparator 3 Control fault[2:0] External GPIO Detection DPWM 0 Fault Control DPWM 1 Fault Control DPWM 2 Fault Control DPWM 3 Fault Control DPWM 0 DPWM 1 DPWM 2 DPWM 3 Analog Comparator 0 Control Analog Comparator 0 Analog Comparator 1 Control Analog Comparator 1 Analog Comparator 2 Control Analog Comparator 2 Analog Comparator 3 Control Analog Comparator 3 Analog Comparator 4 Control Analog Comparator 4 Analog Comparator 5 Control Analog Comparator 5 Analog Comparator 6 Control Analog Comparator 6 Analog Comparator Automated Ramp Figure 7-12. Fault Mux Block Diagram 7.5.5 Communication Ports 7.5.5.1 SCI (UART) Serial Communication Interface A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous startstop serial data communication (see the pin out sections for details) Each interface has a 24 bit for supporting programmable baud rates and has programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used. Both the UART ports support Hardware auto baud correction improving robustness in communication even at higher baud rates. 7.5.5.2 PMBus Interfacte The PMBus Interface supports independent master and slave modes controlled directly by firmware through a processor bus interface. Individual control and status registers enable firmware to send or receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol Specification (PMBus 1.3). The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface connects directly to the I2C/SMBus/PMBus Clock, Data, Alert, and Control signals. Example: PMBus Address Decode via ADC12 Reading Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 45 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is captured by the internal 12-bit ADC. RADDSET is the resistor that sets the PMBus address. Bin(VAD0x) is the address bin for one of 12 address as shown in Figure 7-13. VDD AD00 ON/OFF Control IBIAS RADDSET AD01 To ADC MUX Figure 7-13. PMBus Address Detection Method 7.5.5.3 General Purpose ADC12 The ADC12 is a 12-bit, high speed analog-to-digital converter, equipped with the following options: • Typical conversion speed of 267 ksps • Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence • Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples • Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIG pin or Analog Comparator results • Interrupt capability to embedded processor at completion of ADC conversion • Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or averaged ADC data • Two 10 µA current sources for excitation of PMBus addressing resistors • Dual sample and hold for accurate power measurement • Internal temperature sensor for temperature protection and monitoring The control module ADC12 Contol Block Diagram contains the control and conversion logic for autosequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channels can be sampled in any desired order or programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16. Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical Characteristics plots for the temperature variation associated with this function. 46 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 ADC12 Block ADC12 Registers ADC Averaging S/H ADC Channels 12-bit SAR ADC ADC12 Control Digital Comparators ADC Channel ADC External Trigger (from pin) DPWM Modules Analog Comparators Figure 7-14. ADC12 Control Block Diagram 7.5.5.4 Timers External to the Digital Power Peripherals there are 3 different types of timers in UCD3138A . They are the 24-bit timer, 16-bit timer and the Watchdog timer 7.5.5.4.1 24-bit PWM Timer There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data Buffer register) which can be used to store CPU updates of the compare events while still using the timer. The selected shadow register update mode happens after the compare event matches. The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can be set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored in the corresponding capture data register. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by software controlled register. Five interruptions from the PWM timer can be set, which are the counter rollover event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be disabled or enabled. Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as general purpose I/O for reading the value of the input at the pin. The first compare event can only be used as an interrupt. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 47 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 7.5.5.4.2 16-Bit PWM Timers There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register) which can be used to store CPU updates of compare events while still using the timer. The selected shadow register update mode happens after the compare event matches. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software controlled register. interruptions from the PWM timer can be set due to the counter rollover event (overflow) or by the two comparison match events. Each comparison match and the overflow interruptions can be disabled or enabled. Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the value of the input at the pin. 7.5.5.4.3 Watchdog Timer A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided for status monitoring of the watchdog. 7.5.6 Miscellaneous Analog The Miscellaneous Analog Control (MAC) Registers provide control and monitor a wide variety of functions. These functions include device supervisory features such as brown-out and power saving configuration, general purpose input and output configuration and interfacing, internal temperature sensor control and current sharing control. The MAC module provides trim signals to the oscillator and AFE blocks. These controls are usually used at the time of trimming at manufacturing; therefore this data sheet does not include any descriptions of these trim controls. The MAC registers and peripherals are all available in the 64-pin version. Other UCD3138A devices may have reduced resources. See also the Section 4 section. 7.5.7 Package ID Information Package ID register includes information regarding the package type of the device and can be read by firmware for reporting through PMBus or for other package sensitive decisions. BIT NUMBER Bit Name 7.5.8 1:0 PKG_ID Access R/W Default 0 – UCD3138A RHA Brownout Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition that may be considered unsafe for proper operation of the device. The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower than brownout threshold, it still does not necessarily trigger a device reset. The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an interrupt service routine. See . 48 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.5.9 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Global I/O Up to 30 pins in the UCD3138A device can be configured to serve as a general purpose input or output pin (GPIO). This includes all digital input or output pins except for the RESET pin. The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins, EADC analog input pins and the RESET pin. There are two ways to configure and use the digital pins as GPIO pins: • Through the centralized Global I/O control registers. • Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO functionality. The Global I/O registers offer full control of: • Configuring each pin as a GPIO. • Setting each pin as input or output. • Reading the pin’s logic state, if it is configured as an input pin. • Setting the logic state of the pin, if it is configured as an output pin. • Configuring pin/pins as open drain or push-pull (Normal) The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control Register, Global I/O Value Register and Global I/O Read Register. The following is showing the format of Global I/O EN Register (GLBIOEN) as an example: BIT NUMBER 29:0 Bit Name GLOBAL_IO_EN Access R/W Default 00_0000_0000_0000_0000_0000_0000_0000 Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins 0 = Control of IO is done by the functional block assigned to the IO (Default) 1 = Control of IO is done by Global IO registers. BIT PIN_NAME PIN NUMBER UCD3138A-64 PINS UCD3138A-40 PINS 29 FAULT[3] 43 NA 28 ADC_EXT_TRIG 12, 26 8 27 TCK 37 21 26 TDO 38 20 25 TMS 40 24 24 TDI 39 23 23 SCI_TX[1] 29 NA 22 SCI_TX[0] 14 22 21 SCI_RX[1] 30 NA 20 SCI_RX[0] 13 23 19 TMR_CAP 12, 26, 41 8, 21 18 TMR_PWM[1] 32 NA 17 TMR_PWM[0] 12, 26, 31, 37 21 16 PMBUS-CLK 15 9 15 PMBUS-DATA 16 10 14 CONTROL 30 20 13 ALERT 29 19 12 EXT_INT 26, 34 NA Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 49 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com PIN NUMBER BIT PIN_NAME 11 FAULT[2] 42 25 10 FAULT[1] 36 23 9 FAULT[0] 35, 39 22 8 SYNC 12, 26,37 8, 21 7 DPWM3B 24 18 5 DPWM2B 22 16 4 DPWM2A 21 15 3 DPWM1B 20 14 2 DPWM1A 19 13 1 DPWM0B 18 12 0 DPWM0A 17 11 UCD3138A-64 PINS UCD3138A-40 PINS 7.5.10 Temperature Sensor Control Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The internal temperature sensor is disabled as default. Temp Cal Temperature Sensor ADC 12 Ch14 Figure 7-15. Internal Temp Sensor Temperature sensor is calibrated at room temperature (25°C) via a calibration register value. The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement). The temperature sensor can be enabled or disabled. 7.5.11 I/O Mux Control In different packages of UCD3138A several I/O functions are multiplexed and routed toward a single physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be assigned to a physical device pin for your application. 7.5.12 Current Sharing Control UCD3138A provides three separate modes of current sharing operation. • Analog bus current sharing • PWM bus current sharing • Master/Slave current sharing • AD02 has a special ESD protection mechanism that prevents the pin from pulling down the currentshare bus if power is missing from the UCD3138A 50 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 The simplified current sharing circuitry is shown in the drawing below: 3.3 V ISHARE SW3 Digital 3.3 V 3.3V ESD 3. 2 kΩ 400 Ω 250 Ω AD02 AD13 SW2 ESD SW1 ESD 250 Ω EXT CAP R SHARE ADC12 and CMP ADC12 and CMP Figure 7-16. Simplified Current Sharing Circuitry FOR TEST ONLY, ALWAYS KEEP 00 CS_MODE EN_SW1 EN_SW2 DPWM Off or Slave Mode (3-state) 00 00 (default) 0 0 0 PWM Bus 00 01 1 0 ACTIVE Off or Slave Mode (3-state) 00 10 0 0 0 Analog Bus or Master 00 11 0 1 0 CURRENT SHARING MODE The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be controlled through the current sharing control register (CSCTRL). 7.5.13 Temperature Reference The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal temperature sensor (channel 14) during the factory trim and calibration. This information can be used by different periodic temperature compensation routines implemented in the firmware. But it should not be overwritten by firmware, otherwise this factory written value is lost. 7.1 Device Functional Modes The DPWM is a complex logic system which is highly configurable to support several different power supply topologies. This section discusses waveforms, timing, and register settings, rather than ON-logic design. The DPWM functions using a period counter, which increments from 0 to PRD, then resets and begins to increment again. The DPWM logic causes transitions in many digital signals when the period counter reaches the target value for that signal. Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 51 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 7.1.1 www.ti.com Normal Mode In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies. The drawing of the Normal Mode waveforms is shown in Figure 7-1. Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for external delays, such as MOSFET and gate driver turn on times. Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges are dynamic, so blanking is more difficult. Cycle Adjust B has no effect in Normal Mode. Start of Period Start of Period Period Period Counter xx xx Filter controlled edge DPWM Output A Event 1 Filter Duty (High Resolution) Cycle Adjust A (High Resolution) Adaptive Sample Trigger A x x Adaptive Sample Trigger B Sample Trigger 1 To Other Modules Blanking A Begin Blanking A End DPWM Output B Event 3 ± Event 2 (High Res) To Other Modules Event 4 (High Res) DTC Adjustment Sample Trigger 2 Blanking B Begin Blanking B End Phase Trigger xx xx x x Events which change with DPWM mode: • DPWM A Rising Edge = Event 1 • DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A • Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or • Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register • DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2) • DPWM B Falling Edge = Event 4 + DTC Adjustment • Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 7-1. Normal Mode Closed Loop 52 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.1.2 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 DPWM Multiple Output Mode The device uses multi-mode functionality in systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase. The diagram for Multi-Mode is shown in Figure 7-2. Event 2 and Event 4 are not relevant in Multi mode. DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse width operation is possible. DPWMA cannot cross over the period boundary. Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking this rising edge. Cycle Adjust B is usable on DPWM B. Start of Period Start of Period Period Period Counter Filter controlled edge DPWM Output A Event 1 Filter Duty (High Resolution) Cycle Adjust A (High Resolution) DTC Adjustment x x xx xx Adaptive Sample Trigger A Adaptive Sample Trigger B Sample Trigger 1 To Other Modules Blanking A Begin Blanking A End DPWM Output B Event 3 (High Resolution) x x x x Filter Duty (High Resolution) Cycle Adjust B (High Resolution) DTC Adjustment Sample Trigger 2 Blanking B Begin Blanking B End To Other Modules Phase Trigger Events which change with DPWM mode: • DPWM A Rising Edge = Event 1 • DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A + DTC Adjustment • Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or • Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register • DPWM B Rising Edge = Event 3 • DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B + DTC Adjustment • Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 7-2. Multi Mode Closed Loop Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 53 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 7.1.3 www.ti.com DPWM Resonant Mode This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the switching frequency changes, the dead times between the pulses remain the same. The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as described in Section 7.5.2.2. The diagram of this mode is shown in Figure 7-3. The filter has two outputs, filter duty and filter period. In this case, the Filter is configured so that the filter period is twice the filter duty. So when there were no dead times, each DPWM pin in ON for half of the period. For dead-time handling, the device substracts the average of the two dead times from the filter duty for both DPWM pins. Therefore, both pins have the same ON-time, and the dead times are fixed regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the only edge for which the blanking signals can be used easily. Start of Period Start of Period Filter Period Period Counter Filter controlled edge DPWM Output A x x x x Event 1 Filter Duty ± 2 x Event 1 DTC Adjustment Adaptive Sample Trigger A Adaptive Sample Trigger B Sample Trigger 1 To Other Modules Blanking A Begin Blanking A End x x x x x x DPWM Output B 2 x Event 1 To Other Modules xx xx Event 1 DTC Adjustment Sample Trigger 2 Blanking B Begin Blanking B End Phase Trigger Events which change with DPWM mode: • DPWM A Rising Edge = Event 1 • DPWM A Falling Edge = Filter Duty – Event 1 • Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or • Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register • • • DPWM B Rising Edge = Filter Duty + Event 1 DPWM B Falling Edge = Filter Period – Event 1 Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 7-3. Resonant Symmetrical Closed Loop 54 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 7.1.4 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Triangular Mode Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM-B is available. The diagram for Triangular Mode is shown in Figure 7-4. All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center of the on-time does not move in this mode. Start of Period Start of Period Period Period Counter DPWM Output A Sample Trigger 1 To Other Modules Blanking A Begin Blanking A End Filter controlled edge DPWM Output B Cycle Adjust A (High Resolution) Cycle Adjust B (High Resolution) Filter Duty/2 (High Resolution) Period/2 Sample Trigger 2 Blanking B Begin To Other Modules Blanking B End Phase Trigger Events which change with DPWM mode: • DPWM A Rising Edge = None • DPWM A Falling Edge = None • Adaptive Sample Trigger = None • DPWM B Rising Edge = Period / 2 - Filter Duty / 2 + Cycle Adjust A • DPWM B Falling Edge = Period / 2 + Filter Duty / 2 + Cycle Adjust B • Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 7-4. Triangular Mode Closed Loop Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 55 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 7.1.5 www.ti.com Leading Edge Mode Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time. The diagram of the Leading Edge Mode is shown in Figure 7-5. As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are mainly useful for the edges at the beginning and end of the period. Start of Period Start of Period Period Period Counter DPWM Output A Event 1 Filter Duty (High Resolution) Cycle Adjust A (High Resolution) Adaptive Sample Trigger A Adaptive Sample Trigger B Sample Trigger 1 Blanking A Begin To Other Modules Blanking A End DPWM Output B Event 2 - Event 3 (High Resolution) Event 4 (High Resolution) Sample Trigger 2 Blanking B Begin To Other Modules Blanking B End Phase Trigger Events which change with DPWM mode: • DPWM A Rising Edge = Event 1 • DPWM A Falling Edge = = Event 1 - Filter Duty + Cycle Adjust A • Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or • Adaptive Sample Trigger B = Event 1 - Filter Duty / 2 + Adaptive Sample Register • DPWM B Rising Edge = Event 4 • DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A - ( Event 2 – Event 3 ) • Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B • Begin, Blanking B End Figure 7-5. Leading Edge Closed Loop 56 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.2 Application Information The UCD3138A has an extensive set of fully-programmable, high-performance peripherals that make it suitable for a wide range of power supply applications. In order to make the part easier to use, TI has prepared an extensive set of materials to demonstrate the features of the device for several key applications. In each case the following items are available: 1. Full featured EVM hardware that demonstrates classic power supply functionality. 2. An EVM user guide that contains schematics, bill-of-materials, layout guidance and test data showcasing the performance and features of the device and the hardware. 3. A firmware programmers manual that provides a step-by-step walk through of the code. Table 8-1. Application Information APPLICATION EVM DESCRIPTION Phase shifted full bridge This EVM demonstrates a PSFB DC-DC power converter with digital control using the UCD3138A device. Control is implemented by using PCMC with slope compensation. This simplifies the hardware design by eliminating the need for a series blocking capacitors and providing the inherent input voltage feed-forward that comes from PCMC. The controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available to help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 360 W, or full output current of 30 A. LLC resonant converter This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the UCD3138A device. The controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available to help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 340 W, or full output current of 29 A. Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 57 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 8.3 www.ti.com Typical Application This section summarizes the PSFB EVM DC-DC power converter. L1 T1 Q7 +12V Q6 VBUS C1 RL I_pri PRIM CURRENT ORING CTL Q5 T2 VOUT C2 D1 QT1 Lr R2 QT2 VA T1 QB1 Current Sensing QB2 D2 Vref Vout Duty for mode switching EADC0 EADC1 EADC2 I_SHARE Vout DPWM0B DPWM1B DPWM2A SYNCHRONOUS GATE DRIVE DPWM2B DPWM3A DPWM3B ISOLATED GATE Transformer Iout I_pri temp Vin VA Primary DPWM1 DPWM1B DPWM2 DPWM2A DPWM2B CLA1 Load Current I_pri DPWM0B CPCC CLA0 < Iout DPWM0 PCM AD00 AD01 AD02/CMP0 AD03/CMP1/CMP2 AD04/CMP3 AD05/CMP4 AD06/CMP5 AD07/CMP6 AD08 AD09 UART1 DPWM3 FAULT UCD3139A CBC ARM7 OSC DPWM3A DPWM3B FAULT0 ACFAIL_IN FAULT1 ACFAIL_OUT FAULT2 FAILURE GPIO1 ORING_CRTL GPIO2 ON/OFF GPIO3 P_GOOD WD PMBus RST UART0 Memory Copyright © 2016, Texas Instruments Incorporated Figure 8-6. Phase-Shifted Full-Bridge Topology 58 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com 8.3.1 SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Design Requirements Table 8-2. Input Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT 350 385 420 V 420 V ALL SPECIFICATIONS at Vin = 400V and 25°C AMBIENT UNLESS OTHERWISE NOTED. Vin Input voltage range Normal Operating Vinmax Max input voltage Continuous Iin Input current Vin = 350V, Full Load Istby Input no load current Output current is 0A Von Undervoltage lockout Vhys 1.15 A 30 mA Vin Decreasing (input voltage is detected on secondary side) 340 V Vin Increasing 360 V Table 8-3. Output Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT ALL SPECIFICATIONS at Vin = 400V and 25°C AMBIENT UNLESS OTHERWISE NOTED. VO Output voltage setpoint No load on outputs Regline Line regulation All outputs; 360 ≤ Vin ≤ 420; IO = IOmax 0.5% Regload Load regulation All outputs; 0 ≤ IO ≤ IOmax; Vin = 400 V 1% (1) 12 Vn Ripple and noise IO Output current 5 Hz to 20 MHz η Efficiency at phase-shift mode Vo = 12 V, Io = 15 A 93% η Efficiency at PWM ZVS mode Vo = 12 V, Io = 15 A 93% η Efficiency at hard switching mode Vo = 12 V, Io = 15 A Vadj Output adjust range Vtr Transient response overshoot/undershoot tsettling Transient response settling time tstart Output rise time 10% to 90% of Vout V 100 0 mVpp 30 A 12.6 V 90% 11.4 50% load step at 1 AµS, min load at 2 A ±0.36 V 100 µS 50 mS Overshoot At startup fs Switching frequency Over Vin and IO ranges Ishare Current sharing accuracy 50% - Full load ±5% φ Loop phase margin 10% - Full load 45 ° G Loop gain margin 10% - Full load 10 dB (1) 2% 150 kHz Ripple and noise are measured with 10-µF Tantalum capacitor and 0.1-µF ceramic capacitor across output. 8.3.2 Detailed Design Procedure 8.3.2.1 PCMC (Peak Current Mode Control) PSFB (Phase-Shifted Full Bridge) Hardware Configuration Overview The hardware configuration of the UCD3138A PCMC PSFB converter contains two critical elements that are highlighted in the Section 8.3.2.2 and Section 5.7.1.8 sections. 8.3.2.2 DPWM Initialization for PSFB This section describes the key register settings and considerations necessary for the UCD3138A to generate the correct MOSFET waveforms for this topology. This maintains the proper phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set up required to function correctly with PCMC. The UCD3138A DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing these modules, see the UCD3138A Digital Power Peripherals Manual. Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 59 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Figure 8-7 shows the power stage of the PSFB. L1 T1 VOUT Q6 VBUS I_pri PRIM CURRENT Q5 T2 D1 QT1 Lr R2 QT2 T1 QB2 D2 DPWM1B SYNCHRONOUS GATE DRIVE DPWM2B DPWM2A DPWM3B DPWM3A ISOLATED GATE Transformer DPWM0B QB1 Figure 8-7. PSFB Power Stage Schematic 60 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Figure 8-8 shows an overview of the key PSFB signals. 3 A – QB1 ( DPWM1C ) 3 B – QT1 ( DPWM2 C) 2 B – QB2 ( EDGEGEN ) X1 Y3 2 A – QT 2 ( EDGEGEN) X3 Transformer Voltage Y2 X2 1B – QSYN 1,3 Y1 0B – QSYN 2,4 DPWM3 AF DPWM3 BF DPWM 2 AF DPWM 2 BF Peak Level Current . X 1 , X 2 , X 3 and Y 1 , Y 2 , Y 3 are sets of moving edges. All other edges are fixed Figure 8-8. Key PSFB Signals 8.3.3 Fixed Signals to Bridge The two top signals in Figure 8-8 have fixed timing. The DPWM1CF and DPWM2CF signals are used for these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown in Figure 8-9. Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 61 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Figure 8-9. Fixed Signals to Bridge These signals are actually routed to pins DPWM3A and 3B using the Intra Mux with these statements: Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 7; // Send DPWM1C Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 8; // Send DPWM2C Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6. Here are the statements which initialize them: 62 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 // Setup waveform for DPWM-C (re-using blanking B regs) Dpwm2Regs.DPWMBLKBBEG.all = PWM2_EV5 + (4 *16); Dpwm2Regs.DPWMBLKBEND.all = PWM2_EV6; Period End Period Start Controlled by DPWM1 Blanking register Blank B Begin 3 A – QB1 ( DPWM1 C) 3 B – QT1 ( DPWM 2 C) Blank B End Event 6 Event 5 Event 6 Event 5 Event 6 Blank B Begin Blank B End Controlled by DPWM2 Blanking register Figure 8-10. Blank B Timing Information The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for timing information. 8.3.4 Dynamic Signals to Bridge DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by cycle. The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The same PCMC triggering signal is applied to DPWM2 and DPWM3. Both of these are set to normal mode as well. DPWM2 and 3 are chopped and their edges are used to generate the next two dynamic signals to the bridge. They are generated using the Edge Generator Module in DPWM2. The Edge Generator sources are DPWM2 and DPWM3. The edges used are: DPWM2A DPWM2A DPWM2B DPWM2B turned on by a rising edge on DPWM2BF turned off by a falling edge on DPWM3AF turned on by a rising edge on DPWM3BF turned off by a falling edge on DPWM2AF Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 63 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com Period Start Period End 3 A – QB1 ( DPWM 1 C) 3 B – QT1 ( DPWM 2 C) 2 B – QB2 ( EDGEGEN ) 2 A – QT 2 ( EDGEGEN ) Y3 X3 1A 1B– QSYN 1,3 Normal Mode Dead time determined by events Y2 X2 0A Y1 0B – QSYN 2,4 X1 DPWM 3 AF DPWM 3 BF DPWM 2 AF DPWM 2 BF Peak Level Current Chopping point Chopping point X 1 , X 2 , X 3 and Y 1 , Y 2 , Y 3 are sets of moving edges. All other edges are fixed Figure 8-11. Dynamic Signals to Bridge The Edge Generator is configured with these statements: Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2; Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5; Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6; Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1; Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1; The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delay through the DPWM. The finial 6 gate signals are shown in Figure 8-12. 64 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Period Start Period End 3 A – QB1 ( DPWM 1 C) 3 B – QT1 ( DPWM 2 C) 2 B – QB2 ( EDGEGEN ) 2 A – QT 2 ( EDGEGEN ) Y3 X3 1 B – QSYN 1,3 Y2 X2 Y1 0 B – QSYN 2,4 X1 Peak Level Current Chopping point Chopping point Figure 8-12. Final 6 Gate Signals Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2 signals. Using the other 2 DPWMs permits these signals to have a different dead time. The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the falling edge on DPWMxAF. All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used, DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If no PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open loop mode. 8.3.5 System Initialization for PCM PCM (Peak Current Mode) is a specialized configuration for the UCD3138A which involves several peripherals. This section describes how it works across the peripherals. 8.3.5.1 Use of Front Ends and Filters in PSFB All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and voltage mode. The same hardware can be used for both control modes, with the mode determined by which firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is not used at all. FE0 – VOUT – voltage loop FE1 – IOUT – current loop FE2 – IPRI – PCM In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for the compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the current loop for the start point. Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 65 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 8.3.5.2 www.ti.com Peak Current Detection Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault Mux and the DPWMs. A drawing of the major elements is shown in Figure 8-13. Ipri PCM Comparator Loop Mux Fault Mux DPWM Vout Voltage Loop Filter Loop Mux Ramp Module Loop Mux Front End Figure 8-13. Peak Current Detection Function The voltage loop is used to select a peak current level. This level is fed to the Ramp module to generate a compensation ramp. The compensation ramp is compared to the primary current by the PCMC comparator in the Front End. When the ramp value is greater than the primary current, the APCMC signal is sent to the DPWM, causing the events described in the previous sections. The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case, each DPWM frame triggers the start of the ramp. The ramp steps every 32 ns. The PCM_FILTER_SEL bits in the LoopMux.PCMCTRL register are used to select which filter is connected to the ramp module: LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL = 0; //select filter0 With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control loop, with the EADCDAC set to high current. If the voltage loop value becomes higher than the current loop value, then Filter 1 is used to control the PCM ramp start value: LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL = 1; S P A C E //select filter1 for slope compensation source In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The RAMP_EN bit must be set, of course. The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course, so it is necessary to calculate the slope after the current to voltage conversion. Here is the formula for converting from millivolts per microsecond to DACSTEP. m = compensation slope in millivolts per microsecond ACSTEP = 335.5 × M In C, this can be written: #define COMPENSATION_SLOPE 150 //compensation slope in millivolts per microsecond #define DACSTEP_COMP_VALUE ((int) (COMPENSATION_SLOPE*335.5) ) S P A C E //value in DACSTEP for desired compensation slope S P A C E FeCtrl0Regs.DACSTEP.all = DACSTEP_COMP_VALUE; It may also be necessary to set a ramp ending value in the RAMPDACEND register. 66 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling the differential to single ended comparator function. The front end diagram leaves it out for simplicity, but the connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator, however, is single ended. So a conversion is necessary as shown in Figure 8-14. AFE_GAIN 23-AFE_GAIN EAP0 6 bit ADC 8mV/LSB AFE_GAIN EAN0 2 EADC X Signed 9 bit result (error) 1 mV /LSB Averaging SAR/Prebias Ramp Filter x DAC0 10 bit DAC 1.5625mV/LSB Differential to Single Ended CPCC Σ Value Dither 4 bit dithering gives 14 bits of effective resolution 97.65625μV/LSB effective resolution Absolute Value Calculation 10 bit result 1.5625mV/LSB Peak Current Detected Peak Current Mode Comparator Figure 8-14. Differential to Single-Ended Comparator Function The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode. The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but there are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is used: LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */ The PCM_EN bit must also be set. LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4 DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to connect the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration information on all of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to configure your hardware design using the same DPWMs, filters, and front ends for the same functions as the EVM. DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in the Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of the DPWM period. 8.3.5.3 Peak Current Mode (PCM) There is one peak current mode control module in the device however any front end can be configured to use this module. Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 67 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 8.3.6 www.ti.com Application Curves Transient 1 A to 16 A to 1 A ILOAD = 30 A VIN = 385 V syncFETs off Figure 8-16. VOUT Soft Start Figure 8-15. Load Transient Kp = 14000 Ki = 300 Kd = 2000 Alpha = –2 Figure 8-17. Bode Plot 68 Application and Implementation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 9 Power Supply Recommendations 9.1 Power Supply Decoupling and Bulk Capacitors • • Both 3.3 VD and 3.3 VA should have a local 4.7-μF capacitor placed as close as possible to the device pins. BP18 should have a 1-μF capacitor. 10 Layout 10.1 Layout Guidelines • • • • • • • • • • Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that one solid SGND is dedicated for return current path, referred to the layout example. Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has different ESL, Capacitance and ESR, and they have different frequency response. Avoid long traces close to radiation components, and place them into an internal layer, and it is preferred to have grounding shield, and in the end, add a termination circuit; Analog circuit such as ADC sensing lines needs a return current path into the analog circuitry; digital circuit such as GPIO, PMBus and PWM has a return current path into the digital circuitry; although with a single plane, still try to avoid to mix analog current and digital current. Don’t use a ferrite bead or larger than 3-Ω resistor to connect between V33A and V33D. Both 3.3VD and 3.3VA should have local 4.7-µF decoupling capacitors close to the device power pins, add visas to connect decoupling caps directly to SGND. Avoid negative current/negative voltage on all pins, so Schottky diodes may need to clamp the voltage; avoid the voltage spike on all pins more than 3.8 V or less than –0.3 V, add Schottky diodes on the pins which could have voltage spikes during surge test; be aware that a Schottky has relatively higher leakage current, which can affect the voltage sensing at high temperature. If V33 slew rate is less than 2.5 V/ms the RESET pin should have a 2.21-kΩ resistor between the reset pin and V33D and a 2.2-µF capacitor from RESET to ground. For more details please refer to the UCD3138 Family - Practical Design Guideline This capacitor must be located close to the device RESET pin. 2.2 µF between V33D and BP18 can be removed due to internal enhancement design. Configure unused GPIO pins to be inputs or connect them to the ground (DGND or SGND). For detailed practical design guideline refer to UCD3138 Family - Practical Design Guideline Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 69 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 10.2 Layout Example Figure 10-1. UCD3138A Layout Example 70 Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 Figure 10-2. UCD3138A Layout Example, Internal Plane Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 71 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). The following products support development of the your device device applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any your device device application. Hardware Development Tools: Extended Development System (XDS™) Emulator For a complete listing of development-support tools for the your device platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 11.1.1.1 Tools and Documentation The application firmware for UCD3138A is developed on Texas Instruments Code Composer Studio (CCS) integrated development environment (v6.x recommended). Device programming, real time debug and monitoring/configuration of key device parameters for certain power topologies are all available through the TI FUSION_DIGITAL_POWER_DESIGNER software. The FUSION_DIGITAL_POWER_DESIGNER software uses the PMBus protocol to communicate with the device over a serial bus using an interface adaptor known as the USB-TO-GPIO, available as an EVM from Texas Instruments. PMBus-based real-time debug capability is available through the Memory Debugger tool within the Device GUI module of the FUSION_DIGITAL_POWER_DESIGNER GUI, which represents a powerful alternative over traditional JTAG-based approaches. The software application can also be used to program the devices, with a version of the tool known as FUSION_MFR_GUI optimized for manufacturing environments. The FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and reporting capabilities. Programmer manuals are available offering detailed information regarding the application and usage of UCD3138A digital controller: 1. UCD3138A Digital Power Peripheral Programmer's Manual Key topics covered in this manual include: – Digital Pulse Width Modulator (DPWM) – Modes of Operation (Normal/Multi/Phase-shift/Resonant and so forth) – Automatic Mode Switching – DPWMC, Edge Generation and Intra-Mux – Front End – Analog Front End – Error ADC or EADC – Front End DAC – Ramp Module – Successive Approximation Register Module – Filter – Filter Math – Loop Mux – Analog Peak Current Mode 72 Device and Documentation Support Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A UCD3138A www.ti.com SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 – Constant Current/Constant Power (CCCP) – Automatic Cycle Adjustment – Fault Mux – Analog Comparators – Digital Comparators – Fault Pin functions – DPWM Fault Action – Ideal Diode Emulation (IDE), DCM Detection – Oscillator Failure Detection – Register Map for all of the above peripherals in UCD3138A 2. UCD3138A Monitoring and Communications Programmer’s Manual Key topics covered in this manual include: – ADC12 – Control, Conversion, Sequencing & Averaging – Digital Comparators – Temperature Sensor – PMBUS Addressing – Dual Sample and Hold – Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating) – PMBUS Interface – General Purpose Input Output (GPIO) – Timer Modules – PMBus – Register Map for all of the above peripherals in UCD3138A 3. UCD3138A ARM and Digital System Programmer’s Manual Key topics covered in this manual include: – Boot ROM and Boot Flash – BootROM Function – Memory Read/Write Functions – Checksum Functions – Flash Functions – Avoiding Program Flash Lock-Up – ARM7 Architecture – Modes of Operation – Hardware/Software Interrupts – Instruction Set – Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode) – Memory and System Module – Address Decoder, DEC (Memory Mapping) – Memory Controller (MMC) – Central Interrupt Module – Register Map for all of the above peripherals in UCD3138A 4. FUSION_DIGITAL_POWER_DESIGNER for Isolated Power Applications – User guide for Designer GUI – User guide for Device GUI – Firmware Memory Debugger – Manufacturing Tool (MFR GUI) In addition to the tools and documentation described above, for the most up to date information regarding evaluation modules, reference application firmware and application notes/design tips, please visit http://www.ti.com/product/ UCD3138A. Device and Documentation Support Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138A 73 UCD3138A SLUSC66E – MARCH 2015 – REVISED FEBRUARY 2017 www.ti.com 11.2 Documentation Support 11.2.1 References 1. 2. 3. 4. 5. 6. 7. 8. UCD3138A Digital Power Peripherals Programmer’s Manual UCD3138A Monitoring and Communications Programmer’s Manual UCD3138A ARM and Digital System Programmer’s Manual FUSION_DIGITAL_POWER_DESIGNER for Isolated Power Applications Code Composer Studio Development Tools v3.3 – Getting Started Guide ARM7TDMI-S Technical Reference Manual System Management Bus (SMBus) Specification PMBus™ Power System Management Protocol Specification 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks Code Composer Studio, Fusion Digital Power, E2E are trademarks of Texas Instruments. ARM7TDMI-S is a trademark of ARM. PMBus is a trademark of SMIF, Inc.. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical Packaging and Orderable Information 12.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 74 Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Links: UCD3138A Copyright © 2015–2017, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCD3138ARGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138A UCD3138ARGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138A UCD3138ARJAR ACTIVE VQFN RJA 40 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 UCD3138A UCD3138ARJAT ACTIVE VQFN RJA 40 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 UCD3138A UCD3138ARMHR NRND WQFN RMH 40 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138A UCD3138ARMHT NRND WQFN RMH 40 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of