UCD3138HSFBEVM-029

Using the UCD3138HSFBEVM-029 User's Guide Literature Number: SLUUA95A April 2013 – Revised September 2019 WARNING Always follow TI’s set-up and application instructions, including use of all interface components within their recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure your personal safety and the safety of those working around you. Contact TI’s Product Information Center http://support/ti./com for further information. Save all warnings and instructions for future reference. Failure to follow warnings and instructions may result in personal injury, property damage, or death due to electrical shock and/or burn hazards. The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified professional users having training, expertise, and knowledge of electrical safety risks in development and application of high-voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas Instruments. If you are not suitably qualified, you should immediately stop from further use of the HV EVM. 1. Work Area Safety: 1. Keep work area clean and orderly. 2. Qualified observer(s) must be present anytime circuits are energized. 3. Effective barriers and signage must be present in the area where the TI HV EVM and its interface electronics are energized, indicating operation of accessible high voltages may be 2 present, for the purpose of protecting inadvertent access. 4. All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related apparatus used in a development environment exceeding 50 VRMS/75 VDC must be electrically located within a protected Emergency Power Off (EPO) protected power strip. 5. Use a stable and non-conductive work surface. 6. Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand testing whenever possible. 2. Electrical Safety: 1. De-energize the TI HV EVM and all its inputs, outputs, and electrical loads before performing any electrical or other diagnostic measurements. Revalidate that TI HV EVM power has been safely de-energized. 2. With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring, measurement equipment hook-ups and other application needs, while still assuming the EVM circuit and measuring instruments are electrically live. 3. Once EVM readiness is complete, energize the EVM as intended. WARNING: while the EVM is energized, never touch the EVM or its electrical circuits as they could be at high voltages capable of causing electrical shock hazard. 3. Personal Safety: 1. Wear personal protective equipment e.g. latex gloves and/or safety glasses with side shields or protect EVM in an adequate lucent plastic box with interlocks from accidental touch. 4. Limitation for Safe Use: 1. EVMs are not to be used as all or part of a production unit. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated User's Guide SLUUA95A – April 2013 – Revised September 2019 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter 1 Introduction This EVM, UCD3138HSFBEVM-029 is to help evaluate the UCD3138RHA 40-pin digital control device in a 48-V telecom power conversion application and then to aid in UCD3138 design. The EVM is a standalone symmetrical Hard-Switching Full-Bridge (HSFB) DC-DC power converter. The UCD3138HSFBEVM-029 can be used as it is delivered without additional work, from either hardware or firmware, to evaluate a hard-switching symmetrical full-bridge DC-DC converter. This EVM allows for some of its design parameters to be re-tuned using a GUI based tool, called Texas Instruments Fusion Digital Power Designer. It is also possible to load custom firmware with user’s own definition and development. This user’s guide provides basic evaluation instruction from a viewpoint of system operation in a standalone symmetrical HSFB DC-DC power converter. WARNING High voltages are present on this evaluation module during operation and for a while even after power off. This module should only be tested by skilled personnel in a controlled laboratory environment. High temperature exceeding 60°C may be found during EVM operation and for a while even after power off. This EVM’s purpose is to facilitate the evaluation of digital control in a hard-switching full-bridge DC converter using the UCD3138, and cannot be tested and treated as a final product. Read and understand this user’s guide thoroughly before starting any physical evaluation. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 3 Description 2 www.ti.com Description The UCD3138HSFBEVM-029 demonstrates a symmetrical hard-switching full-bridge DC-DC power converter with digital control using the UCD3138RHA 40-pin device. This EVM includes preloaded firmware providing required control functions for an HSFB converter. For details of the firmware please contact TI. UCD3138HSFBEVM-029 accepts a DC input from 36 VDC to 72 VDC, and outputs a nominal 12 VDC with full output load power 360 W, or full output current 30 A. 2.1 Typical Applications • • • 2.2 Features • • • • • • • • • • • • • 4 48-V Telecom DC-DC Power Conversion Servers Telecommunication Systems Digitally Controlled and Standalone Hard Switching Full-Bridge DC-DC Power Conversion Voltage Mode Control Secondary Side Control DC Input from 36 VDC to 72 VDC 12 VDC Regulated Output from No Load to Full Load Full-Load Power 360 W, or Full-Load Current 30 A High Efficiency Constant Soft-Start Time Protection: Over Voltage, Under Voltage, Over Current, and Over Temperature Constant Current and Constant Power Input Voltage Feed Forward Control PMBus Communications Test Points to Facilitate Device and Topology Evaluation Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Performance Specifications www.ti.com 3 Performance Specifications Table 1. UCD3138HSFBEVM-029 Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Characteristics Voltage operation range 36 Input UVLO On 72 VDC A 35 Input UVLO Off 32 Input current Input = 36 VDC, full load = 30 A 11 Input current Input = 48 VDC, full load = 30 A 9 Input current Input = 72 VDC, full load = 30 A 6 Output Characteristics Output voltage, VOUT No Load to full load Output load current, IOUT 36 to 72 VDC 12 Output voltage ripple 48 VDC and full load = 30 A VDC 30 A 30 mVpp 200 kHz Systems Characteristics Switching frequency Peak efficiency 48 VDC, load = 20 A 94.5% Full load efficiency 48 VDC, full load = 30 A 93.5% Operating temperature Typical 400 LFM forced air flow SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 25 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated ºC 5 6 15A 86V L2 2.2uF 2.2uF Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter OUTC 12 OUTD 11 CTRL 10 GND2 9 5 INC 6 IND 7 DISABLE 8 GND1 DRVQ_T1 DRVQ_T2 1uF C17 6.49k R21 200 R3 OUTB 13 4 INB DRVQ_B2 VAUXPRI OUTA 14 1uF C61 TP18 R48 22.1k C60 1uF C18 1uF Copyright © 2013–2019, Texas Instruments Incorporated 47pF C36 R49 4.99k 10nF C45 BZX84C5V6 D6 Q10 MMBT3904 TP20 VAUXPRI GND2 15 2 GND1 3 INA VCC2 16 1 VCC1 U5 ISO7240CF Secondary DRVQ_B1 0.1uF C62 3.3V_EXT Primary VAUXPRI 2.2uF 2.2uF 2.2uF 2.2uF C30 LO 8 VSS 7 LI 6 HI 5 1 VDD 3 HO 4 HS 0.1uF 2 HB U12 UCC27211 C44 TP22 R50 33.2 330pF C41 15.0k R47 VAUXPRI 220pF C43 OUT 6 GND 5 3 CS VCC 7 REF 8 R69 90.9k 4 RC 2 FB 1 COMP U8 UCC3813D-1 22.1k R53 TP9 +VIN 5V Primary side linear regulator 5V_PRI 0.1uF LI 6 HI 5 3 HO 4 HS 5V_PRI LO 8 VSS 7 1 VDD 0.1uF 2 HB U7 UCC27211 2.2uF C40 C26 C24 C12 C55 C9 TP3 Input Source Connection and Filter C80 C27 470nH +VIN Input Voltage = 36V to 72V DC Input Current Max = 12A TP2 48V Return J1 + 48V Input F1 4.7uF C63 1uF C64 TP21 TP19 2.2uF C51 BUS+ D11 0.1uF C42 D17 BAW56 10.0 R52 MBR0540 D15 10.0 MBR0540 R30 D16 10.0 MBR0540 R2 D18 R1 10.0k Q_B1 R8 10.0k 1.00k R71 1uF C65 R40 10.0k TP25 R5 10.0k 750 R60 47pF C57 3 7 6 2 5 8 4 1 1 3 C54 R74 20.0 R72 10.0 D3 C71 10nF SS24 D8 TP11 R106 10.0 2.2uF 1 R17 TP16 TP6 C73 0.1uF 150k R79 2.2uF 1nF C6 1uF D7 IS- TP14 CS- AD04 1 Parts not used VINSCALED 3.3VD 1 1 R45 R26 C1 1uF C2 -RS 4 3 2 10nF C35 1 C37 GND NC NC IN 9 FB/NC PWPD NC NC 5 6 7 8 -RS OUT U9 TPS715A33 ISHARE 1 C8 47uF 1 3 2 1 TP44 47uF C79 + TP10 10uF C85 C75 -VO 1000uF +VO 12V / 30A +Vout J3 P2 J4 Vout Return 3.3V_EXT 220 R94 R97 C10 47uF C3 1 C38 Max Output Power = 360W +RS 47uF +RS R15 15.0 47uF R16 15.0 3.3V Secondary side linear regulator 1.00 1uF C78 C86 TP4 R73 0 47uF R101 47uF C82 6V_UR +VO -VO DRVQ_SYN2 Scaled : 0 to 75V Input = 0 to 2V output 100pF C49 20.0k TP15 6V_UR Primary Current Sense CS+ 1 R38 INB 4 5 OUTB PWPD INA 2 GND 3 6 VDD 7 OUTA ENB 1 L1 2.2uH DRVQ_SYN1 U3 UCC27524 8 ENA MMBD7000 R93 U11 TLV2371 R93 and R79 set scale factor R9 1.00k C28 TP13 1.00 VAUXS 1.00 1.00 R107 R23 1.00 VAUXS TP12 VIN_CT R11 R10 1.00 R18 10.0k R28 10.0k C46 C5 Q5 Q1 1.00 R4 R108 Vinscaled Inverting Amplifier R82 49.9k SS24 Vin sample and hold R76 50.0k TP17 C70 47pF Q6 Q2 MMBD914 D1 Q4 1000pF C53 R14 20.0 Q3 21V at Vin=75 MMBD914 D5 R92 2.49k 1000pF R31 1.00k T1 100:1 17 16 12 11 T2 540 uH 8 7 BUS+ 8 1 T3 5:2:2 TP23 Q_T2 FDS2670 Q9 Q_B2 R59 3.01 Q_T1 BUS_ITRAN 10.0 MBR0540 R95 BUS_ITRAN Secondary Isolation Boundary Primary 4 9 TP1 +VIN Schematics www.ti.com Schematics Figure 1. UCD3138HSFBEVM-029 Schematics Sheet 1 of 3 SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 3.3VD 3.32k R56 3.3V_EXT P_GOOD +VO Copyright © 2013–2019, Texas Instruments Incorporated R70 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter EMI Control IS- 4.7nF 499 R7 3.3V_EXT ENABLE C16 10nF VINOK 3.32k Q11 16.2k R35 MMBT3904 3.3V_EXT -RS 0.1uF C33 U10 OPA344 1 9 10 11 12 13 14 15 1.50k R54 3.3VD 1 6 2 7 3 8 4 9 5 R33 1.74k ISEC 0.05 x Iout TP27 R20 EAP0 AD02 connect ISHARE 1.00k R32 49.9k 1.62k EAN0 C72 10nF 1 +VS 3 GND R12 1.00k -VO 11 1 C14 TP5 1 1 C23 1 1 6 7 8 11 10 9 R19 10.0k 0 C19 6V_UR 1 PWM0 4700pF AD02 1 R80 ISEC Interface to EADC2 R42 3.09k CS+ 0.0333 x Iout 1 1 1 1 1 1 1 TP34 TP35 TP36 TP37 TP24 TP26 TP28 TP38 1 DPWM0A DRVQ_B1 DPWM1A DRVQ_B2 TDI R105 0 1 Parts not used TCK TDO TMS 1 2 3 4 5 6 7 8 9 10 R104 10.0k J6 R99 33.2 J7 R96 10.0k 33.2 R100 33.2 R98 D10 SM05 R63 10.0k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R62 10.0k I2C Connector 33.2 R102 D4 SM05 DPWM1A DPWM0A DRVQ_B2 DRVQ_T1 DRVQ_T2 DRVQ_B1 DRVQ_SYN2 DRVQ_SYN1 DRVQ_T1 DRVQ_T2 3.3V_EXT DPWM - FET Interconnect Matrix 4 5 12 3 13 1 2 14 1 2 3 4 5 6 7 8 9 10 11 12 16 J2 J5 15 Share Bus Difference Amplifier 1.18k 0.1uF 1 R27 1 R44 ISHARE R22 1uF External Bias Input 1 TP40 TP39TP42 TP43 1uF ISEC 10nF C7 P1 1 TP41 TP31 TP29 TP30 C83 TP33 DPWM_1A DPWM_0A DPWM_3B DPWM_3A DPWM_2B DPWM_2A DPWM_1B DPWM_0B 3 C84 TP32 3.3V_EXT SCI_RX SCI_TX J8 Temp = 0.424 + .00625*T 2 Temperature sensor VOUT U6 LM60C AD06 V=1.2V at 12V input R36 ISEC AD13 10 Serial UART Interface C48 0.1uF 3.3V_EXT Current Sense Amplifier (Low Offset/ X50) 2 5 D13 RED 3 4 137k 47pF R61 C34 ROUT INVALID DIN FORCEON DOUT GND VCC FORCEOFF 16 Output voltage divider and noise filter R68 10.0k 499 R57 +RS 1.00k R41 C69 100pF 1.00k R58 3.3V_EXT IS- -VO R43 0.1uF 0.1uF RIN V- C2- C2+ C1- V+ C1+ EN C47 8 7 6 5 4 3 2 C32 LED Status indicators MMBT3904 Q7 D2 RED C29 0.1uF ON/OFF Manual Switching and noise conditioning S1 R13 499 R24 10.0k 3.32k R34 3.3V_EXT R64 10.0k 0.101 x Vout AD03 10pF 10pF EAP2 C68 R37 1.00k C67 AD01 FAILURE MMBD7000 D9 R84 1.82k MMBT3904 Q8 TP45 R29 2.00k D19 GREEN 1.00k C81 R6 10.0k R55 499 R85 16.2k D12 MMBD7000 VINSCALED 3.3VD R25 49.9k C31 0.1uF 1 U4 SN65C3221 1 INPUT VOLT SENSING Vin = 36V-100V 0.54V-1.52V 2 VIN_CT Opt1: Open J5, Use J2 for DPWM0-3 Opt2: Con J5, use DPWM0, DPWM1 JTAG Connector R103 10.0k PM_CLK PM_DATA PM_ALERT PM_CTRL www.ti.com Schematics Figure 2. UCD3138HSFBEVM-029 Schematics Sheet 2 of 3 7 Schematics www.ti.com Figure 3. UCD3138HSFBEVM-029 Schematics Sheet 3 of 3 8 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Test Setup www.ti.com 5 Test Setup 5.1 Test Equipment DC Voltage Source: capable of 36 VDC to 72 VDC, adjustable, with minimum power rating of 400 W, or current rating not less than 12 A, with current limit function. DC Multi-meter: 1 unit capable of 0 VDC to 75 VDC input range, four digits display preferred; and one unit capable of 0 VDC to 15 VDC input range, four digits display preferred. Output Load: DC load capable of receiving 0 VDC to 15 VDC, 0 A to 30 A, and 0 W to 360 W or greater, with display such as load current and load power. Current-meter, DC, optional in case the load has no display, one unit, capable of 0 A to 30 A. A low ohmic shunt and a DMM is recommended. Oscilloscope: capable of 500-MHz full bandwidth, digital or analog, if digital 5Gs/s or better. Fan: 400 LFM forced air cooling. Recommended Wire Gauge: capable of 30 A, or better than #14 AWG, with the total length of wire less than 8 feet (4 feet input and 4 feet return). 5.2 Recommended Test Setup J6 1 2 12 11 1 2 D19 16 15 S2 S1 J2 J5 5 6 UART0 (J8) 8 7 7 8 10 9 Reset 1 D14 J3 + TP10 - VIN + TP2 J4 J1 - Load TP44 TP1 Forced Air Flow Direction 400LFM Figure 4. UCD3138FBHSEVM-029 Recommended Test Set Up SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 9 Test Setup www.ti.com Figure 5. UCD3138HSFBEVM-029 Board Outlook 10 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated List of Test Points www.ti.com 6 List of Test Points Table 2. UCD3138HSFBEVM-029 List of Test Points TEST POINTS NAME TP1 +VIN Input Voltage positive DESCRIPTION TP2 PWRGND Input Voltage negative TP3 +BUS Input voltage after filter TP4 Voripple TP5 6V UR Bias TP6 PGND Secondary bias GND TP7 3.3VD 3.3VD TP8 AGND UCD3138 AGND TP9 VAUXPRI BNC Vo ripple Secondary Bias 6V_UR Primary side bias voltage TP10 +Vo TP11 VAUXS +Vout test Secondary side bias voltage TP12 SR_Drive1 Drive to FET Q1, 2 and Q3 TP13 SR_Drive2 Drive to FET Q4, 5 and Q6 TP14 IS- TP15 VINSCALED Secondary side current sense negative VIN monitoring sense on secondary side TP16 I_Pri TP17 PGND Primary side current sense transformer output on secondary side TP18 DRV_QT2_iso Q_T2 TP19 DRV_QB1_iso Q_B1 Secondary bias GND TP20 PWRGND TP21 DRV_QT1_iso Q_T1 TP22 DRV_QB2_iso Q_B2 TP23 T3-1 TP24 TP25 Transformer T3 pin 1 Not Used SW1 TP26 TP27 Input Voltage negative Switch node of Q_T1 and Q_B2 Not Used ISEC Secondary side current copper sensing after conditioning TP28 Not Used TP29 Not Used TP30 Not Used TP31 Not Used TP32 3.3VEXT TP33 PGND 3.3V_EXT Secondary bias GND TP34 Not Used TP35-43 Not Used TP44 -VO TP45 EAP2 EAP2 TP46 SYNC UCD3138 SYNC SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback -Vout test Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 11 List of Terminals 7 www.ti.com List of Terminals Table 3. UCD3138HSFBEVM-029 List of Terminals 12 TERMINAL NAME J1 VIN Input 2-pin, input voltage, 36 VDC to 72 VDC DESCRIPTION J2 Driver-A 16-pin header, DPWM to driver configuration J3 +VO 2-pin, output power positive J4 -Vo 2-pin, output power negative J5 Driver-B 12-pin header, DPWM to driver configuration J6 PMBus 10-pin PMBus connection J7 JTAG J8 UART0 P1 Bias P2 ISHARE 14-pin JTAG connection Standard UART connection, RS232, 9-pin female External bias terminal for firmware debugging without power stage on ISHARE and load current sense Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Test Procedure www.ti.com 8 Test Procedure 8.1 Efficiency Measurement Procedure WARNING Danger of electrical shock. High voltage present during the measurement. Do not leave EVM powered when unattended. Danger of heat burn from high temperature. 1. Refer to Figure 4 for basic set up to measure power conversion efficiency. The required equipment for this measurement is listed in Section 5.1. 2. Before making electrical connections, visually check the boards to make sure no shipping damage occurred. 3. In this EVM package, two EVMs are included, UCD3138HSFBEVM-029, and USB-TO-GPIO. For this measurement, the UCD3138HSFBEVM-029 board is needed. 4. Connect the DC voltage source to J1-1 (+) and J1-2 (-). Set up the DC output voltage in the range specified in Table 1, between 36 VDC and 72 VDC; set up the DC source current limit 12 A. 5. Connect an electronic load with either constant-current mode or constant-resistance mode. The load range is from 0 A to 30 A. 6. Check and make sure the jumpers are installed correctly on J2 and J5. 1. J2 should be jumped across to connect its 1-16, 2-15, 7-10, and 8-9. 2. J5 should be jumped across to connect its 1-12, 2-11, 5-8, and 6-7. WARNING Follow the connections correctly to avoid possible damages. 7. It is recommended to use the switch S1 to turn on the board output after the input voltage is applied to the board. Before applying input voltage, make sure the switch, S1, is in the “OFF” position. 8. If the load does not have a current or a power display, a current meter or low ohmic shunt and DMM is needed between the load and the board for current measurements. 9. Connect a volt-meter across the output connector and set the volt-meter scale 0 V to 15 V on its voltage, DC. 10. Turn on the DC voltage source output, flip S1 to “ON” and vary the load. Record output voltage and current measurements. 8.2 Equipment Shutdown 1. Shut down the DC voltage source. 2. Shut down the electronic load. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 13 Performance Data and Typical Characteristic Curves 9 www.ti.com Performance Data and Typical Characteristic Curves Figure 6 through Figure 14 present typical performance results for UCD3138HSFBEVM-029. 9.1 Efficiency HSFB EVM -029 Effi @12Vout, 200KHz,25C 100% 95% Effi (%) 90% 85% 80% 36Vin 75% 48Vin 75Vin 70% 0 5 10 15 20 25 30 Iout (A) Figure 6. UCD3138HSFBEVM-029 Efficiency 14 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Performance Data and Typical Characteristic Curves www.ti.com 9.2 Load Regulation HSFB EVM -029 load regulation 12.05 12.045 Vout (V) 12.04 12.035 12.03 36Vin 12.025 48Vin 75Vin 12.02 0 5 10 15 20 25 30 Iout (A) Figure 7. UCD3138HSFBEVM-029 Load Regulation 9.3 Line Regulation HSFB EVM -029 Line Regulation 12.05 12.045 Vout (V) 12.04 12.035 12.03 Iout=0A 12.025 Iout=15A Iout=30A 12.02 36 39 42 45 48 51 54 57 60 63 66 69 72 75 Vin (V) Figure 8. UCD3138HSFBEVM-029 Line Regulation SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 15 Performance Data and Typical Characteristic Curves 9.4 www.ti.com Constant Power Constant Current (CPCC) Figure 9. Constant Power Constant Current 9.5 Output Voltage Ripple Figure 10. Output Voltage Ripple at 48 VDC and Half Load, 27.2 mV 16 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Performance Data and Typical Characteristic Curves www.ti.com 9.6 Output Turn On Figure 11. Output Turn On 48 VDC with Load Range (Ch 1 = VO, Ch 3 = DPWM1B, Ch 4 = VCT, Load = 1 A) Figure 12. Output Turn On 48 VDC with 6-V Prebias SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 17 Performance Data and Typical Characteristic Curves 9.7 www.ti.com Bode Plots Figure 13. Control Loop Bode Plots at 48 VDC and Half Load Figure 14. Control Loop Bode Plots at 48 VDC and Full Load 18 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Assembly Drawing and PCB Layout www.ti.com 10 EVM Assembly Drawing and PCB Layout The following figures (Figure 15 through Figure 20) show the design of the UCD3138HSFBEVM-029 printed circuit board. PCB dimensions: L x W = 4.5 inch x 4.0 inch, PCB material: FR4 or compatible, four layers and 2-oz copper on each layer. Figure 15. UCD3138HSFBEVM-029 Top Layer Assembly Drawing (top view) Figure 16. UCD3138HSFBEVM-029 Bottom Assembly Drawing (bottom view) SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 19 EVM Assembly Drawing and PCB Layout www.ti.com Figure 17. UCD3138HSFBEVM-029 Top Copper (top view) Figure 18. UCD3138HSFBEVM-029 Internal Layer 1 (top view) 20 Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Assembly Drawing and PCB Layout www.ti.com Figure 19. UCD3138HSFBEVM-029 Internal Layer 2 (top view) Figure 20. UCD3138HSFBEVM-029 Bottom Copper (top view) SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 21 List of Materials 11 www.ti.com List of Materials Component list based on schematics of Figure 1 though Figure 3. Table 4. UCD3138HSFBEVM-029 List of Materials QTY 22 RefDes Description Part Number MFR 7 C1, C2, C3, C8, C10, C79, C82 Capacitor, ceramic, 16 V, X5R, 20%, 47 µF, 1210 STD STD 2 C11, C52 Capacitor, ceramic, 6.3 V, X7R, 10%, 2.2 µF, 0603 STD STD 0 C14, C37, C38, C76 Capacitor, ceramic, 50 V, X7R, 10%, Open, 0603 STD STD Capacitor, ceramic, 50 V, X7R, 10%, 4700 pF, 0603 STD STD 5 C19, C21, C56, C58, C59 12 C20, C23, C26, C29, C30, Capacitor, ceramic, 50 V, X7R, 10%, 0.1 µF, 0603 C31, C32, C33, C42, C44, C47, C48 STD STD 5 C22, C25, C60, C61, C64 Capacitor, ceramic, 16 V, X7R, 10%, 1 µF, 0603 STD STD 1 C28 Capacitor, ceramic, 50 V, X7R, 10%, 1 nF, 0603 STD STD 3 C34, C36, C70 Capacitor, ceramic, 50 V, NP0, 10%, 47 pF, 0603 STD STD 1 C39 Capacitor, ceramic, 50 V, X7R, 10%, 680 pF, 0603 STD STD 2 C4, C85 Capacitor, ceramic, 10 V, X5R, 10%, 10 µF, 0805 STD STD 1 C41 Capacitor, ceramic, 50 V, X7R, 10%, 330 pF, 0603 STD STD 1 C43 Capacitor, ceramic, 50 V, X7R, 10%, 220 pF, 0603 STD STD 4 C49, C66, C69, C74 Capacitor, ceramic, 50 V, NP0, 10%, 100 pF, 0603 STD STD 2 C5, C46 Capacitor, ceramic, 16 V, X7R, 10%, 2.2 µF, 0805 STD STD 1 C50 Capacitor, ceramic, 50 V, X7R, 10%, 1000 pF, 0603 STD STD 2 C53, C54 Capacitor, ceramic, 100 V, X7R, 10%, 1000 pF, 1206 STD STD 1 C57 Capacitor, ceramic, 200 V, NP0, 10%, 47 pF, 0805 STD STD 7 C6, C17, C18, C78, C83, C84, C86 Capacitor, ceramic, 16 V, X7R, 10%, 1 µF, 0805 STD STD 2 C62, C73 Capacitor, ceramic, 16 V, X7R, 10%, 100 nF, 0603 STD STD 1 C63 Capacitor, ceramic, 16 V, X7R, 10%, 4.7 µF, 0805 STD STD 1 C65 Capacitor, ceramic, 100 V, X7R, 10%, 1 µF, 1210 STD STD 2 C67, C68 Capacitor, ceramic, 50 V, NP0, 10%, 10 pF, 0603 STD STD 9 C7, C13, C15, C16, C35, C45, C71, C72, C77 Capacitor, ceramic, 50 V, X7R, 10%, 10 nF, 0603 STD STD 1 C75 Capacitor, Electrolytic, 16 V, 20%, 1000 µF, 12.5 x 20.00 mm EEU-EB1C102 Panasonic 1 C81 Capacitor, ceramic, 2000 V, X7R, 10%, 4.7 nF, 1812 STD STD 8 C9, C12, C24, C27, C40, C51, C55, C80 Capacitor, ceramic, 100 V, X7R, 10%, 2.2 µF, 1210 STD STD 2 D1, D5 Diode, fast switching, 100 V, SOT23 MMBD914LT1G Fairchild 4 D11, D15, D16, D18 Diode, Schottky, 40 V, 0.5 A, SOD-123 MBR0540T1G On Semi 2 D14, D19 LED, 565 NM, green diff, 0603 SML-LX0603GW LUMEX 1 D17 Diode, small-signal, 85 V, 200 MA, SOT23 BAW56-V-GS08 Vishay-Liteon 2 D2, D13 LED, 660 NM, super red diff, 0603 SML-LX0603SRW Lite On 2 D3, D8 Diode, Schottky, 2 A, 40 V, SMB SS24T3G ON SEMI 2 D4, D10 Diode, TVS Zener dual, 300 W, 5 V, SOT23 SM05T1G ON SEMI 1 D6 Diode, Zener, 225 MW, 5.6 V, SOT-23 BZX84C5V6-T1G ON SEMI 3 D7, D9, D12 Diode, dual switch, 100 V, SOT23 MMBD7000LT1G ON SEMI 1 F1 Fuse, 15 A, 86 VDC fast 6125FA, 15 A 86 V, 2410 TR2/6125FA15A Cooper 3 J1, J3, J4 Two position 5-mm terminal block, TB 2 x 5 mm, 0.40 x 0.35 inch ED350/2 OST Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated List of Materials www.ti.com Table 4. UCD3138HSFBEVM-029 List of Materials (continued) 1 J2 Header 16 position 2 mm, header 2 mm 16 pos PRPN062PAENRC Sullins 1 J5 Header 12 position 100 mil, header 0.1 12 pos", 0.100 inch x 2 x 6 PEC06DAAN Sullins 1 J6 Shrouded header 10 pos straight, header 100-2x5 shrouded header 100-2x5 shrouded 0.100 inch x 5 x2 N2510-6002-RB Sullins 0 J7 Connector hdr dual 14pos .100 SRT AU, open, 0.100 inch x 2 x 7 PEC07DAAN Sullins 1 J8 Connector, 9 pin D, right angle, female, 1.213 x 0.510 182-009-213R171 Norcomp 1 L1 Inductor, power, 35 A, 2.2 µH, 1.100 x 1.100 inch SER2814H-222KL Coilcraft 1 L2 Inductor, power, 16 A, 470 nH, 0.255 x 0.270 inch IHLP2525CZERR 47M01 Vishay 2 P1, P2 Conn header 3 position 0.100 vert tin, 3-pin polarized header, 0.100 inch x 3 22-27-2031 Molex 4 Q_B1, Q_B2, Q_T1, Q_T2 MOSFET, N-channel, 100 V, 60 A, 8 mΩ, QFN FDMS86101 Fairchild 6 Q1, Q2, Q3, Q4, Q5, Q6 MOSFET, N-channel, 100 V, 60 A, 8 mΩ, QFN FDMS86101 Fairchild 4 Q7, Q8, Q10, Q11 Transistor, NPN, 350 mW, 200 mA, 40 V, SOT23 MMBT3904 FAIRCHILD MOSFET, N-channel, 200 V, 3 A, S08 1 Q9 FDS2670 Fairchild 16 R1, R5, R6, R8, R18, Resistor, chip, 1/10 W, 1%, 10.0 kΩ, 0603 R19, R24, R28, R40, R62, R63, R64, R68, R96, R103, R104 STD STD 1 R101 Resistor, chip, 1/10 W, 1%, 1 Ω, 0603 STD STD 2 R14, R74 Resistor, chip, 1/3 W, 1%, 20 Ω, 1210 STD STD 2 R15, R16 Resistor, chip, 1/8 W, 1%, 15 Ω, 0805 STD STD 0 R17 Resistor, chip, 1/8 W, 1%, Open, 0805 STD STD 5 R2, R30, R52, R95, R106 Resistor, chip, 1/8 W, 1%, 10 Ω, 0805 STD STD 1 R21 Resistor, chip, 1/10 W, 1%, 6.49 kΩ, 0603 STD STD 4 R22, R46, R51, R105 Resistor, chip, 1/10 W, 0 Ω, 0603 STD STD 1 R91 Resistor, chip, 1/10 W, 3 Ω, 0603 STD STD 4 R25,R32,R76,R82 Resistor, chip, 1/10 W, 1%, 49.9 kΩ, 0603 STD STD 0 R26 Resistor, current sense , 3 W, 1%, open, 0.394 x 0.205 inch BVS-M-R001-1.0 Isotek 0 R27, R38, R39, R44, R45, Resistor, chip, 1/10 W, 1%, open, 0603 R66, R75, R78, R81, R83, R86, R88, R89, R90, R94 STD STD 1 R29 Resistor, chip, 1/10 W, 1%, 2.00 kΩ, 0603 STD STD 1 R3 Resistor, chip, 1/8 W, 1%, 200 Ω, 0805 STD STD 1 R31 Resistor, chip, 1/8 W, 1%, 1.00 kΩ, 0805 STD STD 1 R33 Resistor, chip, 1/10 W, 1%, 1.74 kΩ, 0603 STD STD 3 R34, R56, R58 Resistor, chip, 1/10 W, 1%, 3.32 kΩ, 0603 STD STD 2 R35, R85 Resistor, chip, 1/10 W, 1%, 16.2 kΩ, 0603 STD STD 1 R36 Resistor, chip, 1/10 W, 1%, 1.62 kΩ, 0603 STD STD 6 R4, R10, R11, R23, R107, Resistor, chip, 1/8 W, 1%, 1 Ω, 0805 R108 STD STD 1 R42 Resistor, chip, 1/10 W, 1%, 3.09 kΩ, 0603 STD STD 1 R47 Resistor, chip, 1/10 W, 1%, 15.0 kΩ, 0603 STD STD 2 R48, R53 Resistor, chip, 1/10 W, 1%, 22.1 kΩ, 0603 STD STD 1 R49 Resistor, chip, 1/10 W, 1%, 4.99 kΩ, 0603 STD STD 5 R50, R98, R99, R100, R102 Resistor, chip, 1/10 W, 1%, 33.2 Ω, 0603 STD STD SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter Copyright © 2013–2019, Texas Instruments Incorporated 23 List of Materials www.ti.com Table 4. UCD3138HSFBEVM-029 List of Materials (continued) 24 1 R54 Resistor, chip, 1/10 W, 1%, 1.50 kΩ, 0603 STD STD 1 R59 Resistor, chip, 1/8 W, 1%, 3.01 Ω, 0805 STD STD 1 R60 Resistor, chip, 1/8 W, 1%, 750 Ω, 0805 STD STD 1 R61 Resistor, chip, 1/10 W, 1%, 137 kΩ, 0603 STD STD 1 R65 Resistor, chip, 1/8 W, 1%, 1.65 kΩ, 0805 STD STD 1 R67 Resistor, chip, 1/10 W, 1%, 51.1 kΩ, 0603 STD STD 1 R69 Resistor, chip, 1/8 W, 1%, 90.9 kΩ, 0805 STD STD 4 R7, R13, R55, R57 Resistor, chip, 1/10 W, 1%, 499 Ω, 0603 STD STD 1 R72 Resistor, chip, 1/10 W, 1%, 10 Ω, 0603 STD STD 1 R73 Resistor, chip, 1/8 W, 0 Ω, 0805 STD STD 1 R77 Resistor, chip, 1/10 W, 1%, 0.47 Ω, 0603 STD STD 1 R79 Resistor, chip, 1/10 W, 1%, 150 kΩ, 0603 STD STD 1 R80 Resistor, chip, 1/10 W, 1%, 1.18 kΩ, 0603 STD STD 1 R84 Resistor, chip, 1/10 W, 1%, 1.82 kΩ, 0603 STD STD 1 R87 Resistor, Chip, 1/10 W, 1%, 301 Ω, 0603 STD STD 8 R9, R12, R20, R37, R41, R43, R70, R71 Resistor, chip, 1/10 W, 1%, 1.00 kΩ, 0603 STD STD 1 R92 Resistor, chip, 1/10 W, 1%, 2.49 kΩ, 0603 STD STD 1 R93 Resistor, chip, 1/10 W, 1%, 20.0 kΩ, 0603 STD STD 1 R97 Resistor, chip, 1/10 W, 1%, 220 Ω, 0603 STD STD 1 S1 Switch, on-on mini toggle, SPDT 28 V 0.4 A, 0.28 x 0.18 inch G12AP NKK 1 S2 Switch, SPST, PB momentary, sealed washable, 0.245 X 0.251 KT11P2JM34LFS C&K 1 T1 SMT 100:1 current sense XFMR, 100:01:00, 0.284 x 0.330 inch PA1005.100 Pulse 1 T2 Transformer, aux. flyback ±10%, 540 µH, 0.400 x 0.480 inch 031-00019 XFMRS Inc Power XFMR 400 W 5:2:2, 26x29.5 mm 755044 Payton 5012 Keystone 1 T3 29 TP1, TP2, TP3, TP5, TP6, Test point, white, thru hole, 5012, 0.125 x 0.125 TP7, TP8, TP9, TP10, inch TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP21, TP22, TP23, TP25, TP27, TP32, TP33, TP44, TP45, TP46 1 TP4 Adaptor, 3.5-mm probe clip (or 131-5031-00), 0.200 131-4244-00 inch Tektronix 1 U1 UCD3138RHA, Digital Power Controllers, QFN UCD3138RHA TI 1 U10 OPA344, Mic op amp RRIO, SOT23-5 OPA344NA/250 TI 1 U11 TLV2371, op amp 3 MHZ RRIO, SOT23-5 TLV2371IDBVR TI 2 U2, U9 TPS715A33, LDO reg, QFN-8 TPS715A33DRBT TI 1 U3 UCC27524, Dual HS MOSFET Driver, 5 A, HTSSOP UCC27524DGN 1 U4 SN65C3221, Line DRVR/RCVR 1 channel, TSSOP- SN65C3221PWR 16 TI 1 U5 QISO7240CF, UAD channel 25 MBPS digital isolator, SO-16 ISO7240CFDWR TI 1 U6 LM60C, temp sensor, SOT-23 LM60CIM3X TI 2 U7, U12 UCC27211, high/low-side driver, 4 A, SO8 UCC27211D TI 1 U8 UCC3813D-1, low-pwr current-mode PWM, SO8 UCC3813D-1 TI Digitally Controlled Hard-Switching Full-Bridge DC-DC Converter TI SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Appendix A SLUUA95A – April 2013 – Revised September 2019 12 Digital Full-Bridge Converter Description A.1 Converter Block Diagram GPIO1 O OF / N F GPIO 2 Memory JTAG PMBu s UAR T 3.3VS POR OSC GPIO 0 LED s SYNC ISO7240 DPW 0A (QT1 and QB1) M DPW 1A (QT2 and QB2) M SYNC CM 5 P DPW 0B (Q1) M DPW 1B (Q4) M UCC27524 I_PRI (AD04) AD06/ TEMP (U6) IOUT U10 Conditioning I_PRI +VO C COPPE R SNSING R_copper R84 R85 Q4 T3 Q1 OCP ILI M OV P CM 0 P CM 1,2 AD03/ P AD01 AD02/ ISHAR E AD00 R15 VIN Monitoring ADDR RL C O VOUT L1 R16 (VIN_CT) Secondary Bias VIN Monitor (AD01) CM 3 AD04/ P CM AD13 / 4 P DATA BUS FF VIN_SNS EAD 2 C Q 2 T Q 1 B T1 UCC27211 T2 UC 313 D 8 RS T V 3.3 D ARM 7 D PW 1 M CA P AGN D DGN 3B 3A 2B 2A 1B 1A EAD 1 C R33 COPPE SNSING R Conditioning) (U10 R35 VOUT_SNS EAD 0 C CLA0 (PID) CLA1 X DPW M DPW M DPW M DPW M DPW M DPW M DPW M DPW M 0B 0A Figure 21 shows the converter block diagram used in the EVM. The signals used for control and for detection are also defined in Figure 21 in connection to the UCD3138 pins which are listed in Section A.2 and Figure 22 as well. Q 2 B Primary Bias Q 1 T T3 VIN UCC3813 UCC 27211 Figure 21. Converter Block Diagram and Pin Definitions SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 25 UCD3138 Pin Definition A.2 www.ti.com UCD3138 Pin Definition The definition of each UCD3138 pin is defined in Figure 21. The definitions shown in Figure 22 are for these pins used in the EVM to make full-bridge converter control. It can be found in Figure 21 how the signals on these pins are used in the converter in this EVM. Front End 0 Vout Feedback EAP0 EAN0 EADC DAC0 Load EAP1 Current EAN1 Front End 1 VIN Monitor EAP2 VFF Sense Front End 2 Soft Start Control Filter 1 or 2 (Loop Nesting) CPCC Module PID Filter 0 DPWM0 PID Filter 1 DPWM1 PID Filter 2 DPWM2 Constant Power Constant Current DPWM3 DPWM0A Primary FET DPWM0B SR FET DPWM1A Primary FET DPWM1B SR FET Front End Averaging Digital Comparators Advanced Power Control Mode Switching, Burst Mode, IDE, Synchronous Rectification soft on & off ADC12 Input Voltage Feed Forward ADC12 Control Sequencing, Averaging, Digital Compare, Dual Sample and hold PMBus AD00 AD01 Internal Temperature Sensor AD02 AGND PMBus ADDR AD00 VIN Sense Optional AD01 ISHARE AD02 +VO AD03 I_PRI TEMP IOUT VREG DGND V33A UART0 ARM7TDMI-S 32 bit, 31.25 MHz A Memory PFLASH 32 kB DFLASH 2 kB RAM 4 kB ROM 4 kB AD03 B C AD04 D Fault MUX & Control E Cycle by Cycle Current Limit F Digital Comparators AD13 Power and 1.8 V Voltage Regulator Oscillator AD02 AD06 AD13 Current Share Analog, Average, Master/Slave Analog Comparators AD04 V33D V33DIO AD13 Timers 4 – 16 bit (PWM) 1 – 24 bit AD06 GPIO Control Power On Reset /RESET Brown Out Detection JTAG AD07 G AGND Figure 22. UCD3138 Pin Definition in Hard Switching Full-Bridge Control 26 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Hardware – Introduction www.ti.com A.3 EVM Hardware – Introduction This section describes the EVM hardware functions. A.3.1 Power Stage This EVM implements a traditional symmetrical hard-switching full-bridge dc-dc converter topology. The power stage circuit is shown in Figure 23. The complete schematics are shown in Figure 1 through Figure 3. The main power components on the primary side, Q_T1, Q_T2, Q_B1, and Q_B2 form the MOSFET full-bridge converter. These four FETs are controlled by the UCD3138 DPWM module 0 (DPWM0A) and module 1(DPWM1A). The controller, UCD3138, is located on the secondary side. The driver signals to these four FETs are through digital isolator U5 to transmit from the secondary side to the primary side. The synchronous rectifiers are shown on the same page and are labeled as Q1 to Q3 and Q4 to Q6. They are controlled by DPWM module 0 (DPWM0B) and DPWM module 1 (DPWM1B). Please refer to Figure 22 for DPWM module 0 and 1. The main power transformer is T3. T1 is the current transformer used to sense the primary-side current and feed into the secondary-side UCD3138 controller through AD04. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 27 EVM Hardware – Introduction www.ti.com Figure 23. Full-Bridge Converter Power Stage 28 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Hardware – Introduction www.ti.com A.3.2 Bias Power Supply The main bias supply is a flyback converter using the UCC3813 controller from Texas Instruments. The bias circuit is shown in Figure 24. In this circuit, one output (VAUXPRI) is on the primary side and two outputs (VAUXS and 6V_UR) are on the secondary side. The feedback signal is taken from VAUXPRI. The secondary-side controller needs 3.3 V, which is derived from 6V_UR by a regulator (U2) to supply UCD3138 and by a regulator (U9) to supply digital isolator (U5), external temperature sensor (U6) and UART controller (U4). On the primary side a 5V-LDO is to supply the digital isolator to transmit drive signals from the secondary side to the primary side. The three LDO associated bias circuits are shown in Figure 25. Figure 24. Main Bias Circuit and Input Voltage Optional Monitoring Figure 25. LDO Bias Circuits SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 29 EVM Hardware – Introduction A.3.3 www.ti.com Input Voltage Sensing Using Bias Transformer As the controller is located on the secondary side, special approaches are required to obtain the input voltage information from the primary side for control needs. One approach is to use the main bias power supply transformer winding. As shown in Figure 24, a sample-and-hold circuit is on the secondary side to sense the primary voltage. When switch Q9 turns on, D3 turns on by the negative voltage from divider R31 and R76. The voltage on the winding (6, 7) of bias transformer T2 charges capacitor (C71) to a negative voltage equal to VIN/N times the attenuator ratio of R31 and R76, (N is turns ratio of T2). When Q9 is turned off, D3 is turned off, and the voltage on C71 is held until next switching period. The voltage on C71 is proportional to the input voltage. U11 is used to invert the input negative voltage to positive output voltage scaled by R93 and R79. This input voltage monitoring approach is an optional for potential applications while not enabled in the EVM firmware. A.3.4 Input Voltage Sensing Using Main Transformer The sensing approach described in Section Section A.3.3 is good to use in steady-state but not capable of fast transient sensing. This approach presents slow detection and slow response. Its advantage is less noise sensitive. To improve input voltage sensing speed in real time, the main power transformer can be used. As shown in Figure 26, the approach takes the input voltage signal (VIN_CT) from the center tap of the main transformer secondary side windings, then scaling the signal to feed into UCD3138 EADC02. This EVM uses this sense structure when the converter is in startup, in steady-state, as well as in input voltage feed forward control. Particularly when use this structure for converter startup, the approach is called singleframe input voltage sensing. Single-frame here means one switching cycle. More details on how the main transformer is used to make input voltage sense can be found in Section A.3.5. Figure 26. Input Voltage Sensing Using Main Transformer 30 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Hardware – Introduction www.ti.com A.3.5 Load Current Sensing by PCB Copper To utilize the board area, this EVM uses copper trace (R26) to sense the output load current. The copper sensing related circuit is shown in Figure 27. R41 and R43 are installed to feed the sensing signal to the current amplifier U10. With a low pass filter (C7, R54 and R20), the output voltage of the amplifier is of DC voltage in nature. The signal is then fed to AD13 of the controller. The amplifier gain can be set to 137 by choosing R41 =R43 =1k, R61 =137k. AD13 is used to sense the load current , then the processor utilize the information for many applications, such as reporting the current to the host, calculating output power, implementing current sharing and over current protection. The accuracy of sensing current with a copper trace is usually poor because the resistance of copper trace depends not only on the base copper thickness and plating, but also on the temperature of the copper. The base copper has a temperature coefficient of about 4000 PPM per degree °C. Fortunately, the resistance can be measured and stored during manufacturing, and the temperature of the copper trace can be measured to compensate for temperature drift. The temperature of the copper trace is measured by a temperature sensor U11 (LM60C) then feed into UCD3138 through AD06. Please refer to Section A.6.7 for temperature sensing. Figure 27. Load Current Sensing by PCB Copper SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 31 EVM Hardware – Introduction A.3.6 www.ti.com Load Current Sharing UCD3138 supports three major current sharing techniques: 1. Average current sharing, or pwm bus current sharing. 2. Master/slave current sharing. 3. Droop mode current sharing, or analog bus current sharing. This EVM uses the average current sharing. If interested in the other two sharing techniques, please contact TI for further assistance. The average current sharing technique uses a share bus to balance and evenly distribute current on each paralleled converter. The share bus is called ISHARE in this EVM design. Hence, when making load current sharing, ISHARE from each board requires connecting together. ISHARE connection is located on P2 terminal pin 3 on the EVM board. Figure 28 shows the load sharing module inside UCD3138. When enable the average current sharing, SW1 turns on. The ISHARE bus is on AD02 output which generates a voltage corresponding to the load current of that board. As all boards in share connected together by each of their own ISHARE, the voltage on EXT CAP (C19) is an averaged value representing a targeted sharing value for each converter output current. AD13, is used to measure the load current of each board in voltage, then compare to the voltage on ISHARE to adjust one’s own output current level to match the targeted ISHARE value by DPWM duty cycle control. Figure 28. UCD3138 Load Sharing Module 32 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Hardware – Introduction www.ti.com A.3.7 Serial Port Interface The schematic of the interface for the serial port (UART) is shown in Figure 29. The UART is able to provide real time debug and subsequently reduce code development time. It can also be used as a monitor for fast changing internal variables. The UART is not enabled in delivered EVM boards. Please contact TI to find how to enable this function. Figure 29. Serial Port Interface in the Converter A.3.8 LED Indicators Table 5. LED Status Lights REF DES SILK SCREEN TEXT D14 D13 FUNCTION This light is on in green when 3.3VD is present on UCD3138. VIN_OK This light is on in red when input voltage ok. D2 FAILURE This light is on in red when latch-off fault(s) present, currently OVP only. D19 P_GOOD This light is on in green when the output voltage is within the thresholds defined by PMBUS_CMD_POWER_GOOD_ON and PMBUS_CMD_POWER_GOOD_OFF SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 33 EVM Firmware – Introduction A.4 www.ti.com EVM Firmware – Introduction The reference firmware provided along with the EVM is only intended to demonstrate basic HSFB converter control functionality as well as basic PMBus communication. The firmware can be used as an initial platform for particular applications. A brief introduction to the firmware is provided in this section. A.4.1 Firmware Infrastructure Overview The firmware includes one startup routine and three program threads. The startup routine is to make initialization to set up the controller to the targeted operation functions or status. Please contact TI to obtain the detailed initialization information. The three program threads are (a) the Fast Interrupt (FIQ); (b) the Standard Interrupt (IRQ); and (c) the Background Loop, as shown in Figure 30. • Fast Interrupt (FIQ): Critical or time sensitive tasks are within the FIQ. Functionally, FIQ events are the highest priority and are addressed as soon as possible. It occurs every four switching cycles, set by DPWM interrupt. • Standard Interrupt (IRQ): The majority of the firmware tasks occur during the IRQ. IRQ events occur synchronously every 100 µs set by timer. • Background Loop: Non time sensitive tasks are implemented in background loop. Background Loop items are addressed whenever FIQ and IRQ events are not handled. FIQ FIQ Complete 4 Switching Cycle FIQ Complete 4 Switching Cycle 100µs Timer Background Loop IRQ IRQ Complete Figure 30. Firmware Structure Overview 34 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated EVM Firmware – Introduction www.ti.com A.4.2 Tasks within FIQ The FIQ events are with the highest priority and are addressed as soon as possible. Critical or time sensitive tasks are in the FIQ. In the firmware uploaded into the EVM, the function called by the FIQ is constant power and constant current function. There are two control loops in the EVM. Voltage loop for VOUT regulation; and current loop for constant current protection. Front end 0 and filter 0 are for the voltage loop, front end 1 and filter 1 are for the current loop. In FIQ, the filter output of the two loops is compared. The loop takes control of the power stage is decided base on the larger output of the two filter-outputs. The FIQ gets called to response every four-switching cycles. PSON ON Monitoring Vin Idle PSON OF F No F aults & PSON Vout prebias calculation Po wer off fo r 1s Wait fo r PSON T og g le No F au lts OCP, OTP Hiccup Ramp up OVP Latch Ram p up Vo u t com p lete Vin Un der Vo ltag e OCP, OTP OVP SYNFET Ramp up OVP OC P, OTP OC P, OTP Ram p up Over OVP Feedforward Enable FF In itializatio n Do ne Regulated Figure 31. State Machine SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 35 EVM Firmware – Introduction A.4.3 www.ti.com Tasks within IRQ State Machine Almost all firmware tasks occur during the IRQ. The only exceptions are the serial interface and PMBus tasks, which occur in the background loop; and the over current protection (OCP), which is handled by the FIQ. The IRQ is called to response every 100 µs. At the heart of the IRQ function is the power supply state machine implemented with “switch” command. The state machine has its structure as shown in Figure 31. At a higher level, this state machine allows the digital controller to optimize the performance of the power supply, based on exactly what it is doing. A.4.4 Tasks within Background Loop The background loop handles all PMBus communication as well as process and transmit data through the UART. The data flash is managed with a dual-bank approach. This provides redundancy in the event of a power interruption during the programming of data flash. Once new data flash values have been written, a function called erase_task() is initiated in the background loop to erase the old values. The erase_task() continues to get called until all of the old DFLASH segments are erased. Erasing the data flash in segments allows the processor in the controller to handle other tasks instead of waiting for the entire data flash to be erased before doing anything else. 36 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Normal Operation www.ti.com A.5 System Normal Operation The EVM is designed to operate in PWM hard switching mode in normal operation conditions. At very light load condition, if needed, the burst operation can be enabled for EVM operation. Please contact TI to find how to enable this function. On the other end of the operation, if the load power keeps increasing beyond the rated value, then an over load condition occurs. In such a case, the system enters protection operation, first entering constant power constant current mode, then if load power still keeps increasing, this triggers cycle-by-cycle current limit. Please refer to Section A.6 to learn more about these protection functions. The converter of this EVM is designed to work in the following manner. • When VIN reaches above 22 V, the auxiliary power supply turns on. The UCD3138 starts and uses the single-frame approach to check if VIN reaches 36 V if S1 is on. If VIN reaches 36 V or above, operation starts. • The converter is in normal operation to regulate the output voltage at 12 V nominally. As shown in Figure 32, Ch1 = TP13, Ch2 = TP25, Ch3 = TP23, and Ch4 = TP12, all referenced to the primary-side ground. • When the load current reaches such a level to have full power as specified in a pre-determined constant power setting, say 360 W, the output voltage to be regulated reduced, the higher the load current, the lower the output voltage regulation point, in this way, the constant power operation is achieved. • The converter is controlled to keep operating in constant power mode until the load current reaches a pre-determined level, say 36 A, then the operation enters the constant current mode. In this mode, frond end 1 and filter 1 takes control of the power stage and maintains the output current at the setting point 36A. If the controller sees a large current on the primary side, say over 14 A, hardware cycle-bycycle current limit function becomes active. • Further increase load current shifts the primary-side current peak value higher. When the peak values reaches a pre-determined level, the operation is in short circuit protection mode. Figure 32. Normal Operation Switching Waveforms SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 37 System Normal Operation A.5.1 www.ti.com Start-Up with Single-Frame Input Voltage Sensing Before start up, the EVM uses a different way to sense the primary side voltage. It is called single-frame VIN sensing. In idle mode, two sets of single DPWM frames with 800 ns width are sent, EADC2 are used to catch the second pulse from secondary and input voltage is determined. The sensing point can be programmed to get the best noise performance. The single-frame VIN sensing scheme is illustrated in Figure 33. Figure 34 shows test waveforms, where the green and the blue are two primary DPWM; the orange is VIN_SNS feed to EADC2. The purple is the transformer CT. Single frame mode Start up DPWM0A Primary DPWM1A DPWM0B Secondary DPWM1B EADC sampling Transformer CT Td Vout 0V Figure 33. Input Voltage Sensing Using EADC2 Figure 34. Single-Frame Approach Test In normal operation control, the sensing hardware connection also serves the input voltage feed forward control, refer to Section A.5.2. A.5.2 Prebias Load and Load Synchronous Startup When start a converter into pre-biased load condition, or start with two or more converters in parallel, special techniques are required since even a small difference from each output voltage may cause reverse current flow. The special technique, called synchronous startup, is used to enhance the parallel startup performance of UCD3138 controlled converters. This technique uses a GPIO pin as sync-pin which connects each board together to start at the same time then the output voltage difference from different converter is minimized. 38 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Normal Operation www.ti.com A.5.3 Current Sharing Operation To make two boards in current sharing operation, P2 pin 3 of each board is required to connect together as shown in Figure 35. P2 pin 3 serves as an “ISAHRE” connection, refer to Section A.3.6. Figure 36 provides a test result, the yellow is output voltage, the other two channels are output currents from two paralleled EVM boards. The test was made with total load current change from 3 A to 60 A. The current sharing ratio in steady state at 60-A load is nearly perfect, that is as close to 50%-50%. In the transient, the sharing difference is about 9.8 A with settle down time about 560 µs. With the 95% load step change, the VO overshoot and undershoot is about 0.4 V on 12 V, or about 3.5% The current sharing operation is made possible in the steady-state. To share the load current in soft start time, it is recommended to use Synchronous Startup technique as described in Section A.5.2. With this technique, the load current can still be shared to some degree since CPCC allows completing the soft start without shut down even if one converter in slight over load condition. Please contact TI to find how to set up synchronous startup. Ishare Bus ISHARE 1 ISHARE 2 AD02 AD02 PS1 PS2 Iout2 Iout1 AD13 AD13 Figure 35. Current Sharing Operation Figure 36. Current Sharing Test SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 39 System Normal Operation A.5.4 www.ti.com Input Voltage Feed Forward Control The input voltage feed forward control employed in the power converter control is to help to maintain output voltage regulation during input voltage high transient time. This technique can adjust the needed final duty cycle right with the input voltage change without go through normal feedback loop which usually has much longer timer delay in order to correct the output voltage error from input voltage transient. By ignoring the various losses, assuming output voltage 12 V and unity transformer turns ratio, and assuming the converter secondary-side in CCM (as SR is in place), the relationship between input and output in a DC-DC forward type of converter, can be described by the duty cycle, V d = OUT VIN (1) Plot this equation, the relationship between input and output can be shown with the red curve in Figure 37. Figure 37. Duty Cycle Change in Feed Forward Control In digital control, the duty cycle shown in the red-curve can be represented by a piecewise-linear approximation overlaid in the blue-curve. UCD3138 implements the blue-curve approximation with a nonliner multiplier as shown Figure 38 which shows the control functions implemented in UCD3138. In normal operation without input voltage transient, CLA2 output is unity. The DPWM is solely controlled by CLA1. When input voltage is in transient, CLA2 generates a multiplier based on input voltage change level which can be pre-programmed. Figure 38. UCD3138 Digital Feed-Forward Control 40 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Normal Operation www.ti.com On the control used in this EVM, the input voltage sense value is compared with VREF2, their difference, Vth, will set up the multiplier from CLA2 to CLA1 as below. • If -Vth1 < Vth < Vth1, CLA2 = Gain0, or KP0 • If -Vth2 < Vth < –Vth1, or, Vth1 < Vth < Vth2, CLA2 = Gain1, or KP1 • If -Vth2 > Vth or Vth2 < Vth, CLA2 = Gain2, or KP2 The above can be expressed as, ( Gain = K C + KP ´ VDAC - Vin _ sense ) (2) In steady-state, Gain0 = KC, where KC can be described as a unity number although in practice it may be designed differently to match other scaled values. During the input voltage transient, nonlinear gain is generated to achieve desired duty cycle by feed forward control approximation. As the control algorithm is of symmetrical characteristics from ±Vth1 and ±Vth2, an equilibrium point is required to be established. From practice such as in 48-V telecom application, this point may be initially selected at VIN0 = 48 V. During the operation with different input voltage, a new equilibrium point will be re-established corresponding to that input voltage. In this EVM design, Vin_sense signal is from VIN_CT as shown in Figure 26 and its relationship to VIN is expressed as, Vin_sense = (VIN/N) x R29 / (R25 + R29) = k x VIN, where k = 0.0154, and N is the turns ratio of transformer T3. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 41 System Normal Operation A.5.5 www.ti.com Feed Forward Function Test Load = 1 A, VIN from 40 V to 58 V, VIN slew rate 20 V/us, VO maximum shift 0.68 V, recovery time 50 µs. In Figure 39, the purple is VOUT and the yellow is VIN. In Figure 40, the green is primary side DPWM and the yellow is VIN. Figure 39. VO Change from Digital Feed Forward Control Figure 40. Duty Cycle Change from Digital Feed Forward Control 42 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Normal Operation www.ti.com A.5.6 Light Load Operation At light load, the burst operation can be enabled when the switching duty cycle is small. The significant benefit from this operation is the reduction of the power losses. The associated disadvantage is of higher output voltage ripple in steady-state and of larger output voltage dip in load demanding transient. But the higher ripple and the larger dip can be solved especially with digital control of its convenience and flexibility. For example, non-linear control from digital control can solve the large dip during load transient. The higher ripple can also be reduced by narrowed duty cycle on/off limit for burst operation control. Figure 41 shows the burst operation timing diagram with UCD3138. When the controller detected light load condition, the operation is enabled into Light Load Enable (LLE) by firmware. When load condition is changed to heavy, CLA can generate a large gain to adapt the load change and minimize the output voltage drop although the operation is still in LLE mode. If the load keeps heavy for certain time, light load will be terminated by the firmware. The burst operation mode is disabled in the EVM. Please contact TI to know how to enable this feature. Figure 41. Burst Operation Timing Diagram SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 43 System Operation in Protection A.6 A.6.1 www.ti.com System Operation in Protection Faults and Warnings The system comes equipped with a variety of programmable fault and warning options. In section 12.3.8, Table 5 lists the LEDs used to indicate a fault. Table 6 below shows the basic faults and warnings available in the EVM along with the corresponding action taken by these events. Each of these parameters can be modified through the GUI. Table 6. Faults and Warnings SIGNAL TYPE WARNING VOUT Over Report Report & Latch off Under Report Report Over Report Report & Latch off VIN FAULT RESPONSE Under Report Report & Latch off IOUT Over Report Report & Latch off IIN Over Report Cycle by cycle limiting Temperature Over Report Report and Latch off The GUI reporting includes appropriate setting of the PMBus alert line, status byte and status word. Faults and warnings can be reset by toggling the unit off and then on. Alternatively, as long as the system does not latch off, the “Clear Faults” button can also be used to clear any faults or warnings. Refer to Figure 42 which is from the Designer GUI Monitor tab. More details can be found in Section A.8. Figure 42. Faults and Warnings 44 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Operation in Protection www.ti.com A.6.2 Constant Power Constant Current Operation Both hardware and firmware in this EVM supports Constant Power Constant Current, or CPCC operation. Figure 43 illustrates the behavior of the output voltage and output current (V¬OUT vs. IOUT). However, the EVM comes pre-programmed with a constant power threshold of 360 W and a constant current threshold of 36 A. Some of the limits are adjustable through the GUI and new setting can be saved to data flash. The maximum hardware capability is to limit the current within 36 A. Figure 44 shows the GUI interface to these controls with the default values. The CPCC can be enabled or disabled through GUI. Details can be found in Section A.4.2. After the output power reaches the set point, VOUT starts to drop while the power keeps the same which means the current may increase. The power stage stays on and it will not enter latch mode. When the current loop filter output (Front End 1 and Filter 1) is larger than the voltage loop filter output (Front End 0 and Filter 0), the current loop takes control of the power stage and output voltage starts in hiccup operation state. In hiccup state, the power stage stays on for 1s, and then goes to idle state and try to turn on again. If the load is reduced, the power stage will go to regulated state. If the load current is still high, the output voltage goes to hiccup state again. Only OVP will take the power stage to latch-off state. OTP, OCP, and constant current will take the power state to hiccup state. In hiccup state, the power state turns on automatically. In latch state, toggle off the PSON switch is needed or recycle the input power. CPCC @Vin=48V 14 12 Vout (V) 10 8 w Fan w/o Fan 6 4 2 0 0 5 10 15 20 25 30 35 40 Iout (A) Figure 43. Constant Power Constatnt Current Operation Figure 44. CPCC Default Values and Adjustable through GUI SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 45 System Operation in Protection A.6.3 www.ti.com Cycle-By-Cycle Current Limit Cycle-by-cycle current limit is made to the primary-side input current. The current is sensed by current transformer T1. The sensing circuit is shown in Figure 45; also refer to full schematics of Figure 1 and power stage Figure 23. The current signal is fed into AD04 and compared to a programmable threshold on a cycle-by-cycle basis. Whenever this current exceeds the threshold the active DPWM waveforms are truncated. The cycle-by-cycle current limit is mainly used to the primary current to limit its peak within predetermined value, default as 16 A. As AD04 is a simple voltage comparator, external current slope compensation circuit may be needed in order to minimize the sub-harmonics normally existing in peak current mode control including cycle-bycycle current limit. An example circuit is shown in Figure 46. More detail on this circuit can be found in “Modeling, Analysis and Compensation of the Current-Mode Converter”, (TI Literature Number SLUA101). In case the peak current mode control is employed in an application, the peak current mode control should be made through Front End 2 (EADC2) instead of using AD04. Frond End 2 has build-in current slope compensation (RAMP) as shown in Figure 47 which does not require external slope compensation. UCD3138 can balance two pulses in a switching cycle with the same width. In UCD3138RHA, this feature exists in the DPWM module on its two outputs, for example between DPWM0A and 0B, but not available on the interconnection matrix. Then this EVM is not able to balance the pulse width in a switching cycle. If this feature is preferred, please contact TI for technical assistance. Figure 45. Cycle-by-Cycle Current Limit Sensing Circuit Figure 46. An Example of External Slope Compensation 46 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated System Operation in Protection www.ti.com Figure 47. Peak Current Mode Control with Front End 2 SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 47 System Operation in Protection A.6.4 www.ti.com Short Circuit Protection Load short circuit protection is mainly based on the secondary-side current sensing when the load current is beyond a 36 A by default. In short circuit protection the output voltage is in hiccup state. Figure 48 shows a test results with the conditions: short circuit test at 30-A load, VOUT (Ch1), IPRI (Ch 2), and VIN (Ch 3). Figure 48. Short Circuit Protection Test A.6.5 Output Over Voltage Output over voltage detection and protection is through AD03, refer to Figure 1 and Figure 23. When output over voltage is detected, the switching pulses will be disabled and the board will be in latch-off until recycle the input power or toggle the switch S1. A.6.6 Input Over Voltage The input over voltage is detected based on the main power transformer winding as described in Section A.3.4. Currently in the EVM delivered, input voltage is detected and the firmware provides warning to the Designer GUI. Please contact TI if need OVP protection. A.6.7 Over Temperature Over temperature includes UCD3138 internal temperature sensing and external added temperature sensing. The external over temperature condition is determined by a temperature sensing element on U13, LM60C. The temperature signal is fed into the controller through AD06. U13 is located on board top side next to the current sensing copper. Then it is sensing the temperature of secondary-side board temperature. In addition to the over temperature protection, this temperature information is used to compensate the copper current sensing. Figure 49. Temperature Detection Circuit 48 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Loop Compensation Using PID Control www.ti.com A.7 Loop Compensation Using PID Control PID control is usually used in the feedback loop compensation in digitally controlled power converters. We will describe several aspects how to use PID control. A.7.1 Digital PID Coefficients Transfermation to Poles and Zeros in s-Domain PID control in UCD3138 CLA for control loop is formed in the following equation in z-domain: Gc (z) = KP + KI 1 + z -1 1 - z -1 + KD 1 - z -1 1 - a´ z -1 (3) If Equation 3 is converted to the s-domain equivalent using the bilinear transform, the result has two forms. One is with two real zeros and one real pole: æ s öæ s ö + 1÷ ç + 1÷ ç wz1 ø è wz2 ø Gcz (s) = K 0 è æ s ö sç + 1÷ ç wp1 ÷ è ø (4) K0 is the gain of the frequency domain pole at origin, and K0 is also represented as the angular frequency when the integrator Bode plot gain crosses over with 0-dB. By the way, K0 can be used as a method for initially designing the feedback loop compensation, refer to for more details. The second way is when the two zeros are possibly presented with complex conjugates and in such a case, æ s2 ö s ç + + 1÷ ç w2 Q ´ wr ÷ r ø Gcz (s) = K 0 è æ s ö sç + 1÷ ç wp1 ÷ è ø (5) Two complex conjugate zeros are expressed as, wr æ ö 2 wz1, z2 = ç 1 ± j 4 ´ Q - 1 ÷ and j = -1 2´Q è ø (6) wr = wz1 ´ wz2 Q= (7) wz1 ´ wz2 wz1 + wz2 (8) The factor of Q is in the range of 0 to infinite. The two complex conjugate zeros become the two real zeros when Q is not greater than 0.5. Q £ 0.5 (9) SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 49 Loop Compensation Using PID Control www.ti.com Hence, Equation 4 is actually a special form of Equation 5. In this sense, Equation 5 can be used in either case across the range of Q. A low pass filter usually exists in a control loop of its feedback path. The low pass filter adds a pole to the loop, 1 Hcs (s) = K cs s +1 wpcs (10) The close loop transfer function is then shown as below: GM (s) ´ GPID (s) Gcs (s) = 1 + GM (s) ´ GPID (s) ´ Hcs (s) (11) where GM(s) is the control plant transfer function. For example, GM(s) can be the transfer function associated to the modulator in an HSFB converter. The parameters can be calculated with the assumption of sensor sampling cycle TS much smaller than the corresponding time constant of the voltage loop bandwidth, TC. A rule of thumb is to choose the sampling frequency to meet Ts £ 0.05 ´ TC (12) When the above assumption is true, the delay effect from the sampling (usually with zero order hold or ZOH) can be ignored and the parameters can be determined after we know where the poles and zeros should be positioned. Table 7 summarizes the poles and zeros in a form to relate z-domain to s-domain. KP = ( K 0 ´ wp1 ´ wz1 + wp1 ´ wz2 - wz1 ´ wz2 wp1 ´ wz1 ´ wz2 ) (13) K ´ Ts KI = 0 2 KD = a= (14) ( )( ) wp1 ´ wz1 ´ wz2 (Ts ´ wp1 + 2 ) 2 ´ K 0 ´ wp1 - wz1 ´ wp1 - wz2 (15) 2 - Ts ´ wp1 2 + Ts ´ wp1 (16) Table 7. Poles and Zeros from PID Coefficients System Name Complex Zeros (K0, fZ, QZ, fP) Transfer Functions s 2 2 (2 ´ p ´ fz ) + s +1 2 ´ p ´ fz ´ Qz æ ö s s ´ç + 1÷ ÷ 2 ´ p ´ K 0 çè 2 ´ p ´ fp ø 50 Real Zeros (K0, fZ1, fZ2, fP) æ ö æ ö s s + 1÷ ´ ç + 1÷ ç 2 f 2 f ´ p ´ ´ p ´ z1 z2 è ø è ø æ ö s s ´ç + 1÷ ç ÷ 2 ´ p ´ K 0 è 2 ´ p ´ fp ø Device PID (Kp, Ki, KD, α) æ ö 1 + z -1 1 - z -1 1 1000 ´ ç K p + K i ´ + Kd ´ ÷ ´ 2-SC ´ KCOMP ´ 2-19 ´ ç 1 - z -1 1 - a ´ 2-8 ´ z -1 ø÷ 24 ´ (PRD + 1) è 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Loop Compensation Using PID Control www.ti.com A.7.2 Tuning PID Coefficients for Loop Compensation When making fine-tune adjustments to the feedback control loop, one would like to know each parameter in PID how to affect the control loop characteristics without going through complicated description of the above equations. Table 8 below helps this and visually shown in Figure 50. Table 8. Tuning PID Coefficients CONTROL PARAMETERS KP IMPACT ON BODE PLOT Increasing KP Pushes up the minimum gain between the two zeros. Moves the two zeros apart. KI Increasing KI Pushes up integration curve at low frequencies. Gives a higher low-frequency gain. Moves the first zero to the right. KD Increasing KD Shifts the second zero left. Doesn’t impact the second pole. α Increasing α Shifts the second pole to the right. Shifts the second zero to the right. TS = 1 / fS Increasing the sampling frequency fS : Causes the whole Bode plot to shift to right. Figure 50. Tuning PID Parameters A.7.3 Measuring the Control Loop The control loop measurement can be made by injecting frequency sweep signal across R16. The connections can take advantage of P2 pin 1 and TP10. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 51 Evaluating the EVM with GUI A.8 www.ti.com Evaluating the EVM with GUI Collectively, the GUI is called Texas Instruments Fusion Digital Power Designer. The GUI serves the interface for several families of TI digital control IC’s including the family of UCD31xx, that is the UCD3138 as its one member. The GUI can be divided into two main categories, Designer GUI and Device GUI. In the family of UCD31xx, each EVM is related to a particular Designer GUI to allow users to re-tune/reconfigure a particular EVM in that regarding with existing hardware and firmware. Device GUI is related to a particular device to access its internal registers and memory cells. UCD3138HSFBEVM-029 is a standalone board where UCD3138RGH 40-pin device is placed. The firmware to control this converter is downloaded into this board through Device GUI. How to install the GUI is described in the user’s guide “Using the UCD3138CC64EVM-030 (TI Lit#, SLUU886)”. The designer GUI is installed at the same time when installing the Device GUI. A.8.1 Graphical User Interface (GUI) As mentioned above, there are two types of graphical user interfaces (GUI), one is Device GUI, and the other is Designer GUI. The Device GUI is sometimes called low level GUI. From the Device GUI, device’s registers are accessed if the device is in the ROM mode and the PMBus communication is established. This GUI should be used to download the code when the device is blank at the first programming. Also, at the flash mode, a customer can send PMBus commands to read or write the data. The Designer GUI is an interface between a host and a user’s board. It supports some of PMBus commands for configuration, monitoring and design such as loop compensator built in the UCD3138 digital controller. 52 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com A.8.1.1 Hardware Setup The board hardware connection is overall the same as shown in Section 5.2 and Figure 4 while shown in Figure 51 again. The addition to the setup is to connect USB-to-GPIO to the board. The ribbon cable connects to J6 and the USB cabled connects to a host PC computer. The remaining connections are described again in the below. USB-to-GPIO J6 1 2 12 11 1 2 D19 16 15 S2 S1 J2 J5 5 6 UART0 (J8) 8 7 7 8 10 9 Reset 1 D14 J3 + TP10 - VIN + TP2 J4 J1 - Load TP44 TP1 Forced Air Flow Direction 400LFM Figure 51. Test Setup SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 53 Evaluating the EVM with GUI • • • • • • www.ti.com Refer to Figure 51 for basic hardware connections. The required equipment is listed in Section 5.1. Before making electrical connections, visually check the boards to make sure no shipping damage occurred. Connect the DC voltage source to J1-1 (+) and J1-2 (-). Set up the DC output voltage in the range specified in Table 1, between 36 VDC and 72 VDC; set up the DC source current limit 12 A. Connect an electronic load with either constant current mode or constant resistance mode. The load range is from zero to 30 A. Connect USB-to-GPIO ribbon cable to J6 and connect USB-to-GPIO USB cable to a host PC computer. Check and make sure the jumpers are installed correctly on J2 and J5. – J2 should be jumped across to connect its 1-16, 2-15, 7-10, and 8-9. – J5 should be jumped across to connect its 1-12, 2-11, 5-8, and 6-7. WARNING Follow the connections correctly to avoid possible damages • • • 54 It is recommended to use the switch S1 to turn on the board output after the input voltage is applied to the board. Before applying input voltage, make sure the switch, S1, is in the “OFF” position. If the load does not have a current or a power display, a current meter or low ohmic shunt and DMM will be needed between the load and the board for current measurements. Connect a volt-meter across the output connector and set the volt-meter scale 0 V to 15 V on its voltage, DC. 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com A.8.1.2 GUI Installation GUI software can be downloaded from the TI website, www.ti.com. The software should be installed in the host PC before it is executed. More details about the TI GUI, which is called TI Fusion Digital Power Designer (DFPD), can be found in its user’s guide/manual. Please contact TI to get this user’s guide/manual. After the GUI installation, the Guide can be found in the Designer GUI of its real time “Help”. “Help” > “Documentation & Help Center” > “UCD3138” Copy the TI Fusion Digital Power Designer zip file and unzip the file TI-Fusion-Digital-Power-Designerxx.zip to get installer TI-Fusion-Digital-Power-Designer-xxx.exe. The xxx in the file name refers to the GUI release version. Double click the installer TI-Fusion-Digital-Power-Designer-xxx.exe and follow the straight forward instructions to finish the installation. Normally, you need accept all the installation defaults. In order to get all GUI functions, all boxes under Select Additional Tasks should be checked, shown in Figure 52. Figure 52. GUI Installation After the installation, a quick launch button is created next to the start menu which contains shortcuts to commonly used applications. Figure 53 shows the icon of TI DFPD after the installation. Some other icons such as UCD3K Device GUI are also displayed on the desktop. For more information on the GUI installation, one can refer to UCD3138CC64EVM-030 user’s guide. Figure 53. GUI Shortcut Location SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 55 Evaluating the EVM with GUI A.8.1.3 www.ti.com USB-to-GPIO Adaptor Connection CAUTION Shut off DC power source before connection to avoid electrical shock! Connect one end of the ribbon cable to the module, and connect the other end to the USB-to-GPIO (HPA172) interface adapter. Connect the Mini connector of the USB cable to the USB interface adapter, and connect the other end to the USB port of the host computer. A.8.1.4 Launch the Designer GUI Click the Quick Launch Shortcut icon located next to the start menu. The GUI starts to look for the attached device attached to the PMBus. If the device is found and the communication is established successfully, one should see a screen that looks similar to Figure 54. In the following we will describe how to use the GUI to evaluate the module. Figure 54. Designer GUI Overview 56 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com A.8.1.5 Designer GUI Overview The Designer GUI has four tabs, as shown in Figure 54, namely, Configure, Design, Monitor, and Status. After launch the GUI, its default tab is Monitor. To go to the other three tabs, simply click the tab you would like to go. In the GUI used with this EVM, Configure is used to configure the EVM settings through PMBus commands. Design is mainly used to make tuning control loop parameters and to set up the FeedForward control non-linear gains. Monitor is used to monitor the board operation. Status is mainly used to show fault and/or warnings. A.8.2 Operation Monitoring After the designer GUI launched, the Monitor tab is presented by default as shown in Figure 54. This tab provides a quick overview of operation status with some settings changeable as well. This tab also provides oscilloscope type of plot view in real time operation. The number of scope windows can be adjusted by check or un-check upper left square boxes to show or to hide these scope plot windows. Figure 55. Designer GUI Status SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 57 Evaluating the EVM with GUI A.8.3 www.ti.com Operation Status After click the Status tab as shown in Figure 54, the EVM operation status is shown as in Figure 55. All grayed entries are candidates that can be implemented. Those in black are showing current operation status which helps to indicate potential operation issues with warning or fault indications. If a fault occurred, the corresponding entry is highlighted in red. Warnings are not a fault while may remind the user that those might need attention. A.8.4 Configuring EVM Configure tab can help to adjust the EVM feature setup conveniently without directly accessing the firmware code. Also, it helps to navigate through the various features of the converter through the GUI. Figure 56. GUI Supported PMBus Commands 58 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com A.8.4.1 GUI Supported PMBus Commands Figure 56 displays the various GUI based PMBus commands supported by the current version of the firmware. Adding additional standard commands is easy to do with the built in “Isolated Bit Mask” generator. This tool creates a coded index that the GUI reads from the device to determine what PMBus commands are supported. To add a standard command simply modify the bit mask and the GUI will automatically display the new command. Please contact Texas Instruments for details on the use of this tool. A.8.4.2 Configuring EVM with GUI In the Configure tab, change configuration is made simple. For example, to configure CPCC, the CPCC control can be accessed by clicking the drop down arrow next to the Value/Edit box on the CPCC[MFR 36] line as shown in Figure 57. As we mentioned before, maximum current 36A and maximum power 360 W. Please consult Texas Instruments if there is any uncertainty to be resolved. Figure 57. Configure CPCC As one more example, in the following, we will describe how to configure the dead time. Configuring other functions is made in the similar way. Again, please consult Texas Instruments if there is any uncertainty to be resolved before making your configuration. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 59 Evaluating the EVM with GUI A.8.4.3 www.ti.com Configuring Dead Time Click the drop down arrow next to the Value/Edit box on the DEADBAND_CONFIG [MFR 26] line, a dialogue box of Figure 58 is present to allow configuring the dead time. Figure 58. Configuring Dead Time 60 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com A.8.5 Tuning Control Loop Using GUI Design A.8.5.1 Options to Program Digital Control Loop The GUI comes equipped with 3 different ways to program the UCD3138 digital control loop compensator. Table 9 lists the three options, (a) using K0, fZ, QZ, and fP; (b) using K0, fZ1, fZ2, and fP; (c) using KP, Ki, Kd, and α. In option (c), the compensator is described by Device PID. In this context, Kp, Ki, Kd and α are the raw register values used to configure the positions of the poles and zeros of the compensator. SC is a gain scaling term. Although it is normally set to zero it provides additional gain for situations where the power stage gain may be low. PRD is used to configure the minimum operating period and KCOMP is used to configure the maximum operating period. In the context of the compensator they are simply gain terms that modify the overall transfer function by a fixed value. It is important to be aware that the proper way to configure PRD and KCOMP varies based on the control topology implemented. Table 9. Programming Digital Control Loop SYSTEM NAME Complex Zeros (K0, fz, Qz, fp) TRANSFER FUNCTIONS s 2 2 (2 ´ p ´ fz ) + s +1 2 ´ p ´ fz ´ Qz æ ö s s ´ç + 1÷ ç ÷ 2 ´ p ´ K 0 è 2 ´ p ´ fp ø Real Zeros (K0, fz1, fz2, fp) s2 2 (2 ´ p ´ fz ) + s +1 2 ´ p ´ fz ´ Qz æ ö s s ´ç + 1÷ ÷ 2 ´ p ´ K 0 çè 2 ´ p ´ fp ø Device PID (Kp, Ki, Kd, α) æ ö 1 + z -1 1 - z -1 1 1000 ´ ç K p + K i ´ + Kd ´ ÷ ´ 2-SC ´ KCOMP ´ 2-19 ´ -1 -8 -1 ÷ 4 ç 1- z 1- a ´ 2 ´ z ø 2 ´ (PRD + 1) è The compensator of this EVM is configured to acquire one sample per switching cycle, TS, as defined by Equation 17 where TDPWM = 250 ps, Ts = 16 ´ (PRD + 1) ´ TDPWM (17) When the converter operates in PWM mode KCOMP = PRD and the “Device PID” option in Table 9 is expressed in Equation 16 which correctly describes the behavior of the compensator. For clarity Equation 18 displays the exact transfer function used in PWM mode operation. æ ö 2-SC ´ PRD ´ 2-19 1 + z -1 1 - z -1 1000 ´ ç K p + K i ´ + Kd ´ ÷´ ç 1 - z -1 1 - a ´ 2-8 ´ z -1 ÷ø 24 ´ (PRD + 1) è (18) Equation 18 is based on a fixed sample rate. This means Equation 18 is assumed with one switching frequency. The value of that frequency is inside the variable z; z = es TS (19) where TS is the switching period, that is the reciprocal of the switching frequency. In PWM mode, the switching frequency is fixed at 200 kHz such that TS is fixed and the only value. Figure 59 shows an example of Bode plot outputs from the GUI. Figure 60 shows the PID coefficients used. Figure 61 shows the schematics used to obtain the Bode Plots in Figure 59 with the PID coefficients shown in Figure 60. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 61 Evaluating the EVM with GUI www.ti.com Figure 59. Bode Plots from GUI 62 12 Digital Full-Bridge Converter Description SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Evaluating the EVM with GUI www.ti.com Figure 60. PID Coefficients Used in Voltage Loop Figure 61. Bode Plots Calculation NOTE: The above Figure 61 schematic was used in the bode plots calculation. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback 12 Digital Full-Bridge Converter Description Copyright © 2013–2019, Texas Instruments Incorporated 63 Firmware Development for HSFB Power Converter A.9 www.ti.com Firmware Development for HSFB Power Converter Please contact TI for additional information regarding UCD3138 digital HSFB firmware development. A.10 References 1. UCD3138 Datasheet, Highly Integrated Digital Controller for Isolated Power, (Texas Instruments, Literature Number SLUSAP2), 2012 2. UCD3138CC64EVM-030 Evaluation Module and User’s Guide, Programmable Digital Power Controller Control Card Evaluation Module, (Texas Instruments Literature Number SLUU886), 2012 3. TI Application Manual, UCD3138 Digital Power Peripherals Programmer’s Manual, (Texas Instruments Literature Number SLUU995) 4. TI Application Manual, UCD3138 Monitoring and Communications Programmer’s Manual, (Texas Instruments Literature Number SLUU996) 5. TI Application Manual, UCD3138 ARM and Digital System Programmer’s Manual, (Texas Instruments Literature Number SLUU994) 6. User Guide, UCD3138 Isolated Power Fusion GUI, (please contact TI). Note this User Guide is also available in the GUI after installation. Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (April 2013) to A Revision .......................................................................................................... Page • • 64 changed R91 from 0 Ohm to 3 Ohm (schematic) ..................................................................................... 8 changed R91 from 0 Ohm to 3 Ohm (list of materials) ............................................................................. 22 Revision History SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated STANDARD TERMS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms that accompany such Software 1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system. 2 Limited Warranty and Related Remedies/Disclaimers: 2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement. 2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM. User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10) business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected. 2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. WARNING Evaluation Kits are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User shall operate the Evaluation Kit within TI’s recommended guidelines and any applicable legal or environmental requirements as well as reasonable and customary safeguards. Failure to set up and/or operate the Evaluation Kit within TI’s recommended guidelines may result in personal injury or death or property damage. Proper set up entails following TI’s instructions for electrical ratings of interface circuits such as input, output and electrical loads. NOTE: EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG. Revision History 3 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • • • • Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. 66 Revision History SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Revision History www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur 3.3 Japan 3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に 輸入される評価用キット、ボードについては、次のところをご覧ください。 http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan. If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs (which for the avoidance of doubt are stated strictly for convenience and should be verified by User): 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan. 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/ /www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 3.4 European Union 3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures. SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Revision History 67 Revision History 4 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages. 4.3 Safety-Related Warnings and Restrictions: 4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm. 4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees. 4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements. 5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free. 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED. 7. 68 USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED. Revision History SLUUA95A – April 2013 – Revised September 2019 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Revision History www.ti.com 8. Limitations on Damages and Liability: 8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED. 8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT. 9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs. 10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. 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