UCD7242
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
Digital Dual Synchronous-Buck Power Driver
Check for Samples: UCD7242
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Fully Integrated Power Switches With Drivers
for Dual Synchronous Buck Converters
Full Compatibility With TI Fusion Digital Power
Supply Controllers, Such as the UCD92xx
Family
Wide Input Voltage Range: 4.75 V to 18 V
Operational Down to 2.2 V Input With an
External Bias Supply
Up to 10A Output Current per Channel
Operational to 2 MHz Switching Frequency
High Side Current Limit With Current Limit
Flag
Onboard Regulated 6 V Driver Supply From VIN
Thermal Protection
Temperature Sense Output – Voltage
Proportional to Chip Temperature
UVLO and OVLO Circuits Ensure Proper Drive
Voltage
Rated From –40°C to 125°C Junction
Temperature
RoHS Compliant
Accurate On-Die Current Sensing (±5%)
•
Digitally-Controlled Synchronous-Buck Power
Stages
High Current Dual-Phase VRM/EVRD
Regulators for Desktop, Server, Telecom and
Notebook Processors
TMON
VIN
PWM-B
SRE-B
FLT-B
VGGDIS
PWM-A
SRE-A
FLT-A
IMON-B
IMON-A
BST-B
BST-A
BSW-B
BSW-A
SW-B
SW-A
PGND
PGND
GND BP3
VGG
DESCRIPTION
The UCD7242 is a complete power system ready to drive two independent buck power supplies (see Figure 1).
High side MOSFETs, low side MOSFETs, drivers, current sensing circuitry and necessary protection functions
are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits
provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous
rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6.25 V by an internally regulated VGG
supply. The internal VGG regulator can be disabled to permit the user to supply an independent gate drive
voltage. This flexibility allows a wide power conversion input voltage range of 2.2V to 18V. Internal under voltage
lockout (UVLO) logic ensures VGG is good before allowing chip operation.
The synchronous rectifier enable (SRE) pin controls whether or not the low-side MOSFET is turned on when the
PWM signal is low. When SRE is high the part operates in continuous conduction mode for all loads. In this
mode the drive logic block uses the PWM signal to control both the high-side and low-side gate drive signals.
Dead time is also optimized to prevent cross conduction. When SRE is low, the part operates in discontinuous
conduction mode at light loads. In this mode the low-side MOSFET is always held off.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
On-board comparators monitor the current through the high side switch to safeguard the power stage from
sudden high current loads. Blanking delay is set for the high side comparator to avoid false reports coincident
with switching edge noise. In the event of an over-current fault, the high-side FET is turned off and the Fault Flag
(FLT) is asserted to alert the controller.
MOSFET current is measured and monitored by a precision integrated current sense element. This method
provides an accuracy of ±5% over most of the load range. The amplified signal is available for use by the
controller on the IMON pin.
An on-chip temperature sense converts the die temperature to a voltage at the TMON pin for the controller’s use.
If the die temperature exceeds 170°C, the temperature sensor initiates a thermal shutdown that halts output
switching and sets the FLT flag. Normal operation resumes when the die temperature falls below the thermal
hysteresis band.
VIN
VIN
VIN
TMON
30
31
32
27
19
28
29
VIN
UCD7242
PWM-B
PWM-A
1
Thermal
Sense
SRE-B
Drive
Logic
2
FLT-B
26
SRE-A
Drive
Logic
25
FLT-A
9
18
VIN
IMON-B
VGG
Generator
Current
Sense
Processor
7
BST-B
Current
Sense
Processor
3
IMON-A
20
BST-A
24
VIN
VIN
BSW-A
BSW-B
4
VOUT-B
Driver
23
Driver
SW-A
SW-B
13
14
PGND
VOUT-A
PGND
10
Driver
VDD LDO
11
15
Driver
16
12
17
8
Testmode
21
GND
6
22
VGG DIS BP3
5
VGG
Short
Figure 1. Typical Application Circuit and Block Diagram
2
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE, TA
PIN COUNT
–40°C to 125°C
32-pin
ORDERABLE PART
NUMBER
SUPPLY
UCD7242RSJR
Reel of 2500
UCD7242RSJT
Reel of 250
PACKAGE
TOP SIDE MARKING
QFN
UCD7242
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIN
Supply voltage
BST
Boot voltage
VGG, VGG_DIS
Gate supply voltage
BP3
Logic supply voltage
DC
RATING
VALUE
–0.3 to 20
V
–0.3 to SW + 7
V
34
V
7
V
AC (2)
DC
4
V
–2 to VIN + 1
V
34
V
SW, BSW
Switch voltage
TMON, IMON, Testmode
Analog outputs
–0.3 to 3.6
V
PWM-A, PWM-B, SRE-A,
SRE-B, FLT-A, FLT-B
Digital I/O’s
–0.3 to 5.5
V
TJ
Junction temperature
–55 to 150
°C
Tstg
Storage temperature
–55 to 150
°C
ESD rating
HBM: Human Body model
2000
V
CDM: Charged device model
500
V
(1)
AC (2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive
into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of
packages.
AC levels are limited to within 5 ns.
(2)
DISSIPATION RATINGS (TYPICAL)
PACKAGE
AIRFLOW (LFM)
RθJA TI EVM BOARD (1)
POWER RATING
TA = 25°C
POWER RATING
TA = 85°C
0 (natural convection)
19.1°C/W
5.2 W
2.1 W
200
15.1°C/W
6.6 W
2.6 W
400
13.4°C/W
7.5 W
3.0 W
RSJ
(1)
Data taken using TI EVM.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
VIN
Power input voltage (internally generated VGG)
4.75
12
18
V
VIN
Power input voltage (externally generated VGG)
2.2
12
18
V
VGG
Externally supplied gate drive voltage
4.75
6.2
TJ
Operating junction temperature range
–40
125
°C
fs
Switching frequency
300
2000
kHz
750
V
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UNIT
3
UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –40°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX
UNIT
SUPPLY SECTION
Supply current
Outputs not switching, VIN = 2.2 V,
PWM(INH) = LOW, SRE(INL) = HIGH,
VGG_DIS = HIGH, VGG = 5V
6
mA
Outputs not switching, VIN = 18 V,
PWM(INH) = LOW, SRE(INL) = HIGH,
VGG_DIS = LOW
6
mA
GATE DRIVE UNDER VOLTAGE LOCKOUT
VGG
UVLO ON
BP3 Rising
UVLO OFF
BP3 Falling
4.0
UVLO hysteresis
V
3.8
V
200
mV
VGG SUPPLY GENERATOR
VGG
VIN = 7 to 18 V
VGG drop out
5.2
6.25
6.8
V
600
mV
3.3
3.45
V
2.1
2.3
V
VIN = 4.75 to 7 V, IVGG < 50 mA
BP3 SUPPLY VOLTAGE
BP3
IDD = 0 to 10 mA
3.15
INPUT SIGNAL (PWM, SRE)
VIH
Positive-going input threshold voltage
VIL
Negative-going input threshold voltage
1
3-state Condition
tHLD_R
IPWM
1.4
3-state hold-off time
Input current
275
VPWM = 5.0 V
133
VPWM = 3.3 V
Input current
V
1.9
VPWM = 1.65 V
V
ns
μA
66
VPWM = 0 V
ISRE
1.2
–66
VSRE = 5.0 V
1
VSRE = 3.3 V
1
VSRE = 0 V
1
μA
VGG DISABLE (VGG_DIS)
Input resistance to AGND
VGG_DIS
50
Threshold
100
1.35
Hysteresis
150
1.6
550
kΩ
V
mV
FAULT FLAG (FLT)
FLT Output High Level
IOH = 2 mA
FLT Output Low Level
IOL = –2 mA
2.7
V
0.6
V
CURRENT LIMIT
Over current threshold
14.5
15
Tfault_HS delay until HS FET off (1)
Tfault_FF delay until FLT asserted (1)
Propagation delay from PWM to reset FLT (1)
High side blanking time
(1)
1st falling edge of PWM without a fault event
Over currents during this period will not be detected
15.5
A
80
ns
100
ns
100
ns
60
ns
21
μA/A
CURRENT SENSE AMPLIFIER
Gain
Bandwidth
(1)
4
IMON/ IOUT, (see Figure 14 )
(1)
19
5
20
kHz
As designed and characterized. Not 100% tested in production.
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –40°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX
UNIT
THERMAL SENSE
Thermal shutdown (2)
170
Thermal shutdown hysteresis (2)
°C
20
°C
10
mV/°C
470
mV
32
ns
High side MOSFET RDS(ON)
15.5
mΩ
Low side MOSFET RDS(ON)
6.5
Temperature Sense T (2)
Gain, TJ = –20°C to 125°C
Temperature Sense T Offset (2)
TJ = 0°C, –100 μA ≤ ITMON ≤ 100 μA
POWER MOSFETS
Propagation delay from PWM to switch node
going high
5
10
ns
(2)
6
11
ns
Low side MOSFET turn on – Dead Time
(2)
mΩ
High side MOSFET turn on – Dead Time (2)
As designed and characterized. Not 100% tested in production.
DEVICE INFORMATION
PINOUT
32 31
VIN
30
29
VIN
NC
PINOUT
(BOTTOM VIEW)
VIN
SWA
SWB
VIN
NC
VIN
PINOUT
(TOP VIEW)
27 28
28 27
29
30
31 32
VIN
PWM_B
1
26
PWM_A
26
1
SRE_B
2
25
SRE_A
25
2
24
BST_A
24
3
23
BSW_A
23
4
22
BP3
22
5
21
6
BST_B
3
BSW_B
4
VGG
5
VGG_DIS
6
IMON_B
testmode
7
20
AGND
IMON_A
21
20
7
8
19
TMON
19
8
FLT_B
9
18
FLT_A
18
9
Special
6mm x 6mm
QFN
Pkg Code: RSJ
PGND
12
13
14
15
16 17
PGND
SWB
SWA
PGND
NC
PGND
NC
10 11
PGND
PGND
17 16
15
14
13
12
11
10
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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PIN FUNCTIONS
UCD7242 –BUCK POWER STAGE
QFN
PIN NAME
I/O
FUNCTION
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-B is high.
1
I
PWM = high
PWM = low
PWM = 1.65 V
SRE = high
HS = on, LS = off
HS = off, LS = on
HS = off, LS = off
SRE = low
HS = on, LS = off
HS = off, LS = off
HS = off, LS = off
2
SRE-B
I
Synchronous Rectifier Enable input for the B-channel. High impedance digital input capable of
accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
3
BST_B
I
Connection for the B-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic capacitor from this pin to BSW-B (pin 4).
4
BSW-B
I
Connection for B-channel charge pump capacitor. Internally connected to SW-B.
5
VGG
I/O
Gate drive voltage for the power MOSFETs. For VIN ≥ 4.75V, the internal VGG generator can be used.
For VIN < 4.75 V, this pin should be driven from an external bias supply. When externally driven,
VGG_DIS must be tied to VGG. In all cases, bypass this pin with a 4.7μF (min), 10V (min) ceramic
capacitor to PGND.
6
VGG_DIS
I
When tied to VGG, disables the on-chip VGG generator to allow gate drive voltage to be supplied from
an external source. This is required when VIN is < 4.75V. To use the internal VGG generator, tie to
GND.
7
IMON-B
O
MOSFET current sense monitor output. Provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
8
testmode
I
Test mode only. Tie to GND.
9
FLT-B
O
Fault flag for the B-channel. This signal is a 3.3V digital output which is latched high when the current
in the B-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor will initiate a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
10, 12, 15, 17
PGND
–
Shared power ground return for the buck power stage
11, 16
NC
–
No internal connection. It is recommended that these pins be tied to PGND.
13
SW-B
–
Switching node of the B-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
14
SW-A
–
Switching node of the A-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
O
Fault flag for the A-channel. This signal is a 3.3V digital output which is latched high when the current
in the A-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor initiates a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
18
6
PWM-B
FLT-A
19
TMON
O
Temperature sense pin. The voltage on this pin is proportional to the die temperature. The gain is
10mV/°C. At TJ = 0°C, the output voltage has an offset of 0.47V. When the die temperature reaches
the thermal shutdown threshold, this pin is pulled to BP3 and the power FETs are switched off. When
the die temperature falls below the thermal hysteresis band, the FLT flag clears and normal operation
resumes.
20
IMON -A
O
MOSFET current sense monitor output. Provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
21
GND
–
Analog ground return.
22
BP3
O
Output of internal 3.3V LDO regulator for powering internal logic circuits. Bypass this pin with 1μF
(min) to GND. This LDO is supplied by the VGG pin.
23
BSW-A
–
Connection for A-channel charge pump capacitor. Internally connected to SW-A.
24
BST-A
–
Connection for the A-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic cap from this pin to BSW-A (pin 23).
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
PIN FUNCTIONS (continued)
UCD7242 –BUCK POWER STAGE
QFN
PIN NAME
I/O
FUNCTION
25
SRE-A
I
Synchronous Rectifier Enable input for the A-channel. High impedance digital input capable of
accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-A is high.
26
PWM -A
I
PWM = high
PWM = low
PWM = 1.65 V
SRE = high
HS = on, LS = off
HS = off, LS = on
HS = off, LS = off
SRE = low
HS = on, LS = off
HS = off, LS = off
HS = off, LS = off
27, 29, 30, 32
VIN
–
Input Voltage to the buck power stage and driver circuit
28, 31
NC
–
No internal connection. It is recommended that these pins be tied to VIN.
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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TYPICAL CHARACTERISTICS
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
Efficiency - %
90
85
VO = 3.3 V, fs = 500 kHz, VI = 8 V
VO = 3.3 V, fs = 750 kHz, VI = 8 V
VO = 3.3 V, fs = 1 MHz, VI = 8 V
VO = 2 V, fs = 500 kHz, VI = 8 V
80
VO = 2 V, fs = 750 kHz, VI = 8 V
VO = 2 V, fs = 1 MHz, VI = 8 V
VO = 1.2 V, fs = 500 kHz, VI = 8 V
75
VO = 1.2 V, fs = 750 kHz, VI = 8 V
VO = 1.2 V, fs = 1 MHz, VI = 8 V
0
2
4
6
8
10
6
8
10
Load - A
Figure 2.
UCD7242
3
VO = 3.3 V, fs = 500 kHz, VI = 8 V
VO = 3.3 V, fs = 750 kHz, VI = 8 V
VO = 3.3 V, fs = 1 MHz, VI = 8 V
VO = 2 V, fs = 500 kHz, VI = 8 V
2.5
Power Loss - W
VO = 2 V, fs = 750 kHz, VI = 8 V
VO = 2 V, fs = 1 MHz, VI = 8 V
VO = 1.2 V, fs = 500 kHz, VI = 8 V
2
VO = 1.2 V, fs = 750 kHz, VI = 8 V
VO = 1.2 V, fs = 1 MHz, VI = 8 V
1.5
1
0.5
0
0
2
4
Load - A
Figure 3.
8
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
Efficiency - %
90
85
VO = 3.3 V, fs = 500 kHz, VI = 10 V
VO = 3.3 V, fs = 750 kHz, VI = 10 V
VO = 3.3 V, fs = 1 MHz, VI = 10 V
VO = 2 V, fs = 500 kHz, VI = 10 V
80
VO = 2 V, fs = 750 kHz, VI = 10 V
75
VO = 2 V, fs = 1 MHz, VI = 10 V
VO = 1.2 V, fs = 500 kHz, VI = 10 V
VO = 1.2 V, fs = 750 kHz, VI = 10 V
VO = 1.2 V, fs = 1 MHz, VI = 10 V
70
0
2
4
6
8
10
6
8
10
Load - A
Figure 4.
UCD7242
3
2.5
VO = 3.3 V, fs = 500 kHz, VI = 10 V
VO = 3.3 V, fs = 750 kHz, VI = 10 V
VO = 3.3 V, fs = 1 MHz, VI = 10 V
VO = 2 V, fs = 500 kHz, VI = 10 V
Power Loss - W
VO = 2 V, fs = 750 kHz, VI = 10 V
2
VO = 2 V, fs = 1 MHz, VI = 10 V
VO = 1.2 V, fs = 500 kHz, VI = 10 V
VO = 1.2 V, fs = 750 kHz, VI = 10 V
VO = 1.2 V, fs = 1 MHz, VI = 10 V
1.5
1
0.5
0
0
2
4
Load - A
Figure 5.
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
Efficiency - %
85
80
VO = 3.3 V, fs = 500 kHz, VI = 12 V
VO = 3.3 V, fs = 750 kHz, VI = 12 V
VO = 3.3 V, fs = 1 MHz, VI = 12 V
VO = 2 V, fs = 500 kHz, VI = 12 V
75
VO = 2 V, fs = 750 kHz, VI = 12 V
70
VO = 2 V, fs = 1 MHz, VI = 12 V
VO = 1.2 V, fs = 500 kHz, VI = 12 V
VO = 1.2 V, fs = 750 kHz, VI = 12 V
VO = 1.2 V, fs = 1 MHz, VI = 12 V
65
0
2
4
6
8
10
6
8
10
Load - A
Figure 6.
UCD7242
2.5
VO = 3.3 V, fs = 500 kHz, VI = 12 V
VO = 3.3 V, fs = 750 kHz, VI = 12 V
VO = 3.3 V, fs = 1 MHz, VI = 12 V
VO = 2 V, fs = 500 kHz, VI = 12 V
2
VO = 2 V, fs = 1 MHz, VI = 12 V
VO = 1.2 V, fs = 500 kHz, VI = 12 V
Power Loss - W
3
VO = 2 V, fs = 750 kHz, VI = 12 V
VO = 1.2 V, fs = 750 kHz, VI = 12 V
VO = 1.2 V, fs = 1 MHz, VI = 12 V
1.5
1
0.5
0
0
2
4
Load - A
Figure 7.
10
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UCD7242
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
Efficiency - %
85
80
75
VO = 3.3 V, fs = 500 kHz, VI = 14 V
VO = 3.3 V, fs = 750 kHz, VI = 14 V
VO = 3.3 V, fs = 1 MHz, VI = 14 V
VO = 2 V, fs = 500 kHz, VI = 14 V
70
VO = 2 V, fs = 750 kHz, VI = 14 V
VO = 2 V, fs = 1 MHz, VI = 14 V
VO = 1.2 V, fs = 500 kHz, VI = 14 V
65
VO = 1.2 V, fs = 750 kHz, VI = 14 V
VO = 1.2 V, fs = 1 MHz, VI = 14 V
60
0
2
4
6
8
10
6
8
10
Load - A
Figure 8.
UCD7242
3
Power Loss - W
2.5
VO = 3.3 V, fs = 500 kHz, VI = 14 V
VO = 3.3 V, fs = 750 kHz, VI = 14 V
VO = 3.3 V, fs = 1 MHz, VI = 14 V
VO = 2 V, fs = 500 kHz, VI = 14 V
VO = 2 V, fs = 750 kHz, VI = 14 V
VO = 2 V, fs = 1 MHz, VI = 14 V
VO = 1.2 V, fs = 500 kHz, VI = 14 V
2
VO = 1.2 V, fs = 750 kHz, VI = 14 V
VO = 1.2 V, fs = 1 MHz, VI = 14 V
1.5
1
0.5
0
0
2
4
Load - A
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242 1 Rail Operating
50
IGG - mA
fs = 2000 kHz
40
fs = 1500 kHz
30
fs = 1000 kHz
20
fs = 500 kHz
10
fs = 0 kHz
0
4
4.5
5
5.5
6
6.5
VGG - V
Figure 10. VGG Supply Current with 1 Rail Operating and 1 Rail Off
UCD7242 2 Rail Operating
fs = 2000 kHz
80
IGG - mA
fs = 1500 kHz
60
fs = 1000 kHz
40
fs = 500 kHz
20
fs = 0 kHz
0
4
4.5
5
5.5
6
6.5
VGG - V
Figure 11. VGG Supply Current with 2 Rails Operating
12
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TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
Continuous Operation at IOUT = 10A
10
7
5
MTTF - Years
TJ = 150°C
3
TJ = 140°C
2
TJ = 130°C
TJ = 120°C
1
TJ = 110°C
0
20
30
50
Duty Cycle - %
70
100
Figure 12.
Figure 12 shows the mean time to failure (MTTF) for an output load current of 10A on a single output, or an
output load current of 10A on both outputs.
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DETAILED DESCRIPTION
PWM INPUT
The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET on
time. This input is designed to accept 3.3V logic levels, but is also tolerant of 5V input levels. The SRE pin sets
the behavior of the PWM pin. When the SRE pin is asserted high, the device is placed in synchronous mode. In
this mode, the timing duration of the high-side gate drive and the low-side gate drive are both controlled by the
PWM input signal. When PWM is high, the high-side MOSFET is on and the low-side MOSFET is off. When
PWM is low, the high-side MOSFET is off and the low-side MOSFET is on. An optimized anti-cross-conduction
delay is introduced to ensure the proper FET is turned off before the other FET is turned on. When the SRE pin
is asserted low, the device is placed in non-synchronous mode. In this mode the PWM input only controls the
high-side MOSFET. When PMW is high, the high-side MOSFET is on. The low side FET is always held off.
The PWM input supports a 3-state detection feature. It can detect if the PWM input signal has entered a 3-state
mode. When 3-state mode is detected, both the high-side and low-side MOSFETs are held off. To support this
mode, the PWM input pin has an internal pull-up resistor of approximately 50kΩ to 3.3V and a 50kΩ pull-down
resistor to ground. During normal operation, the PWM input signal swings below 0.8V and above 2.5V. If the
source driving the PWM pin enters a 3-state or high impedance state, the internal pull-up/pull down resistors will
tend to pull the voltage on the PWM pin to 1.65V. If the voltage on the PWM pin remains within the 0.8V to 2.5V
3-state detection band for longer than tHLD_R, 3-state detection hold-off time, then the device enters 3-state mode
and turns both MOSFETs off. This behavior occurs regardless of the state of the SRE pin. When exiting 3-state
mode, PWM should first be asserted low and SRE High. This ensures that the bootstrap capacitor is recharged
before attempting to turn on the high-side FET. The logic threshold of this pin typically exhibits 900mV of
hysteresis to provide noise immunity and ensure glitch-free operation.
SRE INPUT
The SRE (Synchronous Rectifier Enable) pin is a high impedance digital input. It is designed to accept 3.3V logic
levels, but is also tolerant of 5V levels. When asserted high, the operation of the low-side synchronous rectifier
FET is enabled. The state of the low-side MOSFET is governed by the PWM input. When SRE is asserted low,
the low-side FET is continuously held low, keeping the FET off. While held off, current flow in the low-side FET is
restricted to its intrinsic body diode. The logic threshold of this pin typically exhibits 900mV of hysteresis to
provide noise immunity and ensure glitch-free operation.
VIN
VIN supplies power to the internal circuits of the device. The input power is conditioned by an internal linear
regulator that provides the VGG gate drive voltage. A second regulator that operates off of the VGG rail produces
an internal 3.3V supply that powers the internal analog and digital functional blocks. The VGG regulator produces
a nominal 6.2V. The output of the VGG regulator is monitored by the Under-Voltage Lock Out (UVLO) circuitry.
The device will not attempt to produce gate drive pulses until the VGG voltage is above the UVLO threshold. This
ensures that there is sufficient voltage available to drive the power FETs into saturation when switching activity
begins. To use the internal VGG regulator, VIN should be at least 4.7V. When performing power conversion with
VIN values less than 4.7V, the gate drive voltage must be supplied externally. (See VGG and VGG DIS sections
for details.)
VGG
The VGG pin is the gate drive voltage for the high current gate driver stages. For VIN ≥ 4.75V, the internal VGG
generator can be used. For VIN < 4.75 V, this pin should be driven from an external bias supply. When using the
internal regulator, the VGG_DIS pin should be tied low. When using an external VGG, VGG_DIS must be tied to
VGG. Current is drawn from the VGG supply in fast, high-current pulses. A 4.7μF ceramic capacitor (10V
minimum) should be connected from the VGG pin to the PGND pin as close as possible to the package. Whether
internally or externally supplied, the voltage on the VGG pin is monitored by the ULVO circuitry. The voltage must
be higher than the UVLO threshold before power conversion can occur. The average current drawn from the VGG
supply is dependant on the switching frequency, the absolute value of VGG and the total gate charge of the power
FETs inside the device.
14
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VGG_DIS
This pin, when asserted high, disables the on-chip VGG linear regulator. When tied low, the VGG linear regulator
is used to derive VGG from VIN. This pin is designed to be permanently tied high or low depending on the power
architecture being implemented. It is not intended to be switched dynamically while the device is in operation.
SW
The SW pin is the switching node of the power conversion stage. When configured as a synchronous buck, the
voltage swing on SW normally traverses from slightly below ground to above VIN. Parasitic inductance in the
high-side FET conduction path and the output capacitance (Coss) of the low side FET form a resonant circuit
than can produce high frequency ( > 100MHz) ringing on this node. The voltage peak of this ringing will exceed
VIN. Care must be taken not to exceed the maximum voltage rating of this pin. The main areas available to
impact this amplitude are: the driver voltage magnitude (VGG) and the parasitic source and return paths for the
MOSFET (VIN, PGND). In some cases, a series resistor and capacitor snubber network connected from this pin
to PGND can be helpful in damping the ringing and decreasing the peak amplitude. In general this should not be
necessary due to the integrated nature of this part.
BST
The BST pin provides the drive voltage for the high-side FET. A bootstrap capacitor is connected from this pin to
the BST-SW node. Internally, a diode connects the BST pin to the VGG supply. In normal operation, when the
high side FET is off and the low-side FET is on, the SW node is pulled to ground and, thus, holds one side of the
bootstrap capacitor at ground potential. The other side of the bootstrap capacitor is clamped by the internal diode
to VGG. The voltage across the bootstrap capacitor at this point is the magnitude of the gate drive voltage
available to switch-on the high-side FET. The bootstrap capacitor should be a low ESR ceramic type, a minimum
value of 0.22μF is recommended.
In order to ensure that the bootstrap capacitor has sufficient time to recharge, the steady-state duty cycle must
not exceed what is shown in Figure 13. The curve in Figure 13 is for CBST= 0.22µF. Different values of CBST will
have different DMAX limitations.
96
Maximum Duty Cycle - %
94
92
90
88
86
0.6
0.8
1
1.2
1.4
1.6
fs - Switching Frequency - MHz
1.8
2
Figure 13.
BST-SW
Electrically this node is the same as the SW pin. However, it is physically closer to the BST pin so as to minimize
parasitic inductance effects of trace routing to the BST capacitor. Keeping the external traces short should
minimize turn on and off times.
This pin is not sized for conducting inductor current and should not be tied to the SW pin. It is only for the BST
pin capacitor connection.
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IMON
MOSFET current sense monitor output. This pin provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should be
connected to a resistor to GND to produce a voltage proportional to the power-stage load current. For example, a
value of 10kΩ to ground produces a voltage of 2.0V when the power stage current is 10A.The accuracy of the
reported current is a function of the peak to peak ripple current in the inductor (ΔI). The nominal behavior is
described by Equation 1. The plot illustrates the possible variability in the sensed current as a function of load for
a ΔI=4A. If no PWM is detected for 8µs IMON will report 0V.
ì μA
ïï20 A IOUT
IMON(IOUT, DI) = í
ï10 μA IOUT + 5 μA DI
ïî
A
A
ΔI ü
2 ïï
ý
ΔI ï
If IOUT <
2 ïþ
If IOUT ³
(1)
200
175
150
125
100
75
50
DI = 4 A
25
0
0
1
2
3
4
5
6
IOUT (A)
7
8
9
10
Figure 14. Sensed Current Variability
TMON
The voltage on this pin is proportional to the die temperature with a gain of 10 mV/°C and an offset voltage of
0.47 V at TJ = 0°C (Equation 2):
10mV
TMON(TJ) = 0.47 V +
(TJ )
°C
(2)
16
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2.0
1.8
1.6
TMON - V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
TJ - Junction Temperature - °C
Figure 15. Typical Characteristics
If the junction temperature exceeds approximately 170°C, the device will enter thermal shutdown. This will assert
the FLT pin, both MOSFETs will be turned off and the switch node will go high impedance. When the junction
temperature cools by approximately 20°C, the device will exit thermal shutdown and resume switching as
directed by the PWM and SRE pins. During a thermal shutdown event, the voltage on the Temp pin is driven to
3.3V.
FLT
This signal is a 3.3V digital output which is latched high when the current in the high-side FET exceeds the
current limit trip point. When tripped, high-side FET drive pulses are truncated to limit output current. FLT is
cleared on the falling edge of the first PWM pulse without a fault. Additionally, if the die temperature exceeds
170°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag.
Normal operation resumes when the die temperature falls below the thermal hysteresis band. The FLT flag will
clear after a PWM pulse occurs without a fault. Current limit is ignored during the high side blanking time. If an
over current event occurs during the blanking time the part will not initiate current limit for ~50ns.
PWM
ILIMIT
IL
HS
LS
FLT
Figure 16. FLT Signal
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APPLICATION INFORMATION
A partial schematic of a power supply application using the UCD7242 power stage is provided below. Although
not shown the IC controlling the output is from the UCD92XX family of digital controllers.
Vin
+
330 mF
PWM1
26 PWM-A
Vin 29
SRE1
25 SRE-A
NC 28
FF1
18 FLT-A
Vin 27
CS1
20 IMON-A
EAp1
22 mF 25 V
1 PWM-B
BST-A 24
SRE2
2 SRE-B
BSW-A 23
FF2
9 FLT-B
PGND 15
CS2
7 IMON-B
19 TMON
Vout1
SW-A 14
PWM2
Temp
10 W
800 nH
+
0.22 mF
47 mF
330 mF
RBIAS
GND
NC 16
10 W
EAn1
PGND 17
Vin 30
EAp2
10 kW
10 kW
UCD7242
NC 31
22 mF 25 V
Vin 32
22 BP3
10 W
800 nH
Vout2
SW-B 13
1 mF
21 AGND
BST-B 3
BSW-B 4
5 VGG
4.7 mF
6 VGG DIS
8 Test
+
0.22 mF
47 mF
RBIAS
GND
PGND 10
NC 11
PGND 12
330 mF
10 W
EAn2
PRE-BIAS OPERATION
The UCD7242 has no problem starting up into pre-biased output voltages. However, when one channel is held in
tri-state and the second channel is actively switching, the tri-stated channel may generate a DC voltage through
weak capacitive coupling between SW-A and SW-B. This coupling comes principally from the close proximity of
the switch nodes on the silicon and the PWB layout.
There are several options to address this concern.
1. The device(s) that the UCD7242 is powering on a 3-stated channel has a known current draw at subregulation voltage levels. This current draw may be sufficient to hold the voltage down.
2. Instead of holding the off channel in a 3-state condition, drive PWM actively low. This forces the synchronous
rectifier to turn on and prevent the pre-bias voltage from rising. If this option is elected, it is important to verify
that there are no other sources of leakage in the system.
3. Add a small load resistor, RBIAS. In most cases a value of 1kΩ should keep the output voltage below 200mV.
Some experimentation may be needed to determine the appropriate value. In many cases, the feedback
divider may provide a sufficient load.
It is important that VBIAS be less than or equal to the steady state output voltage during regulation. If this
condition is not enforced the controller in charge of regulating this rail will be unable to start up. If start up is
forced, damage may result.
18
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OPERATING FREQUENCY
Switching frequency is a key place to start the design of any DC/DC converter. This will set performance limits on
things such as: maximum efficiency, minimum size, and achievable closed loop bandwidth. A higher switching
frequency is, generally, going to yield a smaller design at the expense of a lower efficiency. The size benefit is
principally a result of the smaller inductor and capacitor energy storage elements needed to maintain ripple and
transient response requirements. The additional losses result from a variety of factors, however, one of the
largest contributors is the loss incurred by switching the MOSFETs on and off. The integrated nature of the
UCD7242 makes these losses drastically smaller and subsequently enables excellent efficiency from a few
hundred kHz up to the low MHz. For a reasonable trade off of size versus efficiency, 750kHz is a good place to
start.
VGG
If 4.75V < VIN ≤ 6V a simple efficiency enhancement can be achieved by connecting VGG_DIS and VGG directly to
VIN. This allows the solution to bypass the drop out voltage of the internal VGG linear regulator, subsequently
improving the enhancement of the MOSFETs. When doing this it is critical to make sure that VGG never exceeds
the absolute maximum rating of 7V.
INDUCTOR SELECTION
There are three main considerations in the selection of an inductor once the switching frequency has been
determined. Any real world design is an iterative trade off of each of these factors.
1. The electrical value which in turn is driven by:
(a) RMS current
(b) The maximum desired output ripple voltage
(c) The desired transient response of the converter
2. Losses
(a) Copper (PCu)
(b) Core (Pfe)
3. Saturation characteristics of the core
INDUCTANCE VALUE
The principle equation used to determine the inductance is:
di (t)
vL (t) = L L
dt
(3)
During the on time of the converter the inductance can be solved to be:
V - VOUT D
L = IN
DI
¦s
(4)
Where:
VIN
Input Voltage
VOUT
Output voltage
fs
Switching frequency
D
Duty cycle (VOUT/VIN for a buck converter)
ΔI
The target peak to peak inductor current.
In general, it is desirable to make ΔI large to improve transient response and small to reduce output ripple
voltage and RMS current. A number of considerations go into this however, ΔI = 0.4 IOUT results in a small ILRMS
without an unnecessary penalty on transient response. It also creates a reasonable ripple current that most
practical capacitor banks can handle. Here IOUT is defined as the maximum expected steady state current.
Plugging these assumptions into the above inductance equation results in:
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V - VOUT D
L = 5 IN
2 ´ IOUT ¦s
(5)
For example, plotting this result as a function of VIN and VOUT results in:
Figure 17. Inductance vs. VIN and VOUT
In this graph IOUT is 10A, the switching frequency is 750kHz and the inductor ΔI is 4A. If the switching frequency
is cut in half then the resulting inductance would be twice the value shown. Notice that the maximum inductance
occurs at the maximum VIN and VOUT shown on the plot. In general, this inductance value should be used in
order to keep the inductor ripple current from becoming too large over the range of supported VIN and VOUT.
INDUCTOR LOSSES AND SATURATION
The current rating of an inductor is based on two things: the current necessary to raise the component
temperature by 40°C and the current level necessary to reduce the inductance to 80% of its initial value
(saturation current (1) ). The current rating is the lower of these two numbers. Both of these factors are influenced
by the choice of core material. Popular materials currently in use are: ferrite, powdered alloy and powdered iron.
Ferrite is regarded as the highest performance material and as such is the lowest loss and the highest cost. Solid
ferrite all by itself will saturate with a relatively small amount of current. This can be addressed by inserting a gap
into the core. This, in effect, makes the inductor behave in a linear manner over a wide DC current range.
However, once the inductance begins to roll off, these gapped materials exhibit a “sharp” saturation
characteristic. In other words, the inductance value reduces rapidly with increases in current above the saturation
level. This small inductance that results, can produce dangerously high current levels.
(1)
20
Although “saturation current” is standard terminology among many inductor vendors, technically saturation does not occur until the
relative permeability of the core is reduced to approximately 1. This is a value much larger than what is typically seen on data sheets.
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Powdered iron has the advantage of lower cost and a soft saturation characteristic; however, its losses can be
very large as switching frequencies increase. This can make it undesirable for a UCD7242 based application
where higher switching frequency may be desired. It’s also worth noting that many powdered iron cores exhibit
an aging characteristic where the core losses increase over time. This is a wear-out mechanism that needs to be
considered when using these materials.
The powdered alloy cores bring the soft saturation characteristics of powdered iron with considerable
improvements in loss without the wear-out mechanism observed in powdered iron. These benefits come at a cost
premium.
In general the following relative figure of merits can be made:
Ferrite
Powdered Alloy
Cost
High
Medium
Powdered Iron
Low
Loss
Low
Medium
High
Saturation
Rapid
Soft
Soft
When selecting an inductor with an appropriate core it’s important to have in mind the following:
1. ILRMS, maximum RMS current
2. ΔI, maximum peak to peak current
3. IMAX, maximum peak current
The RMS current can be determined by Equation 6:
ILRMS = IO UT 2 +
D I2
12
(6)
When the 40% ripple constraint is used at maximum load current, this equation simplifies to: ILRMS≈IOUT.
It is widely recognized that the Steinmetz equation (Pfe) is a good representation of core losses for sinusoidal
stimulation. It is important to recognize that this approximation applies to sinusoidal excitation only. This is a
reasonable assumption when working with converters whose duty cycles are near 50%, however, when the duty
cycle becomes narrow this estimate may no longer be valid and considerably more loss may result.
Pƒe = k × ƒα × BAC β
(7)
(7)
The principle drivers in this equation are the material and its respective geometry (k, α, β), the peak AC flux
density (BAC) and the excitation frequency (ƒ). The frequency is simply the switching frequency of the converter
while the constant k, can be computed based on the effective core volume (Ve) and a specific material constant
(kƒe).
k = kƒe × Ve
(8)
(8)
The AC flux density (BAC) is related to the conventional inductance specifications by the following relationship:
L
DI
B AC =
Ae ´ N 2
(9)
Where L is the inductance, Ae, is the effective cross sectional area that the flux takes through the core and N is
the number of turns.
Some inductor manufactures use the inductor ΔI as a figure of merit for this loss, since all of the other terms are
a constant for a given component. They may provide a plot of core loss versus ΔI for various frequencies where
ΔI can be calculated as:
V - VOUT D
DI = IN
L
¦s
(10)
IMAX has a direct impact on the saturation level. A good rule of thumb is to add 15% of head room to the
maximum steady state peak value to provide some room for transients.
ΔI ö
æ
IMAX = 1.15 × çIOUT +
÷
2ø
è
(11)
For example for a 10A design has the following:
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IOUT
10A
ILRMS
10A
ΔI
4A
IMAX
13.8A
Armed with this data one can now approach the inductor data sheet to select a part with a “saturation” limit
above 13.8A and current “heating” limit above 10A. Furthermore, total losses can be estimated based on the
datasheet DCR value (ILRMS 2DCR) and the core loss curves for a given frequency and ΔI.
INPUT CAPACITANCE
Due to the non-zero impedance of the power planes of the input voltage rail, it is necessary to add some local
capacitance near the UCD7242 to ensure that the voltage at this node is quiet and stable. The primary things to
consider are:
1. The radiated fields generated by the di/dt and dv/dt from this node
2. RMS currents capability needed in the capacitors
3. The AC voltage present and respective susceptibility of any device connected to this node
ICINRMS =
IOUT 2 ´ D ´ (1 - D) +
D I2
´D
12
(12)
As a point of reference if ΔI=0.4 IOUT this places the worst case ICINRMS at approximately 5A. This corresponds to
a duty cycle of approximately 50%. Other duty cycles can result in a significantly lower RMS current.
A good input capacitor would be a 22μF X5R ceramic capacitor. Equally important as selecting the proper
capacitor is placing and routing that capacitor. It is crucial that the decoupling be placed as close as possible to
both the power pin (VIN) and ground (PGND). It is important to recognize that each power stage should have its
own local decoupling. One 22μF capacitor should be placed across each VIN and PGND pair. The proximity of
the capacitance to these pins will reduce the radiated fields mentioned above.
OUTPUT CAPACITANCE
The goal of the output capacitor bank is to keep the output voltage within regulation limits during steady state
and transient conditions.
The total AC RMS current flowing through the capacitor bank can be calculated as:
DI
ICOUTRMS =
12
(13)
For a single type of output capacitor the output ripple voltage wave form can be approximated by the following
equation:
VO UT (t) = IC (t) ´ esr +
1
C
ò
t
IC (t ) ´ dt
0
(14)
Where:
DI ´ ¦ s
ì
DI
D
´ t t<
ï
¦s
D
2
ï
IC (t) = í
ï D I ´ ¦ s ´ æ t - D ö + D I otherwise
ç
÷
ï 1 - D
¦s ø
2
è
î
(15)
After substitution and simplification yields
ì
æ DI ´ ¦ s
DI ö 1 æ t ´ ΔI ´ (¦ s ´ t - D ) ΔI ´ (1 - 2 ´ D ) ö
D
´ t - ÷ + ´ç
esr ´ ç
t<
÷
ï
´
¦
¦
D
2
C
2
×
D
12
è
ø
è
ø
ï
s
s
VO UT (t) = í
æ DI ´ ¦ s æ
D ö DI ö 1 æ DI ´ (¦ s ´ t - 1) ´ (D - ¦ s ´ t ) DI ´ (1 - 2 ´ D ) ö
ï
÷ otherwise
ïesr ´ ç 1- D ´ ç t - ¦ ÷ + 2 ÷ + C ´ ç
2 ´ (1- D ) ´ ¦ s
12 ´ ¦ s
è
è
ø
è
ø
s ø
î
22
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The term in this equation multiplied by the esr gives the ripple voltage component due to esr and the term
multiplied by 1/C gives the ripple voltage component due to the change in charge on the capacitor plates. In the
case were the esr component dominates the peak to peak output voltage can be approximated as:
VPPesr ≉ ΔI × esr
(17)
(17)
When the charge term dominates the peak to peak voltage ripple becomes:
DI
VPPQ »
8 ´ C ´ ¦s
(18)
It is tempting to simply add these two results together for the case where the voltage ripple is significantly
influenced by both the capacitance and the esr. However, this will yield an overly pessimistic result, in that it
does not account for the phase difference between these terms.
Using the ripple voltage equations and the RMS current equation should give a design that safely meets the
steady state output requirements. However, additional capacitance is often needed to meet transient
requirements and the specific local decoupling requirements of any IC that is being powered off of this voltage.
This is not just a function of the capacitor bank but also the dynamics of the control loop. See the UCD9240
Compensation Cookbook for additional details.
DECOUPLING
It is necessary that VGG and BP3 have their own local capacitance as physically close as possible to these pins.
The VGG capacitor should be connected as close as possible to pin 5 and PGND with a 4.7μF ceramic capacitor.
The BP3 capacitor should be connected as close as possible to pin 22 and AGND with a 1μF ceramic capacitor.
The UCD7242 also supports the ability to operate from input voltages down to 2.2V. In these cases an additional
supply rail must be connected to VGG and VGG_DIS must be shorted to VGG. Potential external bias supply
generators for low VIN operation: TPS63000, TPS61220. The amount of current required for this supply is
dependant on the VGG voltage, the switching frequency and the number of active channels used in the UCD7242.
When both sides are active, use Figure 11: VGG Supply Current with 2 Rails Operating for current draw
estimates. If only one side is active, use Figure 10: VGG Supply Current with 1 Rail Operating and 1 Rail Off.
CURRENT SENSE
An appropriate resistor must be connected to the current sense output pins to convert the IMON current to a
voltage. In the case of the UCD9XXX digital controllers, these parts have a full scale current monitor range of 0V
to 2V. It is desirable to maximize this range to make full use of the current monitoring resolution inside the
controller. In order to ensure that current sensing will occur all the way to IMAX=10A a 1.8V target is chosen. In
this case a resistor 9.09kΩ would work.
VMON
RMO N =
mA
IMAX ´ 20
A
(19)
In some applications it may be necessary to filter the IMON signal. The UCD7242 IMON pin is a current source
output, so a capacitor to ground in parallel with the current-to-voltage conversion resistor is all that is required.
As a rule of thumb, placing the corner frequency of the filter at 20% of the switching frequency should be
sufficient.
For example, if the switching frequency is 500kHz or higher the ripple frequency will be easily rejected with a
corner frequency of approximately 100kHz. With a 100kHz pole point, the filter time constant is 1.6µs. A fast
current transient should be detected within 4.8µs.
CMON =
1
2 × p × RMON × 20%×fs
(20)
20A Power Stage
It is possible to configure the UCD7242 to supply 20A by tying the outputs of two power stages together. When
doing this it is required that the PWM pulse widths of the two PWM input signals be identical. The best way to do
this is to drive PWM-A and PWM-B from the same signal. This ensures that balanced volt seconds will be
applied to the external SW pins.
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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Vin
+
330uF
PWM1
26 PWM-A
Vin 29
SRE1
25 SRE-A
NC 28
EAp1
22uF 25V
18 FLT-A
CS1
SN74LVC1G32
FF1
Vin 27
20 IMON-A
SW-A 14
1 PWM-B
BST-A 24
2 SRE-B
BSW-A 23
9 FLT-B
PGND 15
7 IMON-B
10r0
800nH
Vout1
+
0.22uF
47uF
330uF
GND
NC 16
10r0
Temp
19 TMON
EAn1
PGND 17
Vin 30
4k99
UCD7242
NC 31
22uF 25V
Vin 32
1uF
22 VDD
21 AGND
BST-B 3
BSW-B 4
5 VGG
4.7uF
6 VGG DIS
8 Test
800nH
SW-B 13
0.22uF
PGND 10
NC 11
PGND 12
Figure 18. 20A Design
Layout Recommendations
The primary thermal cooling path is from the VIN, GND, and the SW “stripes” on the bottom of the package. Wide
copper traces should connect to these nodes. 1-ounce copper should be the minimum thickness of the top layer;
however, 2-ounce copper is better. Multiple thermal vias should be placed near the GND stripes that connect to a
PCB ground plane. There is room to place multiple 10-mil (0.25mm) diameter vias next to the VIN and GND
stripes under the package.
For input bypassing, the 22µF input ceramic capacitors should be connected as close as possible to the VIN and
GND stripes. If possible, the input caps should be placed directly under the UCD7242 using multiple 10-mil vias
to bring the VIN and GND connections to the back side of the board. Minimizing trace inductance in the bypass
path is extremely important to reduce the amplitude of ringing on the switching node.
24
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
VIN
C32
TP31
CS3
TP32
FF3
TP33
SRE3
22uF 25V
1210
TP34
PWM3
PWM3
26 PWM-A
Vin 29
SRE3
25 SRE-A
Vin 28
C8
FF3
18 FF-A
CS3
Vin 27
20 Isense-A
SW-A 14
PWM4
1 PWM-B
BST-A 24
SRE4
2 SRE-B
BSW-A 23
FF4
9 FF-B
PGND 15
CS4
7 Isense-B
PGND 16
19 Tsense
PGND 17
T2
T2
TP35
CS4
TP36
FF4
TP37
R36
10k0
0603
SRE4
TP38
PWM4
TP39
R35
10k0
0603
R37
10k0
0603
C30
4.7uF
0805
TP46
SW3
EAp3
L1
800nH
HM00-08822LF
12.5 x 10.5mm
TP40
Vout3
R30 TB4
10r0 1x2
0603 0.2
Vout3
C9
C27
0.22uF
0603
+ C10
47uF
1210
RBIAS
330uF
10mm x
12.5mm
TP41
GND
EAn3
GND
R31
10r0
0603
Vin 30
U5
UCD7242
6x6 QFN
Pkg RSJ
C28
Vin 31
Vin 32
22uF 25V
1210
TP47
SW4
EAp4
L2
800nH
HM00-08822LF
12.5 x 10.5mm
TP42
Vout4
R32 TB5
10r0 1x2
0603 0.2
Vout4
SW-B 13
C31
1uF
0603
VGG DIS
TP44
VGG
TP45
22uF 25V
1210
22 BP3
21 AGND
BST-B 3
BSW-B 4
6 VGG DIS
PGND 10
5 VGG
PGND 11
8 Test
PGND 12
C11
C29
0.22uF
0603
+ C12
47uF
1210
RBIAS
330uF
10mm x
12.5mm
TP43
GND
EAn4
GND
R33
10r0
0603
Figure 19. Schematic Fragment from 4-Output EVM
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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Output
cap
PGND
PGND
VIN
Input
caps
PGND
PGND
Output
cap
Figure 20. Top Layer
26
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UCD7242
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SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
Note how the ground
end of the VIN and
VOUT caps and the
PGND stripes of the
UCD7242 are all tied
together with multiple
vias.
Note: This is the primary heat dispersal layer as well as the major return-current path.
Figure 21. Layer 2 - Power GND Plane
Figure 22. Layer 3
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UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
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C32 is another VIN
bypass cap
placed directly
under the part.
Note use of
multiple vias to tie
directly to the VIN
and PGND
stripes.
Figure 23. Bottom Layer (X-ray View)
Spacer
REVISION HISTORY
Changes from Original (January 2010) to Revision A
•
Page
Changed Figure 20 through Figure 23 ............................................................................................................................... 26
Changes from Revision A (June 2012) to Revision B
Page
•
Changed From: VIN ± 4.75V To: VIN ≥ 4.75V, and From: VIN > 4.75 V To: VIN < 4.75 V in the VGG pin Description ............ 6
•
Changed From: VIN > 4.75V To: VIN ≥ 4.75V in the VGG Section ....................................................................................... 14
28
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UCD7242RSJR
ACTIVE
VQFN-HR
RSJ
32
2500
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCD7242
Samples
UCD7242RSJT
ACTIVE
VQFN-HR
RSJ
32
250
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCD7242
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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