UCD90120
www.ti.com.......................................................................................................................................................................................... SLVS966 – SEPTEMBER 2009
UCD90120 12-Channel Sequencer and System Health Monitor
FEATURES
1
DESCRIPTION
The UCD90120 Power Supply Sequencer and
System Health Monitor monitors and sequences up to
12 independent voltage rails. The device integrates a
12-bit ADC with a 2.5V internal reference for
monitoring up to 13 power supply voltage, current, or
temperature inputs.
26 GPIO pins can be used for power supply enables,
power-on reset signals, external interrupts, cascading
multiple UCD90120 devices, or other system
functions. 12 of these pins can be used as PWM
outputs
for
power
supply
margining
or
general-purpose PWM functions including clock
generation for switch-mode power supplies.
The TI Fusion Digital Power Designer is provided for
device configuration. This PC-based Graphical User
Interface (GUI) offers an intuitive interface for
configuring, storing, and monitoring all system
operating parameters.
The
UCD90120
has
an
I2C/PMBus/SMBus
communication interface for pre-production and
in-system configuring and monitoring and a JTAG
Port for production programming.
12V
12V OUT
3.3V_UCD
TEMP IC
TEMP12V
INA196
12V OUT
V33A
V33D
I12V
V33FB
• Monitor and Sequence 12 Voltage Rails
– All Rails Sampled Every 200µs
– 12-bit ADC With 2.5V, 0.5% Internal VREF
– Sequence Based on Time, Rail and Pin
Dependencies
– Six Hardware Comparators for Power
Supply Fault Response in < 80µs
– Four Programmable Under-Voltage and
Over-Voltage Thresholds per Monitor
– Programmable Fault Response Including
Retries, Shutdown Slaves and Resequence
• Non-Volatile Error Logging
– Stores Up To 18 Faults
– Log Peak Values For All Monitor Inputs
• Closed Loop Margining for 10 Rails
– Margin Output Adjusts Rail Voltage to
Match User-Defined Margin Thresholds
– Unused Margin Outputs can be Used as
GPIOs or General-Purpose PWM Outputs
• Watchdog Timer and System Reset
– Programmable WDT Reset and Start Times
– Configurable System Reset Pulse Widths
• Flexible Digital I/O Configuration
– Boolean Logic Builder for GPO Config
– GPIOs can be Used as Enables, Resets,
Power Good and Other On-Board Functions
• Wide Range Single Supply (3.3V to 12V)
– Internal Temperature Sensor
– 64-Pin QFN Package
• JTAG and I2C/SMBus/PMBus Interfaces
• Fusion Digital Power™ GUI for Configuring
and Monitoring Device Operation
2
GPIO
VIN
VMON
/EN
GPIO
3.3V OUT
VMON
1.8V OUT
VMON
0.8V OUT
VMON
I0.8V
VMON
TEMP0.8V
VMON
I12V
VMON
TEMP12V
VMON
/MR
3.3V OUT
VOUT
DC-DC 1
VFB
VIN
/EN
GPIO
VOUT
1.8V OUT
LDO1
UCD90120
TEMP IC
VMON
VIN
WDI from main
processor
GPIO
WDO
GPIO
POWER_GOOD
GPIO
/EN
GPIO
VOUT
TEMP0.8V
0.8V OUT
DC-DC 2
VFB
INA196
APPLICATIONS
•
•
•
•
Industrial / ATE
Telecommunications and Networking
Equipment
Servers and Storage Systems
Any System Requiring Sequencing and
Monitoring of Multiple Power Rails
PWM
WARN_OC_0.8V_
OR_12V
GPIO
SYSTEM RESET
GPIO
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO
2MHz
100kΩ
Rmrg
47pF
I2C/
PMBUS
I0.8V
Vmarg
Closed Loop
Margining
JTAG
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Fusion Digital Power is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UCD90120
SLVS966 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Comparators
JTAG
PMBus
PMBus
Internal
Internal
Temperature
Temperature
Sensor
Sensor
General
General Purpose
Purpose
I I /O
( GPIO )
6
Monitor
Inputs
16
SEQUENCING ENGINE
13
12 -bit
200 ksps ,
ADC
( 2. 5 V , 0 . 5 % ref )
FLASH
FLASHMemory
Memory
User
UserData,
Data, Fault
Fault
andand
Peak
Peak
Logging
Logging
BOOLEAN
Logic Builder
Margining
Margining
Outputs
Outputs
Or
Or
GPIO
GPIO
10
64 -pin QFN
ORDERING INFORMATION
ORDERABLE PART NUMBER
PACKAGE
Supply
UCD90120RGCR
64-pin QFN
Reel of 2000
UCD90120RGCT
64-pin QFN
Reel of 250
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
Voltage applied at V33D to DVSS
–0.3 V to 3.8
V
Voltage applied at V33A to AVSS
–0.3 V to 3.8
V
Voltage applied to any pin
(2)
–0.3 V to 3.8
V
–40 to 150
°C
Human body model (HBM)
2.5
kV
Charged device model (CDM)
750
V
Storage temperature (TSTG)
ESD Rating
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
3.3
V33D, V33DIO, V33A
Supply voltage during operation (V33D, V33DIO, V33A)
3.0
TA
Operating free-air temperature range
–40
TJ
Junction temperature
2
MAX
UNIT
3.6
V
110
°C
125
°C
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
8
15
mA
SUPPLY CURRENT
IV33A
IV33DIO
IV33D
VV33A = 3.3V
Supply current
IV33D
VV33DIO = 3.3V
2
10
mA
VV33D = 3.3V
40
45
mA
VV33D = 3.3V storing configuration parameters
in flash memory
50
55
mA
3.3
3.35
V
4
4.6
V
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
VV33
3.3V Linear Regulator
VV33FB
3.3V linear Reg Feedback
IV33FB
Series pass base drive
Beta
Series NPN pass device
Emitter of NPN transistor
3.25
VVIN = 12V
10
mA
40
EXTERNALLY SUPPLIED 3.3V POWER
VV33D,
VV33DIO
Digital 3.3V power
Tambient = 25°C
3.00
3.60
V
VV33A
Analog 3.3V power
Tambient = 25°C
3.00
3.60
V
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
ANALOG INPUTS (MON1–MON13)
VMON
Input voltage range
MON1–MON9
INL
ADC integral nonlinearity
Ilkg
Input leakage current
3V applied to pin
IOFFSET
Input offset current
1kΩ source impedance
RIN
Input impedance
MON1–MON9, Ground reference
MON10–MON13
MON10–MON13, Ground reference
CIN
Input capacitance
TCONVERT
ADC sample period
VREF
0.0
2.5
0.2
2.5
V
–2.5
2.5
mV
100
nA
–5
5
8
0.5
µA
MΩ
1.5
3.0
10
14 voltages sampled, 3.89 µsec/sample
V
MΩ
pF
µsec
200
ADC 2.5V internal
0°C to 125°C
–0.5%
0.5%
reference accuracy
–40°C to 125°C
–1.0%
1.0%
9
11
ANALOG INPUT (PMBUS_ADDRx, INTERNAL TEMP SENSE)
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage – open pin
AddrSens0,1 open
VADDR_SHORT
Voltage – shorted pin
AddrSens0,1 short to ground
TempInternal
Internal temperature sense
accuracy
Over range from 0°C to 100°C
2.26
µA
V
–5
0.124
V
5
°C
Dgnd +
0.25
V
DIGITAL INPUTS AND OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (1), V33DIO = 3.0 V
VOH
High-level output voltage
IOH = –6 mA (2), V33DIO = 3.0 V
VIH
High-level input voltage
V33DIO = 3.0 V
VIL
Low-level input voltage
V33DIO = 3.5 V
V33DIO
– 0.6V
V
2.1
3.6
V
1.4
V
SYSTEM PERFORMANCE
VDDSlew
Minimum VDD slew rate
VDD slew rate between 2.3 and 2.9V
VRESET
Supply voltage at which device
comes out of reset
For power on reset (POR)
tRESET
Low pulse length needed at nReset
pin
To reset device during normal operation
f(PCLK)
Internal oscillator frequency
TA = 125°C, TA = 25°C
Tretention
Retention of configuration
parameters
TJ = 25°C
100
Years
Write_Cycles
Number of nonvolatile erase/write
cycles
TJ = 25°C
20
K cycles
(1)
(2)
4
0.25
V/ms
2.4
V
µS
2
250
MHz
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop
specified.
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PMBus/SMBus/I2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus is shown below.
I2C/SMBus/PMBus TIMING REQUIREMENTS
TA = –40°C to 85°C, 3.0V < VDD < 3.6V; Typical values at TA = 25°C and VCC = 2.5V (Unless otherwise noted)
MAX
UNIT
FSMB
SMBus/PMBus operating frequency
PARAMETER
Slave mode, SMBC 50% duty
cycle
TEST CONDITIONS
MIN
10
TYP
1000
kHz
FI2C
I2C operating frequency
Slave mode, SCL 50% duty cycle
10
1000
kHz
t(BUF)
Bus free time between start and stop
4.7
µs
t(HD:STA)
Hold time after (repeated) start
0.26
µs
t(SU:STA)
Repeated start setup time
0.26
µs
t(SU:STO)
Stop setup time
0.26
µs
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
t(HIGH)
Clock high period
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
tFALL
Clock/data fall time
tRISE
Clock/data rise time
(1)
(2)
(3)
(4)
(5)
Receive Mode
50
ns
See (1)
35
ms
µs
0.5
50
µs
(3)
25
ms
See
(4)
120
ns
See
(5)
120
ns
0.26
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tf = 0.9VDD to (VILMAX – 0.15)
Figure 1. I2C/SMBus Timing Diagram
Start
Stop
TLOW:SEXT
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
PMB_Clk
Clk ACK
Clk ACK
PMB_Data
Figure 2. Bus Timing in Extended Mode
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UCD90120
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DEVICE INFORMATION
UCD90120 PIN ASSIGNMENT
V33FB
V33A
BPCAP
V33D
V33DIO1
V33DIO2
7 44 45 46 47 58
1
MON1
TRCK
10
2
MON2
TCK/GPIO19
36
3
MON3
TDO/GPIO20
37
4
MON4
TDI/GPIO21
38
5
MON5
TMS/GPIO22
39
6
MON6
nTRST
40
59
MON7
62
MON8
GPIO1
11
63
MON9
GPIO2
12
50
MON10
GPIO3
13
52
MON11
GPIO4
14
54
MON12
GPIO13
25
56
MON13
GPIO14
29
UCD90120
GPIO15
30
15
PMBUS_CLK
GPIO16
33
16
PMBUS_DATA
GPIO17
34
27
PMBUS_ALERT
GPIO18
35
28
PMBUS_CNTRL
61
PMBUS_ADDR0
FPWM1/GPIO5
17
60
PMBUS_ADDR1
FPWM2/GPIO6
18
FPWM3/GPIO7
19
20
31
PWM1/GPI1
FPWM4/GPIO8
32
PWM2/GPI2
FPWM5/GPIO9
21
24
NC1
53
NC2
nRESET
9
55
NC3
57
NC4
AVSS3
FPWM8/GPIO12
51
AVSS1
23
AVSS2
FPWM7/GPIO11
DVSS3
FPWM6/GPIO10
PWM4/GPI4
DVSS2
PWM3/GPI3
41
DVSS1
42
22
8 26 43 48 49 64
PIN FUNCTIONS
PIN NAME
PIN NO.
I/O TYPE
DESCRIPTION
ANALOG MONITOR INPUTS
MON1
1
I
Analog Input (0 V–2.5 V)
MON2
2
I
Analog Input (0 V–2.5 V)
MON3
3
I
Analog Input (0 V–2.5 V)
MON4
4
I
Analog Input (0 V–2.5 V)
MON5
5
I
Analog Input (0 V–2.5 V)
MON6
6
I
Analog Input (0 V–2.5 V)
6
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PIN FUNCTIONS (continued)
PIN NAME
PIN NO.
I/O TYPE
DESCRIPTION
MON7
59
I
Analog Input (0 V–2.5 V)
MON8
62
I
Analog Input (0 V–2.5 V)
MON9
63
I
Analog Input (0 V–2.5 V)
MON10
50
I
Analog Input (0.2 V – 2.5 V)
MON11
52
I
Analog Input (0.2 V – 2.5 V)
MON12
54
I
Analog Input (0.2 V – 2.5 V)
MON13
56
I
Analog Input (0.2 V – 2.5 V)
GPIO1
11
I/O
General purpose discrete I/O
GPIO2
12
I/O
General purpose discrete I/O
GPIO3
13
I/O
General purpose discrete I/O
GPIO4
14
I/O
General purpose discrete I/O
GPIO13
25
I/O
General purpose discrete I/O
GPIO14
29
I/O
General purpose discrete I/O
GPIO15
30
I/O
General purpose discrete I/O
GPIO16
33
I/O
General purpose discrete I/O
GPIO17
34
I/O
General purpose discrete I/O
GPIO18
35
I/O
General purpose discrete I/O
FPWM1/GPIO5
17
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6
18
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7
19
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8
20
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9
21
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10
22
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11
23
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12
24
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1
31
I/PWM
Fixed 10 kHz PWM output or GPI
PWM2/GPI2
32
I/PWM
Fixed 1 kHz PWM output or GPI
PWM3/GPI3
42
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM4/GPI4
41
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
GPIO
PWM OUTPUTS
PMBus COMM INTERFACE
PMBUS_CLK
15
I/O
PMBus Clock (Must have pull-up to 3.3 V)
PMBUS_DATA
16
I/O
PMBus Data (Must have pull-up to 3.3 V)
PMBALERT#
27
O
PMBus Alert, Active Low, Open Drain Output (Must have pull-up to 3.3V)
PMBUS_CNTRL
28
I
PMBus Control
PMBUS_ADDR0
61
I
PMBus analog address input. Least significant address bit.
PMBUS_ADDR1
60
I
PMBus analog address input. Most significant address bit.
TRCK
10
O
Test return clock
TCK/GPIO19
36
I/O
Test clock or GPIO
TDO/GPIO20
37
I/O
Test data out or GPIO
TDI/GPIO21
38
I/O
Test data in (tie to Vdd with 10k resistor) or GPIO
TMS/GPIO22
39
I/O
Test mode select (tie to Vdd with 10k resistor) or GPIO
nTRST
40
I
JTAG
Test reset – tie to ground with 10k resistor
INPUT POWER AND GROUNDS
nRESET
9
Active low device reset input. Hold low for at least 2 µs to reset the device
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PIN FUNCTIONS (continued)
PIN NAME
PIN NO.
I/O TYPE
DESCRIPTION
V33FB
58
3.3V Linear Regulator Feedback connection
V33A
46
Analog 3.3 V supply
V33D
45
Digital Core 3.3V supply
V33DIO1
7
Digital I/O 3.3V supply
V33DIO2
44
Digital I/O 3.3V supply
BPCap
47
1.8V Bypass Capacitor – tie 0.1µF cap to analog ground
AVSS1
49
Analog Ground
AVSS2
48
Analog Ground
AVSS3
64
Analog Ground
DVSS1
8
Digital Ground
DVSS2
26
Digital Ground
DVSS3
43
Digital Ground
QFP Ground Pad
NA
PowerPAD – Tie to ground plane
FUNCTIONAL DESCRIPTION
TI FUSION GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
Graphical User Interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip non-volatile memory, and observe system status (voltage, temperature, etc). Fusion
is referenced throughout the datasheet and many sections include screenshots.
THEORY OF OPERATION
Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can
have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are
typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD90120 can
sequence supply voltages to prevent malfunctions, intermittent operation or device damage caused by improper
power-up or power-down. Appropriate handling of under- and over-voltage faults, over-current faults and
over-temperature faults can extend system life and improve long term reliability. The UCD90120 stores power
supply faults to on-chip non-volatile flash memory for aid in system failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, the system is operated at the minimum and maximum expected ambient temperature and with each
power supply set to the minimum and maximum output voltage, commonly referred to as margining. The
UCD90120 can be used to implement accurate closed-loop margining of up to 10 power supplies.
The UCD90120 12-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion
GUI provides a powerful but simple interface for configuring sequencing solutions for systems with between one
and 12 power supplies using 13 analog voltage monitor inputs, 4 GPIs and 22 highly configurable GPIOs. A rail
can include voltage, temperature, current, a power supply enable and a margining output. At least one must be
included in a rail definition. Once the user has defined how the power supply rails should operate in a particular
system, analog input pins and GPIOs can be selected to monitor and enable each supply (Figure 3).
8
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Figure 3. Fusion Pin Assignment Tab
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 4):
• Nominal operating voltage (Vout)
• Under-voltage (UV) and over-voltage (OV) warning and fault limits
• Margin Low and Margin High values
• Power Good On and Power Good Off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails that have to achieve Power Good or Input pins that must be at a defined logic state before a Rail is
enabled (Rail and Input Pin Dependencies)
• Turn On and Turn Off Delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
• Other Rails to turn off in case of a fault on a Rail (Fault Shutdown Slaves)
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Figure 4. Fusion Vout Config Tab
The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage
of a Rail and also update all of the other limits associated with that rail according to the percentages shown to
the right of each entry.
The plot in the upper left section of Figure 4 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the Turn On and Turn Off Delay times, the Power Good On and
Power Good Off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD90120 responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence-off using Turn Off Delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
10
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Figure 5. Fusion Other Config Tab for Fault Responses
Fault responses, along with a number of other parameters including user-specific Manufacturing Info and
external scaling and offset values, are selected in the Fusion Other Config tab. Once the configuration satisfies
the user requirements, it can be written to device SRAM if Fusion is connected to a UCD90120 using I2C/PMBus.
SRAM contents can then be stored to data flash memory so that the configuration remains in the device after a
reset or power cycle.
The Fusion Monitor page has a number of options, including a Device Dashboard and a System Dashboard, for
viewing and controlling device and system status in real time.
Figure 6. Fusion Monitor Page with Device Dashboard and System Dashboard
The UCD90120 also has status registers for each Rail and the capability to log faults to flash memory for use in
system troubleshooting. This is very helpful in the case of a power supply or system failure. The status registers
(Figure 7) and the fault log (Figure 8) are available in Fusion. Please refer to the UCD90120 PMBus Command
Reference and the PMBus_Specification_Part_II_Rev_1-1_20070205 for detailed descriptions of each status
register and supported PMBus commands.
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Figure 7. Fusion Rail Status Register
12
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Figure 8. Fusion Flash error Log (Logged Faults)
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TRCK
GPIO19/TCK
JTAG
MON1
MON2
.
.
.
.
MON13
Analog
Inputs
(13)
Internal
Temp
Sense
M
U
X
12-bit
SAR ADC
200ksps
Glitch MON1 – MON6
Filter
Internal
2.5Vref
0.5%
User Data
Fault Logging
MON1 – MON13
Monitoring
Sequence-ON/
Sequence-OFF
Configuration
ENx
Assert/
Deassert
Rail
Dependencies
GPIO1
GPIOs
Scaling & Unit
Conversion
Amps, °C, RPM
PMBUS_CLK
PMBALERT#
GPIO21/TDI
GPIO22/TMS
FLASH Memory
PMBUS_DATA
GPIO20/TDO
Fast Digital
Comparators
ENx
1-13
OR
GPIO2
.
.
.
GPIOx
GPI/GPIO
Dependencies
PMBus
PMBUS_CNTRL
PMBUS_ADDR0
GPIO
5-12
14,15
GPO/ENx
Control
Config
PMBUS_ADDR1
FPWM1/GPIO5
or
PWM1/GPI1
PWM2/GPI2
Margining/
Trim
Algorithm
PWM3/GPI3
PWMs
FPWM
1-8
and
Margin
Control
OR
FPWM2/GPIO6
.
.
.
.
FPWM8/GPIO12
PWM4/GPI4
SEQUENCING ENGINE
Figure 9. Detailed Block Diagram
POWER SUPPLY SEQUENCING
The UCD90120 can control the turn-on and turn-off sequencing of up to 12 voltage rails by using a GPIO to set a
power supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.
The Auto Enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
within regulation when the measured voltage for that rail crosses the Power Good On (POWER_GOOD_ON (1))
limit. The rail is still in regulation until the voltage drops below Power Good Off (POWER_GOOD_OFF).
(1)
14
In this document configuration parameters such as Power Good On are referred to using Fusion GUI names. The PMBus Command
Reference name is shown in parentheses (POWER_GOOD_ON) the first time the parameter appears.
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Turn-on Sequencing
The following sequence-on options are supported for each rail:
PMBUS_CNTRL PIN
TON_DELAY[1]
RAIL 1 EN
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
RAIL 2 EN
TOFF_DELAY[1]
POWER_GOOD_OFF[1]
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
TON_MAX_FAULT _LIMIT[2]
Rail 1 and Rail 2
are both
sequenced “ON”
and “OFF” by the
PMBUS_CNTRL
pin only
Rail 2 has Rail 1
as an “ON”
dependency
TOFF_MAX_WARN_LIMIT[2]
Figure 10. Sequence-on and Sequence-off Timing
•
•
•
•
•
•
Monitor only – do not sequence-on
Fixed delay time after a PMBus OPERATION command to turn on
Fixed delay time after assertion of the PMBUS_CNTRL pin
Fixed time after one or a group of parent rails achieves regulation
Fixed time after a designated GPI has reached a user-specified state
Any combination of the previous options
The maximum TON_DELAY time is 3276ms.
Turn-off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only – do not sequence-off
• Fixed delay time after a PMBus OPERATION command to turn off
• Fixed delay time after deassertion of the PMBUS_CNTRL pin
• Fixed delay time in response to an Under Voltage, Over Voltage, Under Current, Over Current, Under
Temperature, Over Temperature or Max Turn On fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a Fault Shutdown Slave to the faulted
rail
• Fixed delay time in response to a GPIO reaching a user-specified state
The maximum TOFF_DELAY time is 3276ms.
Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options described above, the time between when a rail is
enabled and when the monitored rail voltage must reach its Power Good On setting can be configured using Max
Turn On (TON_MAX_FAULT_LIMIT). Max Turn On can be set in 1ms increments. A value of 0ms means that
there is No Limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to user-defined delay times. A
sequenced shutdown is configured by selecting appropriate Turn Off Delay (TOFF_DELAY) times for each rail.
The Turn Off Delay times begin when the PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION
command is used to give a Soft Stop command, or when a fault occurs on a rail that has other rails set as Fault
Shutdown Slaves.
Shut-downs on one rail can initiate shut-downs of other rails or controllers. In systems with multiple UCD90120’s,
it is possible for each controller to be both a master and a slave to another controller.
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VOLTAGE MONITORING
Up to 13 voltages can be monitored using the analog input pins. The input voltage range is 0V–2.5V for MON
pins 1-6, 59, 62 and 63. Pins 50, 52, 54 and 56 can measure down to 0.2V. Any voltage between 0V and 0.2V
on these pins will read as 0.2V. External resistors can be used to attenuate voltages higher than 2.5V.
The ADC operates continuously, requiring 3.89µs to convert a single analog input and 54.5µs to convert all 14 of
the analog inputs, including the on-board temperature sensor. Each rail is sampled by the sequencing and
monitoring algorithm every 200µs. The maximum source impedance of any sampled voltage should be less than
4kΩ. The source impedance limit is particularly important when a resistor divider network is used to lower the
voltage applied to the analog input pins.
MON pins selected for Rail 1 through Rail 6 have optional digital hardware comparators, which can be used to
achieve faster fault responses. Each hardware comparator has two thresholds (one UV and one OV) as opposed
to four software thresholds. The hardware comparators respond to UV or OV conditions in about 80µs and can
be used to disable rails or assert GPOs. The only fault response available for the hardware comparators is to
shutdown immediately.
An internal 2.5V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to Table 1.
Table 1. Voltage Range and Resolution
VOLTAGE RANGE
(Volts)
RESOLUTION
(millivolts)
0
127.99805
1.95313
0
63.99902
0.97656
0
31.99951
0.48828
0
15.99976
0.24414
0
7.99988
0.12207
0
3.99994
0.06104
0
1.99997
0.03052
0
0.99998
0.01526
Although the monitor results can be reported with a resolution of about 15µV, the real conversion resolution of
610µV is fixed by the 2.5V reference and the 12-bit ADC.
The MON pins can directly measure voltages but each input can be defined as a voltage, current or temperature.
A single rail can include all three measurement types, each monitored on separate MON pins. If a rail has both
voltage and current assigned to it, then power can be calculated and reported for the rail. Digital filtering applied
to each MON input depends on the type of signal. Voltage inputs have no filtering. Current inputs have a
low-pass filter with a time constant of about 1 second. Temperature inputs have a low-pass filter with a time
constant of about 12.4 seconds.
CURRENT MONITORING
Current can be monitored using the analog inputs. External circuitry must be used in order to first convert the
current to a voltage within the range of the UCD90120 MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding average digital filter
with a time constant of approximately 1 second. The filter reduces the probability of false fault detections, and
introduces a small delay to the current reading. If a rail is defined with a voltage monitor and a current monitor,
then monitoring for under-current warnings begins once the rail voltage reaches POWER_GOOD_ON. If the rail
does not have a voltage monitor, then current monitoring will begin after TON_DELAY.
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The device supports multiple PMBus commands related to current, including READ_IOUT which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT which sets the over current fault limit;
IOUT_OC_WARN_LIMIT which sets the over current warning limit; and IOUT_UC_FAULT_LIMIT which sets the
under current fault limit. The UCD90120 PMBus Command Reference contains a detailed description of how
current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0V at the MON pin. The combination of these PMBus
commands allows current to be reported in Amps.
TEMPERATURE MONITORING AND INTERNAL TEMPERATURE SENSOR
Temperature can be monitored using the analog inputs. External circuitry must be used in order to first convert
the temperature to a voltage within the range of the UCD90120 MONx input being used.
If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter with
a time constant of approximately 12.4 seconds. The filter reduces the probability of false fault detections, and
introduces a small delay to the temperature reading. The internal device temperature is measured using a silicon
diode sensor with an accuracy of ±5°C and is also monitored using the ADC. Temperature monitoring begins
immediately after reset and initialization.
The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1
which reads the internal temperature; READ_TEMPERATURE_2 which reads external temperatures; and
OT_FAULT_LIMIT which sets the over temperature fault limit. The UCD90120 PMBus Command Reference
contains a detailed description of how temperature fault responses are implemented using PMBus commands.
TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature
sensor and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the
user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0V at the MON pin. The
combination of these PMBus commands allows temperature to be reported in degrees Celsius.
FAULT RESPONSES AND ALARM PROCESSING
Monitored rails have a software window comparator with two programmable warning levels (UV and OV) and two
programmable fault levels (UV and OV). When any monitored voltage goes outside of the warning or fault
windows, or when a current, temperature or any other recognized faults occurs, the PMBALERT# pin is asserted
immediately and the appropriate bits are set in the PMBus status registers (Figure 9). Detailed descriptions of the
status
registers
are
provided
in
the
UCD90120
PMBus
Command
Referenceand
the
PMBus_Specification_Part_II_Rev_1-1_20070205.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 51ms with 200µs resolution. A glitch filter for an input defined as a current or
temperature can be between 0 and 25.5 seconds with 100ms resolution. The longer time constants are due to
the fixed low-pass digital filters associated with current and temperature inputs.
Fault response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
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PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT _LIMIT
RAIL 1 VOLTAGE
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
TON_DELAY[2]
RAIL 2 EN
MAX_GLITCH_TIME
TOFF_DELAY[1]
MAX_GLITCH_TIME
TOFF_DELAY[2]
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Figure 11. Sequencing and Fault Response Timing
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
PMBUS_CNTRL PIN
TIME BETWEEN
RESTARTS
RAIL 1 EN
TON_DELAY[1]
POWER_GOOD_ON[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT _LIMIT[1]
TON_MAX_FAULT _LIMIT[1]
TON_DELAY[2]
RAIL 2 EN
RAIL 2 VOLTAGE
Figure 12. Max Turn On Fault
The configurable fault limits are:
Max Turn On fault– Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the
configured time
Under voltage warning– Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
Under voltage fault – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
Over voltage warning – Flagged if a rail exceeds the specified OV warning limit at any time during startup or
operation
Over voltage fault– Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation
Max Turn Off fault– Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal rail
voltage within the configured time.
Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault
occurs. If a warning occurs, the following takes place:
Warning actions
— Immediately assert the PMBALERT# pin
— Status bit gets flagged
— Assert a GPIO pin (optional)
— Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault responses
— Continue Without Interruption: Flag the fault and take no action
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Shut Down Immediately: Shut down the faulted rail immediately and Restart according to the rail
configuration
— Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are
configured. If the rail does not come back, schedule the shutdown of this rail and all fault
shutdown slaves. All selected rails, including the faulty rail, are sequenced-off according to their
T_OFF_DELAY times. If Do Not Restart is selected, then sequence off all selected rails when the
fault is detected.
Restart
— Do Not Restart: Do not attempt to Restart a faulted rail after it has been shut down
— Restart Up To N Times: Attempt to Restart a faulted rail up to 14 times after it has been shut
down. The time between restarts is measured between when the rail enable pin is deasserted
(after any glitch filtering and Turn Off Delay times, if configured to observe them) and then
reasserted. It can be set between 0 and 1275ms in 5ms increments.
— Restart Continuously: Same as Restart Up To N Times except that the device continues to
Restart until the fault goes away, it is commanded off by the specified combination of PMBus
OPERATION command and PMBUS_CNTRL pin status, or power is removed from the device.
— Shut Down Rails and Sequence On: Shut down selected rails immediately or after Continue
Operation time is reached and then sequence-on those rails using Turn On Delay times
SHUT DOWN ALL RAILS AND SEQUENCE ON
In response to a fault, the UCD90120 can be configured to turn off a set of rails and then sequence them back
on. To sequence all rails in the system, then all rails must be selected as Fault Shutdown Slaves of the faulted
rail. If the faulted rail is set to Stop Immediately or Stop With Delay, then the rails designated as Fault Shutdown
Slaves behave the same way. Shut Down All Rails and Sequence On will not be performed until retries are
exhausted for a given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the re-sequencing operation if this occurs. After the faulted rail
and Fault Shutdown Slaves sequence off, the UCD90120 will wait for a programmable delay time between 0 and
1275ms in increments of 5ms and then sequence on the faulted rail and Fault Shutdown Slaves according to the
start-up sequence configuration. This will be repeated until the faulted rail and Fault Shutdown Slaves
successfully achieve regulation or for a user-selected 1, 2, 3 or 4 times. If the re-sequence operation is
successful, the re-sequence counter will be reset if all of the rails that were re-sequenced maintain normal
operation for one second.
Once Shut Down All Rails and Sequence On begins, any faults on the Fault Shutdown Slave rails will be ignored.
If there are two or more simultaneous faults with different Fault Shutdown Slaves the more conservative action is
taken. For example, if a set of rails is already on its second re-sequence, and the device is configured to
re-sequence three times, and another set of rails enters the re-sequence state, that second set of rails will only
be re-sequenced once. Another example – if one set of rails is waiting on all of its rails to shutdown so that it can
resequence, and another set of rails enters the re-sequence state, the device will now wait for all rails from both
sets to shutdown before re-sequencing.
GPIOs
The UCD90120 has 22 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3V or ground.
There are an additional four pins that can be used as either inputs or PWM outputs but not as GPOs. Table 2
lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system level functions such as
external interrupts, power goods, resets, or cascading of multiple devices. GPOs can be sequenced up or down
by configuring a rail without a MON pin but with a GPIO set as an Enable.
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Table 2. GPIO Pin Configuration Options
PIN NAME
PIN#
RAIL EN
(12 MAX)
GPI
(8 MAX)
GPO
(12 MAX)
PWM OUT
(12 MAX)
MARGIN PWM
(12 MAX)
FPWM1/GPIO5
17
X
X
X
X
X
FPWM2/GPIO6
18
X
X
X
X
X
FPWM3/GPIO7
19
X
X
X
X
X
FPWM4/GPIO8
20
X
X
X
X
X
FPWM5/GPIO9
21
X
X
X
X
X
FPWM6/GPIO10
22
X
X
X
X
X
FPWM7/GPIO11
23
X
X
X
X
X
FPWM8/GPIO12
24
X
X
X
X
X
GPI1/PWM1
31
X
X
X
GPI2/PWM2
32
X
X
X
GPI3/PWM3
42
X
X
X
GPI4/PWM4
41
X
X
X
GPIO1
11
X
X
X
GPIO2
12
X
X
X
GPIO3
13
X
X
X
GPIO4
14
X
X
X
GPIO13
25
X
X
X
GPIO14
29
X
X
X
GPIO15
30
X
X
X
GPIO16
33
X
X
X
GPIO17
34
X
X
X
GPIO18
35
X
X
X
TCK/GPIO19
36
X
X
X
TDO/GPIO20
37
X
X
X
TDI/GPIO21
38
X
X
X
TMS/GPIO22
39
X
X
X
20
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GPI Special Functions
Figure 13 lists and describes five special input functions that GPIs can be used for. There can be no more than
one pin assigned to each of these functions.
Figure 13. GPI Configuration – Special Input Functions
PWM Outputs
Pins 17-24 can be configured as FPWMs. The frequency range is 15.259 kHz to 125 MHz. FPWMs can be
configured as Closed Loop Margining outputs or general purpose PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 – same frequency
• FPWM3 and FPWM4 – same frequency
• FPWM5 and FPWM6 – same frequency
• FPWM7 and FPWM8 – same frequency
Pins 31, 32, 41 and 42 can be used as GPIs or PWM outputs.
If
•
•
•
configured as PWM outputs, then limitations apply:
PWM1 has a fixed frequency of 10 kHz
PWM2 has a fixed frequency of 1 kHz
PWM3 and PWM4 frequencies can be 0.93 Hz to 7.8125 MHz.
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Power Supply Enables
Each GPIO can be configured as a Rail Enable pin with either active low or active high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3V or ground. During reset, the
GPIO pins will be high impedance except for the FPWM/GPIO pins 17-24, which will be driven low. External
pulldown or pullup resistors can be tied to the Enable pins to hold the power supplies off during reset. The
UCD90120 can support a maximum of 12 Enable pins.
Cascading Multiple Devices
A GPIO pin can be used to coordinate multiple controllers by using it as a Power Good output from one device
and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship between
multiple devices. During startup, the slave controllers will initiate their start sequences after the master has
completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the
master starts to sequence-off it will send the shut-down signal to its slaves.
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
The PMBus specification implies that the Power Good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD90120 allows GPIOs to be configured to respond to a desired
subset of Power Goods.
GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to four AND’s all OR’d
together (Figure 14). Inputs to the logic blocks can include GPIs and rail status flags. One rail status type is
selectable as an input for each AND gate in a Boolean block. For a selected rail status, the status flags of all
active rails can be included as inputs to the AND gate. “_LATCH” rails status types stay asserted until cleared by
a MFR PMBus command or by a specially configured GPI pin. The different rail status types are shown in
Figure 16. Refer to the UCD90120 PMBus Command Reference for complete definitions of rail status types.
GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
_GPI(0)
1
GPI(0)
_GPI (1:7)
_STATUS(0:11)
Sub - block repeated for each of GPI(1:7)
0
There is one STATUS_TYPE_SELECT for
each of the four AND gates in a boolean
block. See Status Types on next slide.
1
STATUS_TYPE_SELECT(x,0)
Status Type 1
1
13
STATUS(0)
_GPI (0:7)
STATUS(1)
_STATUS(0:12)
1
13
Status Type 35
GPO_INVERSE(x)
GPOx
13
_GPI (0:7)
Sub - block repeated for each of STATUS(0:11)
2
_STATUS(0:12)
STATUS_INVERSE(12)
STATUS(12)
STATUS_ENABLE(12)
1
_STATUS(12)
_GPI (0:7)
3
_STATUS(0:12)
Figure 14. Boolean Logic Combinations
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Figure 15. Fusion Boolean Logic Builder
1.
2.
3.
POWER_GOOD(0:12)
VOUT_OV_FAULT(0:12)
VOUT_OV_FAULT_LATCH(0:12)
20.
21.
22.
TEMP_OT_FAULT(0:12)
TEMP_OT_FAULT_LATCH(0:12)
TEMP_OT_WARN(0:12)
4.
5.
6.
VOUT_OV_WARN(0:12)
VOUT_OV_WARN_LATCH(0:12)
VOUT_UV_WARN(0:12)
23.
24.
25.
TEMP_OT_WARN_LATCH(0:12)
INPUT_VIN_OV_FAULT(0:12)
INPUT_VIN_OV_FAULT_LATCH(0:12)
7.
8.
VOUT_UV_WARN_LATCH(0:12)
VOUT_UV_FAULT(0:12)
26.
27.
INPUT_VIN_OV_WARN(0:12)
INPUT_VIN_OV_WARN_LATCH(0:12)
9.
10.
VOUT_UV_FAULT_LATCH(0:12)
VOUT_TON_FAULT(0:12)
28.
29.
INPUT_VIN_UV_WARN(0:12)
INPUT_VIN_UV_WARN_LATCH(0:12)
11.
12.
13.
14.
15.
16.
17.
18.
19.
VOUT_TON_FAULT_LATCH(0:12)
VOUT_TOFF_WARN(0:12)
VOUT_TOFF_WARN_LATCH(0:12)
IOUT_OC_FAULT(0:12)
IOUT_OC_FAULT_LATCH(0:12)
IOUT_OC_WARN(0:12)
IOUT_OC_WARN_LATCH(0:12)
IOUT_UC_FAULT(0:12)
IOUT_UC_FAULT_LATCH(0:12)
30.
31.
32.
33.
INPUT_VIN_UV_FAULT(0:12)
INPUT_VIN_UV_FAULT_LATCH(0:12)
MFR_SEQ_TIMEOUT(0:12)
MFR_SEQ_TIMEOUT_LATCH(0:12)
Figure 16. Rail status types
MARGINING
Margining is used in product validation testing to verify that the complete system works properly over all
conditions including minimum and maximum power supply voltages, load range, ambient temperature range and
other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION command
or by configuring two GPIO pins as Margin EN and Margin UP/DOWN inputs. The MARGIN_CONFIG command
in the UCD90120 PMBus Command Reference describes different available margining options including ignoring
faults while margining and using closed-loop margining to trim the power supply output voltage one time at power
up.
Open-loop margining is done by connecting a power supply feedback node to ground through one resistor and to
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VCC or the power supply input voltage through another resistor. The power supply regulation loop responds to
change in feedback node voltage by increasing or decreasing the power supply output voltage to return
feedback voltage to the original value. The voltage change is determined by the fixed resistor values and
voltage at VCC and ground. Two GPIO pins must be configured as outputs for connecting resistors from
feedback node of each power supply to VCC or ground.
the
the
the
the
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power supply feedback node through a resistor. The power supply output voltage is monitored
and the margining voltage is controlled by adjusting the PWM duty cycle until the power supply output voltage
reaches the Margin Low and Margin High voltages set by the user.
SYSTEM RESET SIGNAL
The UCD90120 can generate a programmable System Reset pulse as part of Sequence On. The pulse is
created by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails
reach their respective POWER_GOOD_ON levels plus a programmable delay time. The System Reset pulse
width can be programmed as shown in Table 3.
Table 3. System Reset Pulse
Width
Pulse Width
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 sec
2.05 sec
4.10 sec
8.19 sec
16.38 sec
32.8 sec
WATCH DOG TIMER
A GPI and GPO can be configured as a Watch Dog Timer (WDT). The WDT can be independent of power
supply sequencing or tied to a GPIO configured to provide a System Reset signal. The WDT can be reset by
toggling a Watchdog Input (WDI) pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.
The WDT can be active immediately at power up or set to wait while the system initializes. Table 4 lists the
programmable wait times before the initial timeout sequence begins.
Table 4. WDT Initial Wait Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
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Table 4. WDT Initial Wait
Time (continued)
WDT INITIAL WAIT TIME
800 ms
1.6 sec
3.2 sec
6.4 sec
12.8 sec
25.6 sec
51.2 sec
102 sec
205 sec
410 sec
819 sec
1638 sec
The watchdog timeout is programmable from 0 to 2.55s with a 10ms step size. If the WDT times out, the
UCD90120 can assert a GPIO pin configured as WDO that is separate from a GPIO defined as System Reset
pin or it can generate a System Reset pulse. After a timeout, the WDT is restarted by toggling the WDI pin or by
writing to SYSTEM_WATCHDOG_RESET over I2C.
WDI
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