UCD90124
www.ti.com
SLVSA29B – NOVEMBER 2009 – REVISED SEPTEMBER 2010
12-Rail Sequencer and System Health Monitor With Fan Control
Check for Samples: UCD90124
FEATURES
1
•
•
•
•
•
•
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APPLICATIONS
DESCRIPTION
The UCD90124 is a 12-rail PMBus/I2C addressable
power-supply
sequencer
and
system-health
monitor. The device integrates a 12-bit ADC for
monitoring up to 13 power-supply voltage, current, or
temperature inputs. Twenty-six GPIO pins can be
used for power supply enables, power-on reset
signals, external interrupts, cascading, or other
system functions. Twelve of these pins offer PWM
functionality. Using these pins, the UCD90124 offers
support
for
fan
control,
margining,
and
general-purpose PWM functions.
Fan-control signals can be sent using PMBus
commands or generated from one of two built-in
fan-control algorithms. PWM outputs combined with
temperature and fan-speed measurements provide a
complete fan-control solution for up to four
independent fans.
The TI Fusion Digital Power™ designer software is
provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive
interface for configuring, storing, and monitoring all
system operating parameters.
12V
12V OUT
3.3V_UCD
I12V
TEMP IC
TEMP12V
INA196
5.1V
12V OUT
V33A
V33D
•
Monitor and Sequence 12 Voltage Rails
– All Rails Sampled Every 400 ms
– 12-bit ADC With 2.5-V, 0.5% Internal VREF
– Sequence Based on Time, Rail and Pin
Dependencies
– Four Programmable Undervoltage and
Overvoltage Thresholds per Monitor
Fan Control and Monitoring
– Supports Four Fans With Five User-Defined
Speed-vs-Temperature Setpoints
– Supports Two-, Three-, and Four-Wire Fans
Nonvolatile Error and Peak-Value Logging per
Monitor (up to 10 Fault Detail Entries)
Closed-Loop Margining for 10 Rails
– Margin Output Adjusts Rail Voltage to
Match User-Defined Margin Thresholds
Programmable Watchdog Timer and System
Reset
Flexible Digital I/O Configuration
Multiphase PWM Clock Generator
– Clock Frequencies From 15.259 kHz to 125
MHz
– Capability to Configure Independent Clock
Outputs for Synchronizing Switch-Mode
Power Supplies
Internal Temperature Sensor
JTAG and I2C/SMBus/ PMBus™ Interfaces
V33FB
•
2
GPIO
VIN
VMON
VMON
1.8V OUT
VMON
0.8V OUT
VMON
I0.8V
VMON
TEMP0.8V
VMON
3.3V OUT
VOUT
/EN
GPIO
3.3V OUT
DC-DC 1
VFB
VIN
/EN
GPIO
VOUT
1.8V OUT
LDO1
I12V
VMON
TEMP12V
VMON
TEMP IC
•
•
•
•
•
Industrial / ATE
Telecommunications and Networking
Equipment
Servers and Storage Systems
Embedded Computing
Any System Requiring Sequencing and
Monitoring of Multiple Power Rails
VIN
UCD90124
WDI from main
processor
GPIO
WDO
GPIO
POWER_GOOD
GPIO
TEMP0.8V
0.8V OUT
VOUT
/EN
GPIO
DC-DC 2
VFB
INA196
PWM
WARN_OC_0.8V_
OR_12V
GPIO
SYSTEM RESET
GPIO
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO
2MHz
I0.8V
Vmarg
Closed Loop
Margining
4- wire Fan
12 V
12V
I2C/
PMBUS
JTAG
PWM
GPIO
25 kHz Fan PWM
Fan Tach
PWM
TACH
GND
DC Fan
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PMBus, Fusion Digital Power are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
UCD90124
SLVSA29B – NOVEMBER 2009 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
JTAG
Or
GPIO
Comparators
I2C/
PMBus
Internal
Temperature
Sensor
General Purpose I/O
(GPIO)
Rail Enables (12 max)
14
Digital Outputs (12 max)
6
Digital Inputs (8 max)
SEQUENCING ENGINE
Monitor
Inputs
13
Fan Tach Monitors (4 max)
PWM
Multi-phase PWM (8 max)
12-bit
ADC
(0.5% Int. Ref)
Fan Control (4 max)
FLASH Memory
User Data, Fault
and Peak Logging
BOOLEAN
Logic Builder
12
Margining Outputs (10 max)
GPIO Capability
64-pin QFN
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
Voltage applied at V33D to DVSS
–0.3 V to 3.8
V
Voltage applied at V33A to AVSS
–0.3 V to 3.8
V
Voltage applied at V33FB to AVSS
–0.3 V to 5.5
V
–0.3 V to (V33A +
0.3 V)
V
Voltage applied to any other pin
(2)
Storage temperature (Tstg)
ESD rating
(1)
(2)
2
–55 to 150
°C
Human-body model (HBM)
2.5
kV
Charged-device model (CDM)
750
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS
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SLVSA29B – NOVEMBER 2009 – REVISED SEPTEMBER 2010
THERMAL INFORMATION
UCD90124
THERMAL METRIC (1)
RGC
UNITS
64 PINS
Junction-to-ambient thermal resistance (2)
qJA
26.4
(3)
qJC(top)
Junction-to-case(top) thermal resistance
qJB
Junction-to-board thermal resistance
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
qJC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
21.2
(4)
1.7
(5)
Junction-to-case(bottom) thermal resistance
°C/W
0.7
(6)
8.8
(7)
1.7
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
Supply voltage during operation (V33D, V33DIO, V33A)
Operating free-air temperature range, TA
MIN
NOM
MAX
3
3.3
3.6
V
110
°C
125
°C
–40
Junction temperature, TJ
UNIT
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
SUPPLY CURRENT
IV33A
VV33A = 3.3 V
8
mA
IV33DIO
VV33DIO = 3.3 V
2
mA
VV33D = 3.3 V
40
mA
VV33D = 3.3 V, storing configuration parameters
in flash memory
50
mA
Supply current (1)
IV33D
IV33D
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
VV33
3.3-V linear regulator
VV33FB
3.3-V linear reg feedback
IV33FB
Series pass base drive
Beta
Series NPN pass device
Emitter of NPN transistor
3.25
VVIN = 12 V
3.3
3.35
4
4.6
10
V
V
mA
40
EXTERNALLY SUPPLIED 3.3V POWER
VV33D,
VV33DIO
Digital 3.3-V power
TA = 25°C
3
3.6
V
VV33A
Analog 3.3-V power
TA = 25°C
3
3.6
V
0
2.5
V
0.2
2.5
V
2.5
mV
ANALOG INPUTS (MON1–MON13)
VMON
Input voltage range
MON1–MON9
MON10–MON13
INL
ADC integral nonlinearity
Ilkg
Input leakage current
3 V applied to pin
–2.5
IOFFSET
Input offset current
1-kΩ source impedance
RIN
Input impedance
CIN
Input capacitance
tCONVERT
ADC sample period
14 voltages sampled, 3.89 msec/sample
VREF
ADC 2.5 V, internal reference
accuracy
0°C to 125°C
–5
MON1–MON9, ground reference
100
nA
5
mA
8
MON10–MON13, ground reference
0.5
MΩ
1.5
3
10
–40°C to 125°C
400
MΩ
pF
msec
–0.5
0.5
%
–1
1
%
9
11
mA
ANALOG INPUT (PMBUS_ADDRx, INTERNAL TEMP SENSE)
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage – open pin
PMBus_ADDR0, PMBus_ADDR1 open
VADDR_SHORT
Voltage – shorted pin
PMBus_ADDR0, PMBus_ADDR1 short to
ground
TInternal
Internal temperature-sense
accuracy
Over range from 0°C to 100°C
2.26
–5
V
0.124
V
5
°C
Dgnd +
0.25
V
DIGITAL INPUTS AND OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (2), V33DIO = 3 V
VOH
High-level output voltage
IOH = –6 mA (3), V33DIO = 3 V
VIH
High-level input voltage
V33DIO = 3 V
VIL
Low-level input voltage
V33DIO = 3.5 V
(1)
(2)
(3)
4
V33DIO
– 0.6V
2.1
V
3.6
V
1.4
V
Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
FAN CONTROL INPUTS AND OUTPUTS
FPWM1-8
TPWM_FREQ
FAN-PWM frequency
15.259
125000
PWM1
10
PWM2
1
PWM3-4
DUTYPWM
FAN-PWM duty cycle range
TachRANGE
FAN-TACH range
TachRES
FAN-TACH resolution
For 1 Tach pulse per revolution
tMIN
FAN-TACH minimum pulse width
Either positive or negarive polarity
For 1 Tach pulse per revolution. At 2, 3 or 4
pulse/rev, divide by the value
0.001
kHz
7800
0
100
%
30
300k
RPM
30
RPM
200
µs
MARGINING OUTPUTS
TPWM_FREQ
MARGINING-PWM frequency
DUTYPWM
MARGINING-PWM duty cycle range
FPWM1-8
PWM3-4
15.260
125000
0.001
7800
0
100
kHz
%
SYSTEM PERFORMANCE
VDDSlew
Minimum VDD slew rate
VDD slew rate between 2.3 V and 2.9 V
VRESET
Supply voltage at which device
comes out of reset
0.25
V/ms
For power-on reset (POR)
tRESET
Low-pulse duration needed at
RESET pin
To reset device during normal operation
f(PCLK)
Internal oscillator frequency
TA = 125°C, TA = 25°C
240
tretention
Retention of configuration
parameters
TJ = 25°C
100
Years
Write_Cycles
Number of nonvolatile erase/write
cycles
TJ = 25°C
20
K cycles
2.4
V
2
mS
250
260
MHz
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PMBus/SMBus/I2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus is shown below.
I2C/SMBus/PMBus TIMING REQUIREMENTS
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
FSMB
SMBus/PMBus operating frequency
Slave mode, SMBC 50% duty
cycle
FI2C
I2C operating frequency
Slave mode, SCL 50% duty cycle
t(BUF)
Bus free time between start and stop
t(HD:STA)
TYP
MAX
UNIT
10
400
kHz
10
400
kHz
4.7
ms
Hold time after (repeated) start
0.26
ms
t(SU:STA)
Repeated-start setup time
0.26
ms
t(SU:STO)
Stop setup time
0.26
ms
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
50
ns
Receive mode
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
t(HIGH)
Clock high period
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
tf
Clock/data fall time
tr
Clock/data rise time
(1)
(2)
(3)
(4)
(5)
See
(1)
35
ms
50
ms
(3)
25
ms
See
(4)
120
ns
See
(5)
120
ns
0.5
ms
0.26
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Fall time tf = 0.9 VDD to (VILMAX – 0.15)
Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15)
Figure 1. I2C/SMBus Timing Diagram
Start
Stop
TLOW:SEXT
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
PMB_Clk
Clk ACK
Clk ACK
PMB_Data
Figure 2. Bus Timing in Extended Mode
6
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SLVSA29B – NOVEMBER 2009 – REVISED SEPTEMBER 2010
DEVICE INFORMATION
UCD90124 PIN ASSIGNMENT
54
56
MON13
NC1
MON10
AVSS1
50
49
MON1
1
48
AVSS2
MON2
2
47
BPCAP
MON3
3
46
V33A
MON4
4
45
V33D
14
MON5
5
44
V33DIO2
25
MON6
6
43
DVSS3
29
7
42
GPIO14
V33DIO1
PWM 3/GPI3
30
DVSS1
8
GPIO15
GPIO13
MON12
MON11
GPIO4
51
MON11
NC2
52
52
13
MON12
12
GPIO3
53
GPIO2
MON10
NC3
MON9
50
54
63
UCD90124
MON13
MON8
55
11
62
56
GPIO1
MON7
V33FB
40
MON6
NC4
TRST
6
59
57
39
58
TMS/GPIO22
PMBUS_ADDR1
MON5
MON7
38
5
59
37
TDI/GPIO21
60
TDO/GPIO20
MON4
MON8
MON3
4
PMBUS_ADDR0
3
61
36
MON9
10
TCK/GPIO19
62
TRCK
MON2
AVSS3
MON1
63
1
2
64
V33FB
V33A
BPCAP
V33D
V33DIO2
V33DIO1
7 44 45 46 47 58
RESET
9
UCD90124
41
PWM4/GPI4
40
TRST
PWM3/GPI3
FPWM6/GPIO10
22
41
PWM4/GPI4
FPWM7/GPIO11
23
FPWM8/GPIO12
24
51
NC1
9
AVSS3
AVSS1
NC4
AVSS2
57
RESET
DVSS3
NC3
DVSS2
NC2
DVSS1
53
55
32
21
42
PWM2/GPI2
20
FPWM5/GPIO9
31
FPWM4/GPIO8
PWM2/GPI2
PWM1/GPI1
PWM1/GPI1
30
31
32
GPIO15
19
29
FPWM3/GPIO7
GPIO14
GPIO 16
18
28
33
FPWM2/GPIO6
PMBUS_CNTRL
16
PMBUS_ADDR1
27
GPIO 17
PMBUS _DATA
60
PMBUS_ALERT
34
26
15
25
GPIO 18
PMBUS _CLK
17
DVSS2
35
FPWM1/GPIO5
GPIO13
14
PMBUS_ADDR0
24
TCK/GPIO19
GPIO4
61
23
TDO/GPIO 20
36
FPWM7/GPIO11
37
13
FPWM8/GPIO12
12
GPIO3
22
GPIO2
PMBUS_CNTRL
21
35
PMBUS_ALERT
FPWM5/GPIO9
GPIO18
27
28
FPWM6/GPIO10
TDI/GPIO21
20
TMS/GPIO22
38
FWPM4/GPIO8
39
11
19
10
GPIO1
FPWM3/GPIO7
TRCK
34
18
33
GPIO17
17
GPIO16
PMBUS_DATA
FPWM2/GPIO6
PMBUS_CLK
16
FPWM1/GPIO5
15
8 26 43 48 49 64
Table 1. PIN FUNCTIONS
PIN NAME
PIN NO.
I/O TYPE
DESCRIPTION
ANALOG MONITOR INPUTS
MON1
1
I
Analog input (0 V–2.5 V)
MON2
2
I
Analog input (0 V–2.5 V)
MON3
3
I
Analog input (0 V–2.5 V)
MON4
4
I
Analog input (0 V–2.5 V)
MON5
5
I
Analog input (0 V–2.5 V)
MON6
6
I
Analog input (0 V–2.5 V)
MON7
59
I
Analog input (0 V–2.5 V)
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Table 1. PIN FUNCTIONS (continued)
PIN NAME
PIN NO.
I/O TYPE
MON8
62
I
DESCRIPTION
Analog input (0 V–2.5 V)
MON9
63
I
Analog input (0 V–2.5 V)
MON10
50
I
Analog input (0.2 V–2.5 V)
MON11
52
I
Analog input (0.2 V–2.5 V)
MON12
54
I
Analog input (0.2 V–2.5 V)
MON13
56
I
Analog input (0.2 V–2.5 V)
GPIO1
11
I/O
General-purpose discrete I/O
GPIO2
12
I/O
General-purpose discrete I/O
GPIO3
13
I/O
General-purpose discrete I/O
GPIO4
14
I/O
General-purpose discrete I/O
GPIO13
25
I/O
General-purpose discrete I/O
GPIO14
29
I/O
General-purpose discrete I/O
GPIO15
30
I/O
General-purpose discrete I/O
GPIO16
33
I/O
General-purpose discrete I/O
GPIO17
34
I/O
General-purpose discrete I/O
GPIO18
35
I/O
General-purpose discrete I/O
FPWM1/GPIO5
17
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6
18
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7
19
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8
20
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9
21
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10
22
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11
23
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12
24
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1
31
I/PWM
Fixed 10-kHz PWM output or GPI
PWM2/GPI2
32
I/PWM
Fixed 1-kHz PWM output or GPI
PWM3/GPI3
42
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM4/GPI4
41
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
GPIO
PWM OUTPUTS
PMBus COMM INTERFACE
PMBUS_CLK
15
I/O
PMBus clock (must have pullup to 3.3 V)
PMBUS_DATA
16
I/O
PMBus data (must have pullup to 3.3 V)
PMBALERT#
27
O
PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBUS_CNTRL
28
I
PMBus control
PMBUS_ADDR0
61
I
PMBus analog address input. Least-significant address bit
PMBUS_ADDR1
60
I
PMBus analog address input. Most-significant address bit
JTAG
TRCK
10
O
Test return clock
TCK/GPIO19
36
I/O
Test clock or GPIO
TDO/GPIO20
37
I/O
Test data out or GPIO
TDI/GPIO21
38
I/O
Test data in (tie to Vdd with 10-kΩ resistor) or GPIO
TMS/GPIO22
39
I/O
Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO
TRST
40
I
8
Test reset – tie to ground with 10-kΩ resistor
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Table 1. PIN FUNCTIONS (continued)
PIN NAME
PIN NO.
I/O TYPE
DESCRIPTION
INPUT POWER AND GROUNDS
RESET
9
Active-low device reset input. Hold low for at least 2 ms to reset the device.
V33FB
58
3.3-V linear regulator feedback connection
V33A
46
Analog 3.3-V supply
V33D
45
Digital core 3.3-V supply
V33DIO1
7
Digital I/O 3.3-V supply
V33DIO2
44
Digital I/O 3.3-V supply
BPCap
47
1.8-V bypass capacitor – tie 0.1-mF capacitor to analog ground.
AVSS1
49
Analog ground
AVSS2
48
Analog ground
AVSS3
64
Analog ground
DVSS1
8
Digital ground
DVSS2
26
Digital ground
DVSS3
43
Digital ground
QFP ground pad
NA
Thermal pad – tie to ground plane.
FUNCTIONAL DESCRIPTION
TI FUSION GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip nonvolatile memory, and observe system status (voltage, temperature, etc). Fusion is
referenced throughout the data sheet and many sections include screenshots.
PMBUS INTERFACE
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD90124 supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD90124, MFR_SPECIFIC commands are defined to configure or activate those
features. These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS
Command Reference (SLVU352).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007.
The specification is published by the Power Management Bus Implementers Forum and is available from
www.pmbus.org.
The UCD90124 is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The
firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.
The hardware can support either 100-kHz or 400-kHz PMBus operation.
THEORY OF OPERATION
Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can
have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are
typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD90124 can
sequence supply voltages to prevent malfunctions, intermittent operation, or device damage caused by improper
power up or power down. Appropriate handling of under- and overvoltage faults, overcurrent faults and
overtemperature faults can extend system life and improve long term reliability. The UCD90124 stores power
supply faults to on-chip nonvolatile flash memory for aid in system failure analysis.
Tach monitor inputs, PWM outputs and temperature measurements can be combined with a choice between two
built-in fan-control algorithms to provide a stand-alone fan controller for independent operation of up to four fans.
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System reliability can be improved through four-corner testing during system verification. During four-corner
testing, the system is operated at the minimum and maximum expected ambient temperature and with each
power supply set to the minimum and maximum output voltage, commonly referred to as margining. The
UCD90124 can be used to implement accurate closed-loop margining of up to 10 power supplies.
The UCD90124 12-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion
GUI provides a powerful but simple interface for configuring sequencing solutions for systems with between one
and 12 power supplies using 13 analog voltage-monitor inputs, four GPIs and 22 highly configurable GPIOs. A
rail can include voltage, temperature, current, a power-supply enable and a margining output. At least one must
be included in a rail definition. Once the user has defined how the power-supply rails should operate in a
particular system, analog input pins and GPIOs can be selected to monitor and enable each supply (Figure 3).
Figure 3. Fusion Pin-Assignment Tab
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 4):
• Nominal operating voltage (Vout)
• Undervoltage (UV) and overvoltage (OV) warning and fault limits
• Margin-low and margin-high values
• Power-good on and power-good off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails that must achieve power good, or input pins that must be at a defined logic state before a rail is enabled
(rail and input-pin sequence-on dependencies)
• Turn-on and turn-off delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
10
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Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
Figure 4. Fusion VOUT-Config Tab
The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage
of a rail and also update all of the other limits associated with that rail according to the percentages shown to the
right of each entry.
The plot in the upper left section of Figure 4 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turn-on and turn-off delay times, the power-good on and
power-good off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD90124 responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turn-off delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure funciton of Fusion
software. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion is
connected to a UCD90124 using an I2C/PMBus. SRAM contents can then be stored to data flash memory so that
the configuration remains in the device after a reset or power cycle.
The Fusion Monitor page has a number of options, including a device dashboard and a system dashboard, for
viewing and controlling device and system status.
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Figure 5. Fusion Monitor Page with Device Dashboard and System Dashboard
The UCD90124 also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers
(Figure 6) and the fault log (Figure 7) are available in Fusion. See the UCD90xxx Sequencer and System Health
Controller PMBus Command Reference and the PMBus Specification for detailed descriptions of each status
register and supported PMBus commands.
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Figure 6. Fusion Rail-Status Register
Figure 7. Fusion Flash-Error Log (Logged Faults)
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POWER-SUPPLY SEQUENCING
The UCD90124 can control the turn-on and turn-off sequencing of up to 12 voltage rails by using a GPIO to set a
power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON (1))
limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF).
(1)
14
In this document configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx Sequencer
and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first time the
parameter appears.
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Turn-on Sequencing
The following sequence-on options are supported for each rail:
• Monitor only – do not sequence-on
• Fixed delay time after a PMBus OPERATION command to turn on
• Fixed delay time after assertion of the PMBUS_CNTRL pin
• Fixed time after one or a group of parent rails achieves regulation
• Fixed time after a designated GPI has reached a user-specified state
• Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
POWER_GOOD_ON[1]
POWER_GOOD_OFF[1]
RAIL 1 VOLTAGE
TON_DELAY[2]
RAIL 2 EN
TOFF_DELAY[2]
RAIL 2 VOLTAGE
TON_MAX_FAULT _LIMIT[2]
Rail 1 and Rail 2
are both
sequenced “ON”
and “OFF” by the
PMBUS_CNTRL
pin only
Rail 2 has Rail 1
as an “ON”
dependency
TOFF_MAX_WARN_LIMIT[2]
Figure 8. Sequence-on and Sequence-off Timing
Turn-off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only – do not sequence-off
• Fixed delay time after a PMBus OPERATION command to turn off
• Fixed delay time after deassertion of the PMBUS_CNTRL pin
• Fixed delay time in response to an undervoltage, overvoltage, undercurrent, overcurrent, undertemperature,
overtemperature, or max turn-on fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
The maximum TOFF_DELAY time is 3276 ms.
Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to user-defined delay times. A
sequenced shutdown is configured by selecting the appropriate turn-off delay (TOFF_DELAY) times for each rail.
The turn-off delay times begin when the PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION
command is used to give a soft-stop command, or when a fault occurs on a rail that has other rails set as
fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD90124s, it
is possible for each controller to be both a master and a slave to another controller.
VOLTAGE MONITORING
Up to 13 voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for MON
pins 1–6, 59, 62 and 63. Pins 50, 52, 54, and 56 can measure down to 0.2 V. Any voltage between 0 V and 0.2
V on these pins is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.
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The ADC operates continuously, requiring 3.89 ms to convert a single analog input and 54.5 ms to convert all 14
of the analog inputs, including the onboard temperature sensor. Each rail is sampled by the sequencing and
monitoring algorithm every 400 ms. The maximum source impedance of any sampled voltage should be less than
4 kΩ. The source impedance limit is particularly important when a resistor-divider network is used to lower the
voltage applied to the analog input pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 ms (faster than 400 µs for the
ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware
comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to Table 2.
Table 2. Voltage Range and Resolution
VOLTAGE RANGE
(Volts)
RESOLUTION
(millivolts)
0 to 63.99805
1.95313
0 to 31.99902
0.97656
0 to 15.99951
0.48828
0 to 7.99976
0.24414
0 to 3.99988
0.12207
Although the monitor results can be reported with a resolution of about 15 mV, the real conversion resolution of
610 mV is fixed by the 2.5-V reference and the 12-bit ADC.
The MON pins can directly measure voltages, but each input can be defined as a voltage, current, or
temperature. A single rail can include all three measurement types, each monitored on separate MON pins. If a
rail has both voltage and current assigned to it, then power can be calculated and reported for the rail. Digital
filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering. Current and
temperature inputs have a low-pass filter.
CURRENT MONITORING
Current can be monitored using the analog inputs. External circuitry, see Figure 9, must be used in order to
convert the current to a voltage within the range of the UCD90124 MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.
The current for 1 rail is measured every 200µs. If the device is programmed to support 10 rails (independent of
current not being monitored at all rails), then each rail's current will get measured every 2ms. The current
calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of
false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage
monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches
POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after
TON_DELAY.
The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;
IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the
undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference
contains a detailed description of how current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus
commands allows current to be reported in amperes. The example below using the INA196 would require
programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
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UCD90124
MONx
VOUT
Vin+
AVSS1
Rsense
GND
Vin3.3V
Current Path
INA196
V+
Gain = 20V/V
Figure 9. Current Monitoring Circuit Example Using the INA196
REMOTE TEMPERATURE MONITORING AND INTERNAL TEMPERATURE SENSOR
The UCD90124 has support for internal and remote temperature sensing. The internal temperature sensor
requires no calibration and can report the device temperature via the PMBus interface. The remote temperature
sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is
used in the application such as a linear temperature sensor (LTS) connected to the analog inputs.
External circuitry must be used in order to convert the temperature to a voltage within the range of the
UCD90124 MONx input being used.
If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The
temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of
temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The
temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the
probability of false fault detections, and introduces a small delay to the temperature reading. The internal device
temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the
ADC. Temperature monitoring begins immediately after reset and initialization.
The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,
which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and
OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how
temperature-fault responses are implemented using PMBus commands.
TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature
sensor Figure 10and any amplifiers or attenuators between the temperature sensor and the MON pin to be
entered by the user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON
pin. The combination of these PMBus commands allows temperature to be reported in degrees Celsius.
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UCD90124
TMP20
MONx
VOUT
AVSS1
GND
3.3V
V+
Vout = -11.67mV/°C x T + 1.8583
at -40°C < T < 85°C
Figure 10. Remote Temperature Monitoring Circuit Example Using the TMP20
FAULT RESPONSES AND ALERT PROCESSING
Software monitors that the rail stays within a window of normal operation. There are two programmable warning
levels (under and over) and two programmable fault levels (under and over). When any monitored voltage,
current, or temperature goes outside of the warning or fault window, the PMBALERT# pin is asserted
immediately, and the appropriate bits are set in the PMBus status registers (see Figure 6). Detailed descriptions
of the status registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 102 ms with 400-ms resolution. A glitch filter for an input defined as a current
or temperature can be between 0 and 25.5 seconds with 100-ms resolution. The longer time constants are due
to the fixed low-pass digital filters associated with current and temperature inputs.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT _LIMIT
RAIL 1 VOLTAGE
RAIL 2 EN
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
MAX_GLITCH_TIME
TOFF_DELAY[1]
MAX_GLITCH_TIME
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Figure 11. Sequencing and Fault-Response Timing
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PMBUS_CNTRL PIN
TON_DELAY[1]
RAIL 1 EN
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
Time Between Restarts
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
POWER_GOOD_ON[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
TON_DELAY[2]
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
Figure 12. Maximum Turn-on Fault
The configurable fault limits are:
Maximum turn-on fault – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within
the configured time
Undervoltage warning – Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
Undervoltage fault – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
Overvoltage warning – Flagged if a rail exceeds the specified OV warning limit at any time during startup or
operation
Overvoltage fault – Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation
Maximum turn-off warning – Flagged if a rail that is commanded to shut down does not reach 12.5% of the
nominal rail voltage within the configured time
Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault
occurs. If a warning occurs, the following takes place:
Warning Actions
— Immediately assert the PMBALERT# pin
— Status bit is flagged
— Assert a GPIO pin (optional)
— Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault Responses
— Continue Without Interruption: Flag the fault and take no action
— Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail
configuration
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— Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are
configured. If the rail does not come back, schedule the shutdown of this rail and all
fault-shutdown slaves. All selected rails, including the faulty rail, are sequenced off according to
their T_OFF_DELAY times. If Do Not Restart is selected, then sequence off all selected rails
when the fault is detected.
Restart
— Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.
— Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.
The time between restarts is measured between when the rail enable pin is deasserted (after any
glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can
be set between 0 and 1275 ms in 5-ms increments.
— Restart Continuously: Same as Restart Up To N Times except that the device continues to restart
until the fault goes away, it is commanded off by the specified combination of PMBus
OPERATION command and PMBUS_CNTRL pin status, the device is reset, or power is removed
from the device.
— Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after
continue-operation time is reached and then sequence-on those rails using turn-on delay times
SHUT DOWN ALL RAILS AND SEQUENCE ON (RE-SEQUENCE)
In response to a fault, the UCD90124 can be configured to turn off a set of rails and then sequence them back
on. To sequence all rails in the system, then all rails must be selected as fault-shutdown slaves of the faulted rail.
If the faulted rail is set to stop immediately or stop with delay, then the rails designated as fault-shutdown slaves
behave the same way. Shut-down-all-rails and sequence-on are not performed until retries are exhausted for a
given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and
fault-shutdown slaves sequence-off, the UCD90124 waits for a programmable delay time between 0 and 1275
ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the
start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully
achieve regulation or for a user-selected 1, 2, 3, or 4 times. If the resequence operation is successful, the
resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second.
Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there
are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken.
For example, if a set of rails is already on its second resequence and the device is configured to resequence
three times, and another set of rails enters the resequence state, that second set of rails is only resequenced
once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can resequence,
and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut
down before resequencing.
GPIOs
The UCD90124 has 22 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.
There are an additional four pins that can be used as either inputs or PWM outputs but not as GPOs. Table 3
lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system-level functions such as
external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or
down by configuring a rail without a MON pin but with a GPIO set as an enable.
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Table 3. GPIO Pin Configuration Options
PIN NAME
PIN
RAIL EN
(12 MAX)
GPI
(8 MAX)
GPO
(12 MAX)
FAN TACH
(4 MAX)
FAN PWM
(4 MAX)
PWM OUT
(12 MAX)
MARGIN PWM
(10 MAX)
FPWM1/GPIO5
17
X
X
X
X
X
X
X
FPWM2/GPIO6
18
X
X
X
X
X
X
X
FPWM3/GPIO7
19
X
X
X
X
X
X
X
FPWM4/GPIO8
20
X
X
X
X
X
X
X
FPWM5/GPIO9
21
X
X
X
X
X
X
X
FPWM6/GPIO10
22
X
X
X
X
X
X
X
FPWM7/GPIO11
23
X
X
X
X
X
X
X
FPWM8/GPIO12
24
X
X
X
X
X
X
X
FANTAC1/GPI1/PWM1
31
X
X
X
X
FANTAC2/GPI2/PWM2
32
X
X
X
X
FANTAC3/GPI3/PWM3
42
X
X
X
X
X
FANTAC4/GPI4/PWM4
41
X
X
X
X
X
GPIO1
11
X
X
X
X
GPIO2
12
X
X
X
X
GPIO3
13
X
X
X
X
GPIO4
14
X
X
X
X
GPIO13
25
X
X
X
X
GPIO14
29
X
X
X
X
GPIO15
30
X
X
X
X
GPIO16
33
X
X
X
X
GPIO17
34
X
X
X
X
GPIO18
35
X
X
X
X
TCK/GPIO19
36
X
X
X
X
TDO/GPIO20
37
X
X
X
X
TDI/GPIO21
38
X
X
X
X
TMS/GPIO22
39
X
X
X
X
GPO Control
The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in
internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)
can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a
GPO using PMBus commands.
GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to four ANDs all ORed
together (Figure 13). Inputs to the logic blocks can include GPIs and rail-status flags. One rail status type is
selectable as an input for each AND gate in a Boolean block. For a selected rail status, the status flags of all
active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted until cleared by a
MFR PMBus command or by a specially configured GPI pin. The different rail-status types are shown in
Figure 15. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for
complete definitions of rail-status types.
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GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
_GPI(0)
1
GPI(0)
_GPI (1:7)
_STATUS(0:11)
Sub - block repeated for each of GPI(1:7)
0
There is one STATUS_TYPE_SELECT for
each of the four AND gates in a boolean
block. See Status Types on next slide.
1
STATUS_TYPE_SELECT(x,0)
Status Type 1
1
13
STATUS(0)
_GPI (0:7)
STATUS(1)
_STATUS(0:12)
1
13
Status Type 35
GPO_INVERSE(x)
GPOx
13
_GPI (0:7)
Sub - block repeated for each of STATUS(0:11)
2
_STATUS(0:12)
STATUS_INVERSE(12)
STATUS(12)
STATUS_ENABLE(12)
1
_STATUS(12)
_GPI (0:7)
3
_STATUS(0:12)
Figure 13. Boolean Logic Combinations
Figure 14. Fusion Boolean Logic Builder
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1.
2.
3.
POWER_GOOD(0:12)
VOUT_OV_FAULT(0:12)
VOUT_OV_FAULT_LATCH(0:12)
20.
21.
22.
TEMP_OT_FAULT(0:12)
TEMP_OT_FAULT_LATCH(0:12)
TEMP_OT_WARN(0:12)
4.
5.
6.
VOUT_OV_WARN(0:12)
VOUT_OV_WARN_LATCH(0:12)
VOUT_UV_WARN(0:12)
23.
24.
25.
TEMP_OT_WARN_LATCH(0:12)
INPUT_VIN_OV_FAULT(0:12)
INPUT_VIN_OV_FAULT_LATCH(0:12)
7.
8.
VOUT_UV_WARN_LATCH(0:12)
VOUT_UV_FAULT(0:12)
26.
27.
INPUT_VIN_OV_WARN(0:12)
INPUT_VIN_OV_WARN_LATCH(0:12)
9.
10.
VOUT_UV_FAULT_LATCH(0:12)
VOUT_TON_FAULT(0:12)
28.
29.
INPUT_VIN_UV_WARN(0:12)
INPUT_VIN_UV_WARN_LATCH(0:12)
11.
12.
13.
14.
15.
16.
17.
18.
19.
VOUT_TON_FAULT_LATCH(0:12)
VOUT_TOFF_WARN(0:12)
VOUT_TOFF_WARN_LATCH(0:12)
IOUT_OC_FAULT(0:12)
IOUT_OC_FAULT_LATCH(0:12)
IOUT_OC_WARN(0:12)
IOUT_OC_WARN_LATCH(0:12)
IOUT_UC_FAULT(0:12)
IOUT_UC_FAULT_LATCH(0:12)
30.
31.
32.
33.
INPUT_VIN_UV_FAULT(0:12)
INPUT_VIN_UV_FAULT_LATCH(0:12)
MFR_SEQ_TIMEOUT(0:12)
MFR_SEQ_TIMEOUT_LATCH(0:12)
Figure 15. Rail-Status Types
GPI Special Functions
There are five special input functions for which GPIs can be used. There can be no more than one pin assigned
to each of these functions.
•
•
•
•
•
Sequencing Timeout Source - If SEQ_TIMEOUT is non-zero on any rail, a fault will occur if this GPI pin
does not go active within SEQ_TIMEOUT time after the rail reaches its power good state.
Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), you can configure a
GPI that will clear the latched status.
Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a
margined state (low or high).
Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin
Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin
High.
Fans Installed - Fan control is enabled while this pin is asserted.
The polarity of GPI pins can be configured to be either Active Low or Active High.
Power-Supply Enables
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the
GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or
pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD90124 can
support a maximum of 12 enable pins.
Cascading Multiple Devices
A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device
and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship among
multiple devices. During startup, the slave controllers initiate their start sequences after the master has
completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the
master starts to sequence-off, it sends the shut-down signal to its slaves.
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD90124 allows GPIOs to be configured to respond to a desired
subset of power-good signals.
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PWM Outputs
FPWM1-8
Pins 17–24 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs , fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 – same frequency
• FPWM3 and FPWM4 – same frequency
• FPWM5 and FPWM6 – same frequency
• FPWM7 and FPWM8 – same frequency
If an FPWM pin from a pair is not used while its companion is set up to function, it is recommended to configure
the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the system. By
setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for any other
functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as Equation 1.
Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16)
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1.
2.
3.
4.
Divide 250MHz by 75MHz to obtain 3.33.
Round off 3.33 to obtain an integer of 3.
Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.
Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
PWM1-4
Pins 31, 32, 41, and 42 can be used as GPIs or PWM outputs.
If
•
•
•
configured as PWM outputs, then limitations apply:
PWM1 has a fixed frequency of 10 kHz
PWM2 has a fixed frequency of 1 kHz
PWM3 and PWM4 frequencies can be 0.93 Hz to 7.8125 MHz.
The frequency for PWM3 and PWM4 is derived by dividing down a 15.625MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625MHz by any integer between 2 and (224-1). The
duty cycle resolution will be dependent on the set frequency for PWM3 and PWM4.
The PWM3 or PWM4 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as Equation 2
Change per Step (%)PWM3/4 = frequency ÷ 15.625 × 106
(2)
To determine the closest frequency to 1MHz that PWM3 can be set to calculate as the following:
1.
2.
3.
4.
Divide 15.625MHz by 1MHz to obtain 15.625.
Round off 15.625 to obtain an integer of 16.
Divide 15.625MHz by 16 to obtain actual closest frequency of 976.563kHz.
Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.
All frequencies below 238Hz will have a duty cycle resolution of 0.0015%.
24
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Programmable Multiphase PWMs
The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to
360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock
generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270°
(Figure 16).
Figure 16. Multiphase PWMs
MARGINING
Margining is used in product validation testing to verify that the complete system works properly over all
conditions, including minimum and maximum power-supply voltages, load range, ambient temperature range,
and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION
command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG
command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes
different available margining options, including ignoring faults while margining and using closed-loop margining to
trim the power-supply output voltage one time at power up.
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Open-loop margining is done by connecting a power-supply feedback node to ground through one resistor and to
the margined power supply output (VOUT) through another resistor. The power-supply regulation loop responds to
the change in feedback node voltage by increasing or decreasing the power-supply output voltage to return the
feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the
voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors
from the feedback node of each power supply to VOUT or ground.
MON(1:13)
3.3V
UCD90124
POWER
SUPPLY
10k W
GPIO(1:12)
/EN
3.3V
Vout
VOUT
VFB
Rmrg_HI
V BF
GPIO
GPIO
“0” or “1”
VOUT
“0” or “1”
Rmrg_LO
3.3V
POWER
SUPPLY
10k W
/EN
Vout
VOUT
VFB
VFB
Rmrg_HI
VOUT
3.3V
.
Rmrg_LO
Open Loop
Margining
Figure 17. Open-Loop Margining
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power-supply feedback node through a resistor. The power-supply output voltage is monitored,
and the margining voltage is controlled by adjusting the PWM duty cycle until the power-supply output voltage
reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the
same that applies to the voltage measurement resolution (Table 2). When using a closed-loop margining
configuration it is important to determine the default duty cycle that is necessary to maintain the margined
power-supply at the nominal operation voltage. Make note that if margining is configured, and the rail is not set to
Margin High or Margin Low then the PWM used for margining will stay active and operate at the default duty
cycle which will control the operation of the power supply. Given that this closed-loop system has feed back
through the ADC, the closed-loop margining accuracy will be dominated by the ADC measurement. For more
details on configuring the UCD90124 for margining, see the Voltage Margining Using the UCD9012x application
note (SLVA375).
26
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MON (1:13)
3.3V
UCD90124
POWER
SUPPLY
/EN
VOUT
10k W
GPIO
VFB
250 kHz – 1MHz
Vout
R1
VFB
Vmarg
FPWM 1
R3
R4
C1
Closed Loop
Margining
R2
Figure 18. Closed-Loop Margining
FAN CONTROL
The UCD90124 can control and monitor up to four two-, three- or four-wire fans. Up to four GPIO pins can be
used as tachometer inputs. The number of fan tach pulses per revolution for each fan can be entered using the
Fusion GUI. A fan speed-fault threshold can be set to trigger an alarm if the measured speed drops below a
user-defined value.
The two- and three-wire fans are controlled by connecting the positive input of the fan to the specified supply
voltage for the fan. The negative input of the fan is connected to the collector or drain of a transistor. The
transistor is turned off and on using a GPIO pin. Four-wire fans can be controlled the same way. However,
four-wire fans should use the fan PWM input (the fourth wire). It can be driven directly by one of the eight FPWM
or the two adjustable PWM outputs. The normal frequency range for the PWM input is 15 kHz to 40 kHz, but the
specifications for the fan confirm the interface procedure.
Temperature
senso
sensor
r
MONx
AVSS 3
12 V
2--wire Fan
12 V
UCD90124
MOSFET turns
fan on and off
GND
DC Fan
GPIO
GPIO controls
MOSFET
Figure 19. Two-Wire Fan Connection
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Temperature
senso
sensor
r
MONx
AVSS 3
12 V
3--wire Fan
12 V
UCD90124
GPIO
Fan Tach output to
GPI/GPIO for fan
speed monitoring
TACH
MOSFET turns
fan on and off
GND
DC Fan
GPIO
GPIO controls
MOSFET
Figure 20. Three-Wire Fan Connection
Temperature
senso
sensor
r
MONx
AVSS 3
44-wire
Fan
12 V
UCD90124
15kHz – 30kHz
3.3V PWM signal
changes fan speed
with duty cycle
FPWM
12V
PWM
GPIO
TACH
3.3V TACH output
to GPI/GPIO for fan
speed monitoring
DC Fan
GND
Figure 21. Four-Wire Fan Connection
The UCD90124 autocalibrate feature automatically finds and records the turn-on, turn-off and maximum speeds
and duty cycles for any fan. Fans have a minimum speed at which they turn on, a turn-off speed that is usually
slightly lower than the turn-on speed, and a maximum speed that occurs at slightly less than 100% duty cycle.
Each speed has a PWM duty cycle that goes with it. Every fan is slightly different, even if the model numbers are
the same. The built-in temperature control algorithms use the actual measured operating speed range instead of
0 RPM to rated speed of the fan to improve the fan control algorithms. The user can choose whether to use
autocalibrate or to manually enter the fan data.
The UCD90124 can control up to four independent fans as defined in the PMBus standard. When enabled, the
28
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FAN-PWM control output provides a digital signal with a configurable frequency and duty cycle, with a duty cycle
that is set based on the FAN_COMMAND_1 PMBus command. The PWM can be set to frequencies between 1
Hz and 125 MHz based on the UCD90124 PWM type selected for the fan control. The duty cycle can be set from
0% to 100% with 1% resolution. The FAN-TACH fan-control input counts the number of transitions in the
tachometer output from the fan in each 1-second interval. The tachometer can be read by issuing the
READ_FAN_SPEED_1 command. The speed is returned in RPMs.
Fault limits can also be set for the tachometer speed by issuing the FAN_SPEED_FAULT_LIMIT command and
the status checked by issuing the STATUS_FAN_1_2 command. See the UCD90xxx Sequencer and System
Health Controller PMBus Command Reference for a complete description of each command.
The UCD90124 also supports two fan control algorithms.
Hysteretic Fan Control
TempON and TempOFF levels are input by the user. TempON is higher than TempOFF. A GPIO pin is used to turn
the fan or fans on at full speed when the monitored temperature reaches TempON and to turn the fans off when
the temperature drops below TempOFF.
TOT
Inputs: TON, TOFF, TOT, Update
Interval, Rail where MEAS_TEMP
is monitored, GPOx pin
• System starts up at t = 0
seconds
• MEAS_TEMP = 25°C →
ambient temp
• GPO/PWM is low and Fan is off
• Check MEAS_TEMP every 1
second (or 250 msec)
• When MEAS_TEMP = TON, set
GPO/PWM = 1 → turn fan on
• Leave GPO/PWM = 1 unless
MEAS_TEMP < TOFF
• If MEAS_TEMP is > TON,
declare a fault and take the
prescribed action.
Temp increase
above TON : Assert
GPO to turn on Fan
Temp drops below above
TOFF : De-assert GPO to
turn off Fan
TON
TOFF
Temp drops below
TON : GPO and Fan
stays on (hysteresis)
MEAS_TEMP
25°C (tamb)
t = 0 sec 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
GPO output
0
t = 0 sec 1
MaxSpeed
Fan Speed
Off
t = 0 sec 1
Figure 22. Hysteretic Temperature Control for 2- or 3-wire Fans
Set Point Fan Control
The second algorithm (Figure 23) uses five control set points that each have a temperature and a fan speed.
When the monitored temperature increases above one of the set point temperatures, the fan speed is increased
to the corresponding set point value. When the monitored temperature drops below a set point temperature, the
fan speed is reduced to the corresponding set point value. The ramp rate for speed can be selected, allowing the
user to optimize fan performance and minimize audible noise.
The fan speed is varied by changing the duty cycle of a PWM output. For two- and three-wire fans, as the fan is
turned on and off, the inertia of the fan smoothes out the fan speed changes, resulting in variable speed
operation. This approach can be taken with any fan, but would most likely be used with two- or three-wire fans at
a PWM frequency in the 40-Hz to 80-Hz range. Four-wire fans would use the PWM input as described earlier in
this section.
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TOT
TEMP5, SPD5
TEMP4, SPD4
TEMP3, SPD3
Inputs: TOT, Updates Interval, Rail that
MEAS_TEMP
TEMP2, SPD2
MEAS_TEMP is being monitored on, PWM
pin, PWM freq, PWM temp rate, FANTAC
TEMP1, SPD1
pin, 5x (TEMPn, SPEEDn) setpoints.
25°C (T )
• System starts up at t = 0 seconds
t = 0 sec
5
10
15
20
25
30
35
40
45
50
55
60
• MEAS_TEMP = 25°C at ambient temp
• PWM DUTY_CYCLE = 0% and fan is
off
SPD5
Max Speed
• Check MEAS_TEMP every 250 ms (or 1
SPD4
Fan Speed ramps
down to Target Speed
Target and
SPD3
s)
by reducing
PWM Duty Cycle
Ramp Speed
SPD2
• When MEAS_TEMP > TEMP1:
Temp rises above
Fan Speed ramps up to
SPD1
– set SPEED_TARGET = SPEED1
TEMP1 à Target Speed
Target Speed by
Temp falls below
increases to SPD1
increasing PWM Duty
TEMP2 à Target Speed
Cycle
– increase DUTY_CYCLE to
decreases to SPD1
Off (SPD0)
DUTY_CYCLE_ON
t = 0 sec
5
10
15
20
25
30
35
40
45
50
55
60
– increase DUTY_CYCLE by ramp
rate (10%/second) until SPEED =
SPEED_TARGET
When MEAS_TEMP > TEMP2:
100%
– set SPEED_TARGET = SPEED2
– increase DUTY_CYCLE by ramp
PWM duty cycle
rate until SPEED =
SPEED_TARGET
• Repeat as temperature is increased for
0%
each new setpoint
t = 0 sec
5
10
15
20
25
30
35
40
45
50
55
60
• If MEAS_TEMP > TOT, declare a fault
Figure 23. Temperature and Speed Set Point PWM Control for
and take the prescribed action
Four-Wire Fans
amb
•
•
If temperature drops - above TEMP4 to below TEMP3 for example
– when MEAS_TEMP drops below TEMP4, maintain SPEED4 → do not change the DUTY_CYCLE
– when MEAS_TEMP drops below TEMP3, set SPEED_TARGET = SPEED3
– decrease DUTY_CYCLE by ramp rate (10%/second) until SPEED = SPEED_TARGET
To turm the fan off when MEAS_TEMP < TEMP1, set SPEED1 = 0 RPM
EXAMPLE: MEAS_TEMP = 25°C at ambient temp:
• t = 0 to 5 sec: MEAS_TEMP increases from ambient to TEMP1 → increases SPEED_TARGET from SPD0
(Off) to SPD1 → increases DUTY_CYCLE from 0% to DUTYON (30%) → ACTUAL fan speed ramps up
from 0 RPM to SPD1.
• t = 5 to 10 sec: MEAS_TEMP increases > TEMP2 → increases SPEED_TARGET from SPD1 to SPD2 →
increases DUTY_CYCLE → ACTUAL fan speed ramps up from SPD1 to SPD2.
• t = 10 to 25 sec: MEAS_TEMP increases to > TEMP5 → SPEED_TARGET increases from SPD2 to SPD5
→ DUTY_CYCLE ramps to DUTYMAX → ACTUAL fan speed increases SPD5.
• t = 25 to 30 sec: MEAS_TEMP stays > TEMP5 → SPEED_TARGET and DUTY_CYCLE do not change →
ACTUAL fan speed stays at SPD5.
• t = 30 to 35 sec: MEAS_TEMP decreases to < TEMP4 → SPEED_TARGET drops to SPD4 and then to
SPD3 → decreases DUTY_CYCLE → ACTUAL fan speed ramps down from SPD5 to SPD3.
• t = 35 to 60 sec: MEAS_TEMP decreases to < TEMP1 → SPEED_TARGET drops to SPD0 → decreases
DUTY_CYCLE to DUTYOFF → ACTUAL fan speed ramps down from SPD3 to SPD0 (Off).
30
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SYSTEM RESET SIGNAL
The UCD90124 can generate a programmable system-reset signal as part of sequence-on. The signal is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time Figure 24. The system-reset delay
duration can be programmed as shown in Table 4.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_DELAY[2]
RAIL 2 EN
POWER_GOOD_ON[2]
RAIL 2 VOLTAGE
DELAY TIME
GPO SET AS SYSTEM RESET
Figure 24. SYSTEM RESET Timing for a 2-Rail System
Table 4. System-Reset Delay
Duration
Delay Duration
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.19 s
16.38 s
32.8 s
WATCH DOG TIMER
A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply
sequencing or tied to a GPIO configured to provide a system-reset signal. The WDT can be reset by toggling a
watchdog input (WDI) pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.
The WDT can be active immediately at power up or set to wait while the system initializes. Table 5 lists the
programmable wait times before the initial timeout sequence begins.
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Table 5. WDT Initial Wait Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
800 ms
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102 s
205 s
410 s
819 s
1638 s
The watchdog timeout is programmable from 0 to 2.55 s with a 10-ms step size. If the WDT times out, the
UCD90124 can assert a GPIO pin configured as WDO that is separate from a GPIO defined as system-reset pin,
or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the WDI pin or by
writing to SYSTEM_WATCHDOG_RESET over I2C.
WDI