UCD90320ZWSR

Product Folder Order Now Support & Community Tools & Software Technical Documents UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 UCD90320 32-Rail PMBus™ Power Sequencer and System Manager • • • • • • • • • • • Sequence, monitor, and margin 24 voltage rails plus 8 digital rails Monitor and respond to OV, UV, OC, UC, temperature, time-out, and GPI-triggered faults Flexible sequence-on and off dependencies, delay time, Boolean logic, and GPIO configuration to support complex sequencing aplications Four rail profiles for adaptive voltage identification (AVID) voltage regulator High-accuracy closed-loop margining Active trim function improves rail output voltage accuracy Advanced nonvolatile event logging to assist system debugging – Single-event fault log (100 entries) – Peak value log – Black box fault log to save status of all rails and I/O pins at the first fault Easily cascade up to 4 power sequencers and take coordinated fault responses Programmable watchdog timer and system reset Pin-selected rail state PMBus™ 1.2 compliant Dual-bank configurations to provide a fail-safe state when programming Nonvolatile event logging preserves fault events after power dropout. Black box fault log feature preserves the status for all rails and I/O pins when the first fault occurs. The cascading feature offers convenient ways to manage up to 128 voltage rails through one SYNC_CLK pin connection. Device Information(1) PART NUMBER PACKAGE UCD90320 BODY SIZE (NOM) BGA (169) 12.0 mm × 12.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application 12-V OUT 12-V OUT 12-V Cur 12-V Temp IC Temp INA196 3.3-V Supply 12-V OUT V33A V33D AMON 3.3-V OUT VOUT 1.8 V VOUT 0.8 V Cur 12 V Temp 12 V Temp 0.8 V VREF (Optional) AMON AMON AMON AMON AMON VREFA± • 1 The 32 ENx pins and the 16 LGPOx pins can be configured to be active driven or open drain outputs. VREFA+ 1 Features Hot Swap VOUT 3.3 V EN EN EN VFB UCD90320 DMON VIN 2 Applications Wired networking Wireless infrastructure Datacom module Data center and enterprise computing Factory automation and control Test and measurement Medical DC-DC1 AMON 32/¶V 3:5*' • • • • • • • VIN VOUT EN WDI from main processor GPIO WDO GPIO POWER_GOOD LGPO WARN_OV_ 0.8 V or WARN_OV_12 V GPIO EN GPIO Other sequencer done (cascade input) GPIO VOUT 1.8 V LDO1 0.8 V Temp IC EN SYSTEM_RESET VOUT EN VIN VOUT VOUT 0.8 V DC-DC2 VFB 2 I C/PMBus MARGIN 3.3-V 3 Description The UCD90320 device is a 32-rail PMBus™ addressable power sequencer and system manager in a compact 0.8-mm pitch BGA package. JTAG GPIO GPIO UCD90320 (Cascaded) SYNC-CLK SYNC_CLK The 24 integrated ADC channels (AMONx) monitor the power supply voltage, current, and temperature. Of the 84 GPIO pins, 8 can be used as digital monitors (DMONx), 32 to enable the power supply (ENx), 24 for margining (MARx), 16 for logical GPO, and 32 GPIs for cascading, and system function. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 3 3 8 Absolute Maximum Ratings ...................................... 8 ESD Ratings.............................................................. 8 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 9 Electrical Characteristics........................................... 9 Non-Volatile Memory Characteristics ..................... 10 I2C/PMBus Interface Timing Requirements ............ 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 15 8.5 Device Configuration and Programming ................. 41 9 Application and Implementation ........................ 45 9.1 Application Information............................................ 45 9.2 Typical Application ................................................. 45 10 Power Supply Recommendations ..................... 48 11 Layout................................................................... 48 11.1 Layout Guidelines ................................................. 48 11.2 Layout Example .................................................... 49 12 Device and Documentation Support ................. 50 12.1 12.2 12.3 12.4 12.5 Support Resources ............................................... Receiving Notification of Documentation Updates Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 50 50 50 50 50 13 Mechanical, Packaging, and Orderable Information ........................................................... 50 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2019) to Revision C Page • Added 'Dual-bank configurations' item to the Features.......................................................................................................... 1 • Added explanation for dual-bank mechanism in Device Configuration and Programming section...................................... 41 Changes from Revision A (Septemebr 2016) to Revision B Page • Changed pin D8 From: MRGN3 To: MAR3 in the pinout image ........................................................................................... 3 • Added IREF specification to ANALOG-TO-DIGITAL CONVERTER (ADC) section of Electrical Characteristics .................... 9 • Changed the values of VRESET From: MIN = 2.85 , TYP = 3, MAX = 3.15 To: MIN = 2, TYP = 2.3, MAX = 2.6 in the Electrical Characteristics ..................................................................................................................................................... 10 • Changed 200 kΩ to 200 Ω in Figure 40 .............................................................................................................................. 47 Changes from Original (August 2016) to Revision A • 2 Page Changed data sheet status from Product Preview to Production Data .................................................................................. 1 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 5 Description (continued) The FAULT pin coordinates the cascaded devices to take synchronized fault responses. The pin-selected rail states feature uses up to 3 GPIs to control up to eight user-defined power states. These states can implement system low-power modes as outlined in the Advanced Configuration and Power Interface (ACPI) specification. The TI Fusion Digital Power™ designer software is an intuitive PC-based graphic user interface (GUI) that can configure, store, and monitor all system operating parameters. 6 Pin Configuration and Functions ZWS Package 169-Pin BGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 A DVSS UnusedNC AMON6 AMON8 AMON1 0 AMON1 2 AMON2 2 AMON2 4 LGPO3 JTAG_T MS JTAG_T DO GPIO4 MAR15 A B AMON1 5 AMON1 6 AMON5 AMON7 AMON9 AMON1 1 AMON2 1 AMON2 3 LGPO2 JTAG_T DI GPIO1 GPIO2 MAR16 B C AMON1 3 AMON1 4 AVSS LGPO8 LGPO6 LGPO7 DVSS LGPO4 LGPO1 JTAG_T CK GPIO3 MAR14 MAR18 C D VREFA- VREFA+ V33A MAR5 LGPO5 BPCap V33D MAR3 DVSS DMON4 MAR13 MAR17 PMBUS _DATA D E AMON2 AMON1 AVSS MAR6 DVSS V33D DVSS V33D V33D PMBUS _CLK PMBUS _CNTRL MAR19 MAR20 E F AMON4 AMON3 DMON2 DMON1 MAR7 DVSS DVSS DVSS DVSS V33D PMB ALERT# EN26 EN25 F G AMON1 8 AMON1 7 DMON3 EN24 DVSS DVSS DVSS DVSS DVSS RESET EN27 UnusedDVSS UnusedNC G H AMON1 9 AMON2 0 EN23 EN22 DVSS DVSS DVSS DVSS DVSS EN28 EN31 EN30 EN29 H J BPCap EN20 EN21 EN19 DVSS BPCap V33D DVSS V33D V33D DVSS MAR24 MAR1 J K PMBUS _ADDR2 SYNC_ CLK EN17 EN18 MAR10 MAR4 EN13 EN10 EN6 EN4 UnusedDVSS UnusedV33D BPCap K L PMBUS PMBUS _ADDR1 _ADDR0 LGPO9 LGPO13 MAR2 MAR12 EN14 EN9 EN5 EN3 DMON5 MAR22 EN32 L M LGPO10 LGPO11 LGPO12 LGPO15 MAR23 MAR11 EN12 EN8 EN1 UnusedDVSS DMON8 UnusedNC MAR21 M N LGPO14 LGPO16 N 1 2 EN16 EN15 MAR8 MAR9 EN11 EN7 EN2 UnusedNC DMON7 DMON6 UnusedDVSS 3 4 5 6 7 8 9 10 11 12 13 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 3 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Pin Functions PIN NAME NO. I/O DESCRIPTION ANALOG MONITOR PINS (1) AMON1 E2 I Analog input monitor pin AMON2 E1 I Analog input monitor pin AMON3 F2 I Analog input monitor pin AMON4 F1 I Analog input monitor pin AMON5 B3 I Analog input monitor pin AMON6 A3 I Analog input monitor pin AMON7 B4 I Analog input monitor pin AMON8 A4 I Analog input monitor pin AMON9 B5 I Analog input monitor pin AMON10 A5 I Analog input monitor pin AMON11 B6 I Analog input monitor pin AMON12 A6 I Analog input monitor pin AMON13 C1 I Analog input monitor pin AMON14 C2 I Analog input monitor pin AMON15 B1 I Analog input monitor pin AMON16 B2 I Analog input monitor pin AMON17 G2 I Analog input monitor pin AMON18 G1 I Analog input monitor pin AMON19 H1 I Analog input monitor pin AMON20 H2 I Analog input monitor pin AMON21 B7 I Analog input monitor pin AMON22 A7 I Analog input monitor pin AMON23 B8 I Analog input monitor pin AMON24 A8 I Analog input monitor pin M9 I/O Digital output, rail enable signal or GPIO (2) EN2(GPIO) N9 I/O Digital output, rail enable signal or GPIO EN3(GPIO) L10 I/O Digital output, rail enable signal or GPIO EN4(GPIO) K10 I/O Digital output, rail enable signal or GPIO EN5(GPIO) L9 I/O Digital output, rail enable signal or GPIO EN6(GPIO) K9 I/O Digital output, rail enable signal or GPIO EN7(GPIO) N8 I/O Digital output, rail enable signal or GPIO EN8(GPIO) M8 I/O Digital output, rail enable signal or GPIO EN9(GPIO) L8 I/O Digital output, rail enable signal or GPIO EN10(GPIO) K8 I/O Digital output, rail enable signal or GPIO EN11(GPIO) N7 I/O Digital output, rail enable signal or GPIO EN12(GPIO) M7 I/O Digital output, rail enable signal or GPIO EN13(GPIO) K7 I/O Digital output, rail enable signal or GPIO EN14(GPIO) L7 I/O Digital output, rail enable signal or GPIO EN15(GPIO) N4 I/O Digital output, rail enable signal or GPIO EN16(GPIO) N3 I/O Digital output, rail enable signal or GPIO EN17(GPIO) K3 I/O Digital output, rail enable signal or GPIO EN18(GPIO) K4 I/O Digital output, rail enable signal or GPIO EN19(GPIO) J4 I/O Digital output, rail enable signal or GPIO ENABLE PINS EN1(GPIO) (1) (2) 4 TI recommends placing a 200-Ω resistor between analog input and monitor pins. GPIO: GPI, Command GPO, WDI, WDO, system reset (RESET), FAULT pin for multiple chip cascading Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION EN20(GPIO) J2 I/O Digital output, rail enable signal or GPIO EN21(GPIO) J3 I/O Digital output, rail enable signal or GPIO EN22(GPIO) H4 I/O Digital output, rail enable signal or GPIO EN23(GPIO) H3 I/O Digital output, rail enable signal or GPIO EN24(GPIO) G4 I/O Digital output, rail enable signal or GPIO EN25(GPIO) F13 I/O Digital output, rail enable signal or GPIO EN26(GPIO) F12 I/O Digital output, rail enable signal or GPIO EN27(GPIO) G11 I/O Digital output, rail enable signal or GPIO EN28(GPIO) H10 I/O Digital output, rail enable signal or GPIO EN29(GPIO) H13 I/O Digital output, rail enable signal or GPIO EN30(GPIO) H12 I/O Digital output, rail enable signal or GPIO EN31(GPIO) H11 I/O Digital output, rail enable signal or GPIO EN32(GPIO) L13 I/O Digital output, rail enable signal or GPIO CLOSED-LOOP MARGIN PINS MAR1(GPIO) J13 I/O Closed-loop margin PWM output or General GPIO MAR2(GPIO) L5 I/O Closed-loop margin PWM output or General GPIO MAR3(GPIO) D8 I/O Closed-loop margin PWM output or General GPIO MAR4(GPIO) K6 I/O Closed-loop margin PWM output or General GPIO MAR5(GPIO) D4 I/O Closed-loop margin PWM output or General GPIO MAR6(GPIO) E4 I/O Closed-loop margin PWM output or General GPIO MAR7(GPIO) F5 I/O Closed-loop margin PWM output or General GPIO MAR8(GPIO) N5 I/O Closed-loop margin PWM output or General GPIO MAR9(GPIO) N6 I/O Closed-loop margin PWM output or General GPIO MAR10(GPIO) K5 I/O Closed-loop margin PWM output or General GPIO MAR11(GPIO) M6 I/O Closed-loop margin PWM output or General GPIO MAR12(GPIO) L6 I/O Closed-loop margin PWM output or General GPIO MAR13(GPIO) D11 I/O Closed-loop margin PWM output or General GPIO MAR14(GPIO) C12 I/O Closed-loop margin PWM output or General GPIO MAR15(GPIO) A13 I/O Closed-loop margin PWM output or General GPIO MAR16(GPIO) B13 I/O Closed-loop margin PWM output or General GPIO MAR17(GPIO) D12 I/O Closed-loop margin PWM output or General GPIO MAR18(GPIO) C13 I/O Closed-loop margin PWM output or General GPIO MAR19(GPIO) E12 I/O Closed-loop margin PWM output or General GPIO MAR20(GPIO) E13 I/O Closed-loop margin PWM output or General GPIO MAR21(GPIO) M13 I/O Closed-loop margin PWM output or General GPIO MAR22(GPIO) L12 I/O Closed-loop margin PWM output or General GPIO MAR23(GPIO) M5 I/O Closed-loop margin PWM output or General GPIO MAR24(GPIO) J12 I/O Closed-loop margin PWM output or General GPIO F4 I/O Digital input monitor pin or GPIO DMON2(GPIO) F3 I/O Digital input monitor pin or GPIO DMON3(GPIO) G3 I/O Digital input monitor pin or GPIO DMON4(GPIO) D10 I/O Digital input monitor pin or GPIO DMON5(GPIO) L11 I/O Digital input monitor pin or GPIO DMON6(GPIO) N12 I/O Digital input monitor pin or GPIO DMON7(GPIO) N11 I/O Digital input monitor pin or GPIO GPIO AND CASCADING PINS DMON1(GPIO) Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 5 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. DMON8(GPIO) M11 I/O Digital input monitor pin or GPIO B11 I/O GPIO GPIO2 B12 I/O GPIO GPIO3 C11 I/O GPIO GPIO4 A12 I/O GPIO SYNC_CLK K2 I/O Synchronization clock I/O for multiple chip cascading LGPO1(GPIO) C9 I/O Logic GPO or GPIO LGPO2(GPIO) B9 I/O Logic GPO or GPIO LGPO3(GPIO) A9 I/O Logic GPO or GPIO LGPO4(GPIO) C8 I/O Logic GPO or GPIO LGPO5(GPIO) D5 I/O Logic GPO or GPIO LGPO6(GPIO) C5 I/O Logic GPO or GPIO LGPO7(GPIO) C6 I/O Logic GPO or GPIO LGPO8(GPIO) C4 I/O Logic GPO or GPIO LGPO9(GPIO) L3 I/O Logic GPO or GPIO LGPO10(GPIO) M1 I/O Logic GPO or GPIO LGPO11(GPIO) M2 I/O Logic GPO or GPIO LGPO12(GPIO) M3 I/O Logic GPO or GPIO LGPO13(GPIO) L4 I/O Logic GPO or GPIO LGPO14(GPIO) N1 I/O Logic GPO or GPIO LGPO15(GPIO) M4 I/O Logic GPO or GPIO LGPO16(GPIO) N2 I/O Logic GPO or GPIO GPIO GPIO1 LOGIC GPO PINS PMBus COMM INTERFACE PMBUS_CLK E10 I PMBus clock (must pull up to V33D) PMBUS_DATA D13 I/O PMBus data (must pull up to V33D) PMBALERT F11 O PMBus alert, active-low, open-drain output (must pull up to V33D) PMBUS_CNTRL E11 I PMBus control pin PMBUS_ADDR0 L2 I PMBus digital address input. Bit 0 PMBUS_ADDR1 L1 I PMBus digital address input. Bit 1 PMBUS_ADDR2 K1 I PMBus digital address input. Bit 2 JTAG_TMS A10 I Test mode select with internal pull-up JTAG_TCK C10 I Test clock with internal pull-up JTAG_TDO A11 O Test data out with internal pull-up JTAG_TDI B10 I Test data in with internal pull-up JTAG INPUT POWER, GROUND, AND EXTERNAL REFERENCE PINS RESET G10 I Active-low device reset input. Pull up to V33D. V33A D3 I Analog 3.3-V supply. Decouple from V33D to minimize the electrical noise contained on V33D from affecting the analog functions. V33D D7, E6, E8, E9, F10, J7, J9, J10 I Digital 3.3-V supply for I/O and some logic. D6, J1, J6, K13 I Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The BPCap pins should only be connected to each other and an external capacitor as specified in On-Chip Low Drop-Out (LDO) Regulator section of the Electrical Characteristics table. BPCap 6 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Pin Functions (continued) PIN I/O DESCRIPTION C3, E3 I Analog ground. These are separated from DVSS to minimize the electrical noise contained on V33D from affecting the analog functions. A1, C7, D9, E5, F9, H5, H9, J5, J8, J11, H6, H7, H8, G5, G6, G7, G8, G9, F6, F7, F8, E7 I Ground reference for logic and I/O pins. VREFA+ D2 I (Optional) positive node of external reference voltage VREFA- D1 I (Optional) negative node of external reference voltage UNUSED-NC A2, G13, M12, N10 – Do not connect. Leave floating or isolated. UNUSED-DVSS G12, K11, M10, N13 – Tie to DVSS. UNUSED-V33D K12 – Tie to V33D. NAME NO. AVSS DVSS UNUSED PINS Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 7 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage MIN MAX UNIT V33D to DVSS 0 4 V V33A to AVSS 0 4 V on all I/O pins except PMBUS_CNTRL, PMBALERT, MARGIN19, and MARGIN20, regardless of whether the device is powered (2) –0.3 5.5 V PMBUS_CNTRL, PMBALERT, MARGIN19, and MARGIN20 –0.3 VV33D + 0.3 V 25 mA Operating junction temperature, TJ TBD 150 °C Storage temperature, Tstg –65 150 °C Input voltage Output current (1) (2) Maximum current per output pin Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those listed in the Recommended Operating Conditions table. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Applies to static and dynamic signals including overshoot. 7.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VV33D VV33A (1) Supply input voltage MIN NOM MAX UNIT 3.15 3.3 3.63 V 2.97 3.3 3.63 V TA Operating ambient temperature –40 85 °C TC Operating case temperature –40 90 °C TJ Operating junction temperature –40 93 °C (1) 8 It is recommended to connect the V33A pin and the V33D pin to the same supply. V33A must be powered before V33D if sourced from different supplies. There is no restriction on the ordering sequence for powering off. Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 7.4 Thermal Information UCD90320 THERMAL METRIC (1) ZWS (BGA) UNIT 169 PINS Junction-to-ambient thermal resistance (2) (3) 41.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance (2) 15.8 °C/W RθJB Junction-to-board thermal resistance (2) (4) (5) 18.9 °C/W ψJT Junction-to-top characterization parameter (6) 0.3 °C/W 20.3 °C/W n/a °C/W RθJA ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance (1) (2) (3) (4) (5) (6) (4) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Junction to ambient thermal resistance (θJA), junction to board thermal resistance (θJB), and junction to case thermal resistance (θJC) numbers are determined by a package simulator. TJ = TA + (P × θJA) TJ = TPCB + (P × ΨJB) TJ = TB + (P × θJB)() TJ = TC + (P × ΨJT) 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 31.4 54.9 mA 4 µF 1.32 V 250 mA 3.63 V SUPPLY CURRENT IV33 Supply Current VV33D = VV33A = 3.3 V ON-CHIP LOW DROP-OUT (LDO) REGULATOR CLDO External filter capacitor size for internal power supply (1) VLDO LDO output voltage IINRUSH Inrush current 2.5 1.08 1.2 50 ANALOG-TO-DIGITAL CONVERTER (ADC) (2) (3) V33A ADC supply voltage AVSS ADC ground voltage CV33A Voltage reference decoupling capacitance between V33A and AVSS (if using internal reference) (4) VREFA+ Positive external voltage reference on VREFA+ pin VREF– Negative external voltage reference on VREF– pin IREF Current on VREF+ pin input CREF Voltage reference decoupling capacitance between VREFA+ and VREFA– (if using external reference) (4) VADCIN 0 V 1.01 µF 2.4 VAVSS External VREF+ = 3.3 V 3 V AVSS 0.3 V 330.5 440 µA 1.01 µF 0 V33A Analog input range, external reference (6) VVREFA– VVREFA+ ADC input leakage current RADC CADC (4) (5) (6) 3.3 Analog input range, internal reference (5) IL (1) (2) (3) 2.97 V 2 µA ADC equivalent input resistance 2.5 kΩ ADC equivalent input capacitance 10 pF Connect the capacitor as close as possible to pin D6. Total of two ADC channels run independently during normal operation. Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes offset error, gain error, and INL at any given ADC code. Two capacitors (1.0 µF and 0.01 µF) connected in parallel. Internal reference is connected directly between V33A and AVSS. External reference noise level must be under 12 bit (–74 dB) of full scale input, over input bandwidth, measured at VREFA+ - VREFA–. Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 9 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER FCONV ADC conversion rate (on each ADC channel) (1) N ADC resolution ET TEST CONDITIONS MIN TYP MAX UNIT 1 MSPS 12 bits Total unadjusted error, over full input rangea when using internal reference ±10 ±30 Total unadjusted error, over full input range when using external reference ±2.5 ±4 LSB DIGITAL INPUTS AND OUTPUTS (GPIO, Logic GPO, EN, AND MARGIN PINS) 0.65 × VV33D 5.5 V 0 0.35 × VV33D V VIH I/O high-level input voltage (7) VIL I/O low-level input voltage VHYS I/O input hysteresis 0.2 V VOH I/O high-level output voltage 2.4 V VOL I/O low-level output voltage IOH High-level source current VOH = 2.4 V (8) 4 mA IOL Low-level sink current VOL = 0.4 V (8) 4 mA 0.4 V RESET AND BROWNOUT V33DSlew Minimum V33D slew rate between 2.8 V and 3.2 V VRESET Supply voltage at which device comes out of reset VBOR Supply voltage at which device enters brownout VSHDN Supply voltage at which device shuts down tRESET Minimum low-pulse width needed at RESET̅ pin tIRT (7) (8) (9) Internal reset time 0.1 V/ms 2 2.3 2.6 V 2.93 3.02 3.11 V 2.7 2.78 2.87 V 250 (9) 9 ns 11.5 ms PMBUS_CNTRL, PMBALERT, MARGIN19 and MARGIN20 pins have VV33D + 0.3 V as maximum input voltage rating. IO specifications reflect the maximum current where the corresponding output voltage meets the VOH/VOL thresholds. If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a rare case), the internal reset time may be longer. 7.6 Non-Volatile Memory Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONFIGURATION FLASH MEMORY PECYC Number of program and erase cycles before failure TRET Data retention –40°C ≤ TJ ≤ 85°C 100,000 Cycles 20 Years 500,000 Cycles 20 Years FAULT AND EVENT LOGGING EEPROM EPECYC Number of mass program and erase cycles of a single word before failure ETRET Data retention 10 –40°C ≤ TJ ≤ 85°C Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 7.7 I2C/PMBus Interface Timing Requirements MIN NOM MAX UNIT I1 t(HD:STA) Start condition hold time 450 I2 t(LOW) Clock low period (1) 450 I3 tr Clock rise time and data rise time (2) I4 t(HD:DAT) Data hold time I5 tf Clock fall time and data fall time (3) I6 t(HIGH) Clock high time 300 ns I7 t(SU:DAT) Data setup time 225 ns I8 t(SU:STA) Start condition setup time (repeated start only) 450 ns I9 t(SU:STO) Stop condition setup time 300 ns I10 t(DV) Data valid (1) (2) (3) ns ns See (2) 25 112.5 ns ns 125 25 ns ns PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements, Transport and Electrical Interface, Revision 1.2, Section 5.2.6. Because the I2CSCL signal and the I2CSDA signal operate as open-drain-type signals, which the controller can actively drive only "Low", the time that either signal takes to reach a high level depends on external signal capacitance and pull-up resistor values. Specified at a nominal 50-pF load. I2 I10 I6 I5 I2CSCL I1 I7 I4 I8 I3 I9 I2CSDA Figure 1. I2C/PMBus Timing Diagram Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 11 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com 1 1 0.8 0.8 ADC Differential Non-linearity (LSB) ADC Differential Non-linearity (LSB) 7.8 Typical Characteristics 0.6 0.4 0.2 INL Minimum INL Maximum 0 -0.2 -0.4 -0.6 -0.8 -1 -40 -25 -10 5 20 35 50 65 Junction Temperature (°C) 80 95 110 0.6 0.4 0.2 DNL Minimum DNL Maximum 0 -0.2 -0.4 -0.6 -0.8 -1 -40 -25 D001 Figure 2. 12 -10 5 20 35 50 65 Junction Temperature (°C) 80 95 110 D001 Figure 3. Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 8 Detailed Description 8.1 Overview Electronic systems such as CPU, DSP, microcontroller, FPGA, and ASIC can have multiple voltage rails and require certain power-ON and power-OFF sequences in order to function correctly. The UCD90320 device can control up to 32 voltage rails and ensure correct power sequences during normal condition and fault conditions. In addition to sequencing, the device can continuously monitor rail voltages, currents, temperatures, fault conditions, and report the system health information to upper computers through a PMBus interface, improving long term reliability. The device can protect electronic systems by responding to power system faults. The fault responses are conveniently configured by users through Fusion Digital Power Designer software. Fault events are stored in onchip nonvolatile flash memory in order to assist failure analysis. A Black Box Fault Log feature stores comprehensive system statuses at the moment when the first fault occurs. With this feature, failure analysis can be more effective. System reliability can be improved through four-corner testing during system verification. During four-corner testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known as margining. The device can perform accurate closed-loop margining for up to 24 voltage rails. During normal operation, UCD90320 can also actively trim DC output voltages using the same margining circuitry. This feature allows tuning rail voltages to an optimal level. The UCD90320 device supports control environments through both PMBus interface and pin-based interface. The device functions as a PMBus slave. It can communicate with upper computers with PMBus commands, and control voltage rails accordingly. In addition to rail enable (EN) pins, up to 32 GPIO pins can be configured as GPOs and directly controlled by PMBus commands. The device can be controlled by up to 32 GPIO configured GPI pins. The GPIs can be used as fault inputs which can shut down rails. The GPIs can be also used as Boolean logic input to control the 16 Logic GPO outputs. Each of the 16 Logic GPO pins has a flexible Boolean logic builder. Input signals of the Boolean logic builder can include GPIs, other GPOs, and selectable system flags such as POWER_GOOD, faults, warnings, and so forth. A simple state machine is also available for each Logic GPO pin. The device provides additional features such as cascading, pin-selected states, system watchdog, system reset, run time clock, peak value log, reset counter, and so forth. Cascading feature offers convenient ways to cascade up to four UCD90320 devices and manage up to 128 voltage rails through one SYNC_CLK pin connection. Pinselected states feature allows users to define up to 8 rail states. These states can implement system low-power modes as set out in the Advanced Configuration and Power Interface (ACPI) specification. The Feature Description of this datasheet describes other device features. 8.2 Functional Block Diagram JTAG Digital I/O PMBus Slave Rail Enables(32 max) Rail Margining (24 max) 32 Sequencing Engine 24ch ADC (12bit, 2x1MSPS) + 8 Digital Mon Programmable Logic GPO (16 max) 84 Configurable GPIO( GPI, GPO, Fault Pin, watchdog/ system reset, 32 max) Nonvolatile Event Logging Boolean Logic Builder Digital Mon Rail(8 max) Sync Clock Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 13 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com 8.3 Feature Description 8.3.1 TI Fusion Digital Power Designer Software The Texas Instruments Fusion Digital Power Designer software allows the user to configure the device. This PCbased graphic user interface (GUI) offers an intuitive I2C and PMBus interface to the device. The Fusion Digital Power Designer software allows the design engineer to configure the system operating parameters for the application without directly using PMBus commands, store the configuration to on-chip nonvolatile memory, and observe system status (voltage, current, temperature, faults, and so forth). This data sheet references the Fusion Digital Power Designer software is as Fusion Digital Power Designer software and many sections include screenshots. Download the Fusion Digital Power Designer software from TI here. After configuration, the device can perform all designed functions independently without further need for the Fusion GUI. 8.3.2 PMBUS Interface PMBus refers to a serial interface specifically designed to support power management. The PMBus interface is based on the SMBus interface that is built on the I2C physical specification. The UCD90320 device supports revision 1.2 of the PMBus standard. Wherever possible, standard PMBus interface commands support the function of the device. Unique features of the device are defined to configure or activate via the MFR_SPECIFIC commands. These commands are defined in the UCD90320 Sequencer and System Health Controller PMBUS Command Reference. The most current UCD90320 PMBus Command Reference can be found within the TI Fusion Digital Power Designer software through the Help Menu (Help, Documentation & Help Center, Sequencers tab, Documentation section). This data sheet makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power System Management Protocol Specification Part II – Command Language, Revision 1.2, dated 6 September 2010. The specification is published by the Power Management Bus Implementers Forum and is available from www.pmbus.org. The UCD90320 device meets all of the requirements of the Compliance section of the PMBus specification. The firmware complies with the SMBus 1.2 specification, including support for the SMBus ALERT function. The hardware supports either 100-kHz or 400-kHz PMBus operation. 8.3.3 Rail Setup Power rails are defined under the Pin Assignment tab, as shown in Figure 4. Click corresponding buttons to add or delete a rail. After a rail is added, AMON, DMON, EN, and MARGIN pins can be assigned to the rail. UCD90320 has 24 AMON pins, 8 DMON pins, 32 EN pins, and 24 MARGIN pins, thus can support up to 32 rails. Figure 4. Fusion Digital Power Designer Software Rail Setup Window (Configure ►Pin Assignment Tab) 14 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 8.4 Device Functional Modes 8.4.1 Rail Monitoring Configuration After rails are set up in the Pin Assignment tab, they are visible under the Vout Config tab, as shown in Figure 5. The initial voltage values are 0. Figure 5. Rail Selection Window (Rail Configuration) Configure the voltage monitoring parameters of the selected rail under the Vout Config tab. Figure 6 shows the configuration window. Figure 6. Rail Voltage Configuration Window (Rail Configure, Vout Config Tab) When a AMON pin is assigned in Figure 4 to monitor the voltage of a particular a rail, a fault or warn event occurs when the monitored rail voltage exceeds the voltage window defined by the Over and Under Warn/Fault thresholds. When a fault is detected, the device responds with user-defined actions. See the Fault Responses Configuration section for more details. Rail Profile is composed of a group of nine thresholds set by the following: • VOUT_COMMAND Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 15 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Device Functional Modes (continued) • • • • • • • • VOUT_OV_FAULT_LIMIT VOUT_OV_WARNING_LIMIT VOUT_OV_MARGIN_HIGH POWER_GOOD_ON VOUT_MARGIN_LOW POWER_GOOD_OFF VOUT_UV_WARNING_LIMIT VOUT_UV_FAULT_LIMIT Figure 7. Rail Profile Configurations (Rail Config ► Edit Rail Profiles) The device offers 50 individual profiles shared among all 24 AMON voltage rails. Each AMON voltage rail can have at least one but no more than four profiles. The profiles are controlled by 2 GPIs as shown in Figure 8. A programmable block-out period is used to block all voltage related faults on the given rail when profile is changed. Figure 8. Rails Profile Selection Through GPIs (Rail Config ► Edit Rail Profiles) The device supports digital monitor. If a DMON pin is assigned in Figure 7 to monitor POWER_GOOD of POL, the DMON rail has no rail profile. If the DMON input is logic HIGH, the rail is POWER_GOOD, otherwise the rails has UV fault or warns and is at POWER_NOT_GOOD. 16 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Device Functional Modes (continued) Figure 9. Digital Rail Configuration Window Vout Exponent defines the voltage value resolution according to PMBus linear data format. Fusion Digital Power Designer software can automatically select optimal Vout Exponent value to cover the required voltage range with the finest possible resolution. For more information regarding PMBus linear data format, refer to PMBus specification mentioned at the beginning of this section. On/Off Config defines a rail turn-ON and turn-OFF command: • None (Auto enable). Rail always seeks to turn-ON as long as UCD90320 is powered. • CONTROL Pin Only. Rail seeks to turn-ON and turn-OFF according to PMBus CONTROL line (asserted/deasserted). • OPERATION Only. Rail seeks to turn-ON and turn-OFF according to PMBus OPERATION command (On/Off). • Both CONTROL pin and OPERATION. Rail seeks to turn-ON when CONTROL pin is asserted, AND PMBus OPERATION command sets the rail to On. Rail seeks to turn-OFF when OPERATION command sets the rail to OFF, OR when CONTROL line is de-asserted. After receiving a turn ON or turn OFF command, a rail examines a series of conditions before asserting or deasserting its EN pin. Conditions include Rail Sequence On/Off Dependency, GPI Sequence On/Off Dependency, Turn-On/Off Delay, as shown in Rail Sequence Configuration section. Fixed percentage voltages setpoint, when checked, configures a rail into adaptive voltage scaling technology (AVS) mode. The Vout Setpoint can be dynamically set by PMBus during operation in order to achieve energy saving. The rail warn and fault voltage thresholds maintain fixed ratios with respect to the Vout Setpoint. Due to the fact that the power supply and UCD90320 device may not change Vout Setpoint simultaneously or with the same slew rate, the device takes the following steps to avoid false-triggering warn and fault. If the new Vout Setpoint is higher than the current Vout Setpoint, the OV warn and fault thresholds are immediately set to their respective new levels. Other thresholds are initially maintained, and then increase by 20-mV step size in every 400 µs until the new levels are reached. If the new Vout Setpoint is lower than the current Vout Setpoint, the UV warn and fault and Power Good On and Power Good Off thresholds are immediately set to their respective new levels. Other thresholds are initially maintained, and then decrease by 20-mV step size every 400 µs until the new levels are reached. Table 1 summarizes the thresholds adjustment scheme in AVS mode. This feature is not available for DMON pin. Table 1. Thresholds Adjustment Scheme in AVS Mode TRANSITION IMMEDIATE UPDATE OV fault and warn notification UV fault and warn notification, Margin High and Margin Low, Power Good On and Power Good Off UV fault and warn notification, Power Good On and Power Good Off OV fault and warn notification, Margin High and Margin Low New Vout Setpoint to Current Vout Setpoint (1) ADJUSTMENT (1) Gradual adjustment towards new levels with 2-0mV step size and 400-µs step interval Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 17 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Current and temperature monitoring parameters of the selected rail can be configured under the Fault Responses and Limits tab. First, select a rail in the top-right corner of the Fusion Digital Power Designer software, then edit the current and temperature monitoring parameters as shown in Figure 10. Figure 10. Current and Temperature Limits Configuration Window (Rail Config ► IOUT and Temperature Limits) Each rail has a Power Good status determined by the following rules. • If rail voltage is monitored by an AMON pin, the Power Good status is solely determined by Power Good On and Power Good Off thresholds as shown in Figure 6. A rail is given Power Good status if its rail voltage is above the Power Good On threshold. Otherwise, the rail is given Not Power Good status if the rail voltage is below the Power Good Off threshold. The rail remains in the current status if its voltage is neither above Power Good On nor below Power Good Off thresholds. • If rail voltage is not monitored by a AMON or DMON pin, the Power Good status is determined by the turnON and turn-OFF eligibility of the rail. A rail is immediately given Power Good status when the rail meets all the turn-on conditions set by the user, such as On and Off Config, dependencies and delays. Similarly, a rail is immediately given Not Power Good status when the rail meets all the turnoff conditions set by the user. The behavior is the same regardless whether a physical EN pin is assigned to the rail. The Power Good status is not affected by any warnings and faults unless the fault response is to turn OFF the rail. UV fault and warn notification is ignored when a rail is off. UV fault and warn notification is also ignored during start up until the rail enters Power Good status for the first time. This mechanism avoids false-triggering UV fault and warn notification when the rail voltage is expected to be below UV thresholds. A Graceful Shutdown feature is enabled by checking the Configured as VIN Monitor checkbox. When enabled, the rail is configured to monitor VIN. When VIN drops below Power Good Off threshold, the device ignores any UV fault and warn notifications on any other rail. 8.4.2 GPI Configuration Up to 32 of the 84 GPIO pins of the UCD90320 device can be configured as GPI. The GPI configuration window is under the Pin Assignment tab. Figure 11 shows an example. Figure 11. GPI Configuration Window (Hard Configuration ► Monitors and GPIO Pins Assignment) 18 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 The polarity of GPI pins can be configured to be either active high or active low. Each GPI can be used as a source of sequence dependency (see the Rail Sequence Configuration section). The GPI pins can be also used for cascading function (see the Cascading Multiple Devices section). The first defined three GPIs regardless of their main purpose are assigned to the pin selected states function (see the Pin Selected Rail States Configuration section). In addition to hard configuration functions, four special behaviors can be assigned to each GPI pin using the dropdown window shown in Figure 12: • GPI Fault: The de-assertion of this pin is treated as a fault, which can trigger shutdown actions for any voltage rails (see the Fault Responses Configuration section). • Latched Statuses Clear Source: This pin can be used to clear latched-type statuses (_LATCH) (see the GPO Configuration section). • Input Source for Margin Enable: When this pin is asserted, all rails with margining enabled enter into a margined state (low or high). This special behavior can be assigned to only one GPI. • Input Source for Margin Low and Not-High: When this pin is asserted, all margined rails are set to Margin Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails are set to Margin High as long as the Margin Enable is asserted. This special behavior can be assigned to only one GPI. • Configured as Debug Pin: When the pin is asserted, the device does not alert the PMBALERT pin, and neither responds to, nor logs, any faults as defined in Table 2. The device ignores the rail sequence ON and OFF dependency conditions. As soon as the sequence ON and OFF timeout expires, the rails are sequenced ON or OFF accordingly regardless of the timeout action. If the sequence ON or OFF timeout value is set to 0, the rails are sequenced ON or OFF immediately. The fault pins do not pull the fault bus low. LGPOs affected by these events return to the original states. • Configured as Fault Pin: GPI fault enable functionality must be set to enable this feature. When set, if there is no fault on a fault bus. The FAULT pin is digital input pin and it monitors the fault bus. When one or more UCD90329 devices detect a rail fault, the corresponding FAULT pin is turned into active driven low state, pulling down the fault bus voltage and informing all other UCD90320 devices of the corresponding fault. This behavior allows a coordinated action to be taken across multiple devices. After the fault is cleared, the state of the FAULT pin reverts to that of an input pin (see the Cascading Multiple Devices section). Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 19 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Figure 12. GPI Configuration Dropdown Window (Hardware Configuration ► Monitor and GPIO Pins Assignment) 20 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Table 2. List of Events Affected by Debug Mode EVENTS DESCRIPTION VOUT_OV_FAULT Voltage rail is over OV fault threshold VOUT_OV_WARNING Voltage rail is over OV warning threshold VOUT_UV_FAULT Voltage rail is under UV fault threshold VOUT_UV_WARNING Voltage rail is under UV warning threshold TON_MAX Voltage rail fails to reach power good threshold in predefined period. TOFF_MAX Warning Voltage rail fails to reach power not good threshold in predefined period IOUT_OC_FAULT Current rail is over OC fault threshold IOUT_OC_WARNING Current rail is under OC warning threshold IOUT_UC Current rail is under UC fault threshold OT_FAULT Temperature rail is over OT fault threshold OT_WARNING Temperature rail is over OT warning threshold All GPI de-asserted No logging and fault response, but the function of the GPI is not ignored. SYSTEM_WATCHDOG_TIMEOUT System watch timeout RESEQUENCE_ERROR Rail fails to resequence SEQ_ON_TIMEOUT Rail fails to meeting sequence on dependency in predefined period SEQ_OFF_TIMEOUT Rail fails to meeting sequence on dependency in predefined period SLAVE_FAULT Rail is shut down due to that its master has fault Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 21 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com 8.4.3 Rail Sequence Configuration Rail sequences can be configured through the Vout Config tab. First, select a rail in the top-right corner of the Fusion Digital Power Designer software, and then edit the rail sequence as shown in Figure 13. Figure 13. Rail Sequence Configuration Window (Rail Config) 22 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 When a rail receives a turn-ON or turn-OFF command as defined in On/Off Config, it checks its dependency conditions. When all dependencies are fulfilled, the rail then waits for a Turn ON Delay time or a Turn OFF Delay time, and then asserts or de-asserts the EN pin. The device fulfills a Rail Sequence On Dependency status when the rail is in Power Good status. The device fulfills a Rail Sequence Off Dependency status when the rail is in Not Power Good status. The device fulfills a GPI Sequence On Dependency status when the GPI pin is asserted. The device fulfills a GPI Sequence Off Dependency status when the GPI pin is de-asserted. The device fulfills a GPO Sequence On Dependency status when the logical sate of the GPO is TRUE. The device fulfills a GPO Sequence Off Dependency status when the logic state of the GPO is FALSE. After the EN pin of a rail is asserted, if the rail voltage does not rise above Power Good On threshold within the Maximum Turn-ON time, a Time On Max fault occurs. Similarly, after the EN pin of a rail is de-asserted, if the rail voltage does not fall below 12.5% nominal output voltage within Maximum Turn-OFF time, a Time Off Max warning occurs. Each rail can include a Fault Shutdown Slaves function. When a rail shuts down as a result of a fault, the associated slave rails also shut down. The device continues to monitor delays and dependencies of the slave rails during the shutdown process. Fault Shutdown Slaves cannot cascade. In other words, if a rail that is acting as a slave shuts down, the associated slave rails does not shut down. Each rail can set Sequencing On/Off Timeout periods. The timeout periods begin to increment when a rail receives a turn-ON or a turn-OFF command as defined in On/Off Config. When the Sequencing On/Off Timeout period elapsed, the rail executes one of 3 actions including: • Wait Indefinitely • Enable or Disable Rail • Re-sequence (Sequencing On only) Re-sequence is a series of actions that shuts down a rail and the Fault Shutdown Slaves, and then re-enables the rails according to sequence-on delay times and dependencies. The re-sequencing parameters can be configured in the Other Config tab, as shown in Figure 14. Figure 14. Re-Sequencing Options (Global Configuration ► Misc Config) Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 23 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com A re-sequencing event can be repeated for one to approximately four times or unlimited times. The Time Between Re-Sequences period begins to increment when all the relevant rails are given Not Power Good statuses. When the time period elapses, a re-sequence event begins. When the Enable Re-Sequence Abort is checked, the re-sequence event aborts if any relevant rail triggers a Max Turn Off warning. However, the Max Turn Off warning does not stop an ongoing re-sequence event. If any rails at the re-sequence state are caused by a GPI fault response, the device suspends the entire re-sequence event until the GPI fault is physically clear. It is also configurable to ignore the POWER_GOOD_OFF and TOFF_MAX_WARN status of a rail when performing re-sequencing if the corresponding bits are set. After the Rail Sequence is configured, the GUI displays simulated sequence timing in the Vout Config tab. It demonstrates the dependencies among the rails. An example is shown in Figure 15. The rails power-on and power-off slew rates in Figure 15 are for demonstration purpose only. Figure 15. Simulated Sequence Timing Window (Rail Config) 24 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 8.4.4 Fault Responses Configuration In the previous sections, various fault and warn notification thresholds have been configured to monitor voltage, current, temperature, and turn-ON time and turn-OFF time. When a fault threshold is reached, a fault event occurs. The device performs the following three actions in response of a fault event. • Asserts the PMBus ALERT line • Logs the fault event into nonvolatile memory (data flash), set status register bit • Executes fault responses defined by users The Fault Responses can be configured under the Fault Responses and Limits tab. Figure 16 shows an example configuration window. Figure 16. Fault Responses Configuration Window (Rail Configure ► Fault Responses) A programmable glitch filter can be enabled or disabled for each type of fault. When a fault remains present after the glitch filter time expires, the device performs of the three selectable actions: • Log the fault and take no further action. • Log the fault and shut down the rail immediately. • Log the fault and shut down the rail with Turn Off Delay. After shutting down the rail, the device performs one of the three selectable actions: • Do not restart the rail until a new turn-on command is received. • Restart the rail. If the restart is unsuccessful, retry up to a user-defined number of times (up to a maximum of 14) and then remain off until the fault is cleared. • Restart the rail. If the restart is unsuccessful, retry for an unlimited number of times unless the rail is commanded off by a signal defined in On/Off Config. After the rail exhausts the restart attempts, Re-sequence can be initiated (see the Rail Sequence Configuration section). Voltage, current, and temperature monitoring are based on results from the 12-bit ADC(AMON) and 8 DMON. All the voltage monitoring AMON and DMON channels are monitored every 400 µs for up to 32 channels. Current monitoring ADC channels are monitored at 200 µs per channel. Temperature monitoring ADC channels are monitored at approximately 4.17 ms per channel. The ADC results are compared with the programmed thresholds. The time to respond to an individual event is determined by when the event occurs within the ADC conversion cycle and the configured fault responses (glitch filters, time delays, and so forth). GPI pins can also trigger faults if the GPI Fault Enable checkbox in Figure 12 is checked. The GPI Fault Responses options are the same as the Fault Responses discussed earlier in this section, with one exception: the GPI Fault Responses option does not support the retry action. An example configuration window is shown in Figure 17. Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 25 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Figure 17. GPI Fault Responses Configuration Window (Rail Configure ► Fault Responses) 8.4.5 GPO Configuration 8.4.5.1 Command Controlled GPO The UCD90320 device has 84 GPIO pins, all of which can be configured as Command Controlled GPOs. These GPOs are controlled by PMBus commands (GPIO_SELECT and GPIO_CONFIG) and can be used to control LEDs, enable switches, and so forth. Details on controlling a GPO using PMBus commands can be found in the UCD90320 Sequencer and System Health Controller PMBus Command Reference. The configuration window of Command Controlled GPO is under Pin Assignment tab. An example configuration window is shown in Figure 18. Figure 18. Command Controlled GPO Configuration Window (Hardware Configure ► Monitor and GPIO Pins Assignment) 8.4.5.2 Logic GPO UCD90320 also has 16 dedicated Logic GPO (LGPO) pins. The configuration window is under Pin Assignment tab, as shown in Figure 19. 26 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Figure 19. Logic GPO Configuration Window (Hardware Configure ► Monitor and GPIO Pins Assignment) Each LGPO is controlled by an internal Boolean logic builder. Figure 20 shows the configuration interface of the Boolean logic builder. As shown, each Boolean logic builder has a top-level logic gate, which can be configured as AND, OR, or NOR gate with optional time delay. The inputs of the top-level logic gate are two AND paths. Each AND path can select a variety of inputs including GPI states, LGPO states, and rail statuses, as shown in Figure 21. The selectable rail statuses are summarized in Table 3. In Table 3, _LATCH type statuses stay asserted until cleared by a MFR PMBus command or by a specially configured GPI pin shown in Figure 12. See the UCD90320 Sequencer and System Health Controller PMBus Command Reference for complete definitions of rail-status types. Figure 20. Boolean Logic Builder Interface Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 27 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Figure 21. AND Path Configuration Table 3. Selectable Rail Statuses in Boolean Logic Builder Rail-Status Types POWER_GOOD IOUT_OC_FAULT TON_MAX_FAULT MARGIN_EN IOUT_OC_WARN TOFF_MAX_WARN MRG_LOW_nHIGH IOUT_UC_FAULT TON_MAX_FAULT_LATCH VOUT_OV_FAULT IOUT_OC_FAULT_LATCH TOFF_MAX_WARN_LATCH VOUT_OV_WARN IOUT_OC_WARN_LATCH SEQ_ON_TIMEOUT VOUT_UV_WARN IOUT_UC_FAULT_LATCH SEQ_OFF_TIMEOUT VOUT_UV_FAULT TEMP_OT_FAULT SEQ_ON_TIMEOUT_LATCH VOUT_OV_FAULT_LATCH TEMP_OT_WARN SEQ_OFF_TIMEOUT_LATCH VOUT_OV_WARN_LATCH TEMP_OT_FAULT_LATCH SYSTEM_WATCHDOG_TIMEOUT VOUT_UV_WARN_LATCH TEMP_OT_WARN_LATCH SYSTEM_WATCHDOG_TIMEOUT_LATCH VOUT_UV_FAULT_LATCH SINGLE_EVENT_UPSET 28 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 The POWER_GOOD status used by GPO evaluation is based on actual monitoring result from AMON or DMON pins. For a rail that does not have a voltage monitor pin, the POWER_GOOD status is used by sequencing purpose only, and is not used by GPO evaluation. Therefore during GPO evaluation, a rail without an AMON or DMON pin never reports POWER_GOOD status. Each LGPO can be also configured as a simple state machine, as shown in Figure 16. In state machine mode, the top-level logic gate is omitted and only one of the two AND paths is evaluated. The output of the state machine is the result of the active AND path. The evaluation initially starts with AND Path #1. If the evaluation result is TRUE, AND Path #1 remains active until its evaluation result becomes FALSE. When the output associates with AND Path#1 becomes FALSE, AND Path #2 becomes active in the next evaluation cycle. AND Path #2 remains active until its evaluation result becomes TRUE, then AND Path #1 becomes active in the next evaluation cycle. An evaluation cycle is triggered when any input signal to the state machine changes state. GPO1 to GPO8 outputs are internally synchronized to the same clock edge to enable them to change states together. GPO9 to GPO16 outputs are internally synchronized to enable them to change states together. GPO1 through GPIO8 and GPO9 through GPIO16 outputs status are updated within an time window between approximately 1 µs and 3 µs. 8.4.6 Margining Configuration The UCD90320 device provides accurate closed-loop margining for up to 24 voltage rails. System reliability is improved through four-corner testing during system verification. During four-corner testing, the system operates at the minimum and maximum expected ambient temperature and with each power supply set to the minimum and maximum output voltage, commonly referred to as margining. Margining can be controlled via the PMBus interface using the OPERATION command or by configuring two GPI pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG command in the UCD90320 Sequencer and System Health Controller PMBus Command Reference user guide describes several margining options, including ignoring faults while margining and using closed-loop margining to trim the rail output voltage. The device provides 24 PWM output pins for closed-loop margining. Figure 22 shows the block diagram of margining circuit. An external R-C network converts the PWM pulses into a DC margining voltage. The margining voltage is connected to the power supply feedback node through a resistor. The feedback node voltage is thus slightly pulled up or down by the margining voltage, causing the rail output voltage to change. The UCD90320 device monitors the rail output voltage. The device adjusts the margining PWM duty cycle accordingly such that the rail output voltage is regulated at the margin-high or margin-low voltages defined by the user. Effectively, margin control loop of the UCD90320 device overwrites the DC set point of the margined power supply. The margin control loop is extremely slow in order in order to not interfere with the power supply control loop. VREF UCD90320 R4 VIN + R3 Power Supply VOUT MARxx AMONxx R1 C1 C2 VFB R2 Figure 22. Block Diagram of Margining Circuit Margining pins can be configured under the Pin Assignment tab, as shown in Figure 23. When not margining, the margin pin can operate in one of three modes: • Tri-state • Active trim • Active duty cycle Tri-state mode sets the margin pin to high-impedance. Active Trim mode performs a continuously trim the DC output voltage. Active Duty Cycle mode provides a user-defined fixed PWM duty cycle as shown in Figure 23. Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 29 UCD90320 SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 www.ti.com Figure 23. Margining Configuration Dropdown Window (Hardware Configuration ► Monitor and GPIO Pin Assignment) 8.4.7 Pin Selected Rail States Configuration UCD90320 allows users to use up to three GPI pins to control up to eight rail states. Each rail state enables and disables certain rails. This feature is useful to implement system low-power modes, such as those compliant with the Advanced Configuration and Power Interface (ACPI) specification. The Pin Selected States function can be configured under the Pin Selected States tab, as shown in Figure 24. When a new state is presented on the GPI pins, and a rail is commanded to turn ON, it does so according to its sequence-on dependencies and delays. If a rail is commanded to turn OFF by a new state, it can be configured either immediately turn-OFF (Immediate OFF), or turn-OFF with its sequence-off dependencies and delays (Soft Off). If a rail is commanded to remain in the same ON state or OFF state, no action occurs. The Pin Selected Rail States function is implemented by modifying OPERATION command. Therefore, in order to use this function to control rail states, the related rails must be configured to use OPERATION command in On/Off Config (shown in Figure 6). The Pin Selected States feature always uses the first three configured GPI pins to select system states. When selecting a new system state, state changes on GPI pins must be completed within 1 µs, otherwise an unintended system state may be selected. See the UCD90320 Sequencer and System Health Controller PMBus Command Reference for complete configuration settings of Pin Selected States. 30 Submit Documentation Feedback Copyright © 2016–2020, Texas Instruments Incorporated Product Folder Links: UCD90320 UCD90320 www.ti.com SLUSCH8C – AUGUST 2016 – REVISED MAY 2020 Figure 24. Pin Selected States Configuration Window (Global Configuration ►Pin Selected Rail States) 8.4.8 Watchdog Timer The UCD90320 device provides a watchdog timer (WDT). The WDT can be reset by toggling a watchdog input (WDI) pin. If WDI is not toggled within a programmed period, the WDT times out. As a result, a watchdog output (WDO) pin is asserted (generates a pulse) to provide a system-reset signal. The WDI and WDO pins are GPIO pins and are only optional. The WDI can be replaced by SYSTEM_WATCHDOG_RESET command sent over PMBus. The WDO can be manifested through the Boolean Logic defined GPOs, or its function can be integrated into the system reset pin (RESET) configured in the system reset function. See the System Reset Function section. The WDT timer is programmable from 0.001 s to 258.048 s. See also the UCD90320 Sequencer and System Health Controller PMBus Command Reference user guide for details on configuring the watchdog timer. After a timeout, the WDT can be restarted by toggling the WDI pin or by writing SYSTEM_WATCHDOG_RESET command over PMBus. Figure 25 shows the watchdog timing waveforms. WDI