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UCD9081
SLVS813C – JUNE 2008 – REVISED NOVEMBER 2016
UCD9081 8-Channel Power Supply Sequencer and Monitor With Error Logging
1 Features
2 Applications
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Single Supply Voltage: 3.3 V
Low Power Consumption: 3-mA Nominal Supply
Current
Sequences and Monitors Eight Voltage Rails
Rail Voltages Sampled With 3.2-mV Resolution
Internal or External Voltage Reference
Four Configurable Digital Outputs for Power-OnReset and Other Functions
Configurable Digital Output Polarity
Flexible Rail Sequencing Based on Timeline (ms),
Parent Rail Regulation Window, or Parent Rail
Achieving Defined Threshold
Independent Under- and Overvoltage Thresholds
Per Rail
Configurable Regulation Expiration Times Per Rail
Flexible Alarm Processing: Ignore, Log Only,
Retry n Times, Retry Continuously, Sequence,
Parent Rail Can Shutdown Child Rails
Alarm Conditions Logged With Timestamp: Underand Overvoltage Glitch, Sustained Under- and
Overvoltage, Rail Did Not Start
On-Chip Flash for Storing User Data
Error Logging to Flash for System Failure Analysis
I2C™ Interface for Configuration and Monitoring
Microsoft Windows™ GUI for Configuration and
Monitoring
Oscillator
Analog
Inputs
10-bit
SAR ADC
Sequencing
Engine
The UCD9081 power-supply sequencer controls the
enable sequence of up to eight independent voltage
rails and provides four general-purpose digital outputs
(GPO). The device operates from a 3.3-V supply,
provides 3.2-mV resolution of voltage rails, and
requires no external memory or clock. The UCD9081
monitors the voltage rails independently and has a
high degree of rail sequence and alarm response
options. The sequencing of rails can be based on
timed events or on timed events in conjunction with
other rails achieving regulation or a voltage threshold.
In addition, each rail is monitored for undervoltage
and overvoltage glitches and thresholds. Each rail the
UCD9081 monitors can be configured to shut down a
user-defined set of other rails and GPOs, and alarm
conditions are monitored on a per-rail basis.
Figure 20 shows the UCD9081
sequencer in a typical application.
Power
Enables
GeneralPurpose
Outputs
EN8/GPO1
GPO2
GPO3
GPO4
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
MON [1:8]
VOUT1
10 kW
3.3 V
EN [1:7]
RST
0.01 mF
3.3 V
EN
Power
Supply
1
EN
Power
Supply
2
EN
Power
Supply
X
XIN
VOUT2
TEST
UCD 9081
100 kW
3.3 V
Status
Registers
power-supply
Device Information(1)
UCD9081
EN1
EN2
EN3
EN4
EN5
EN6
EN7
Config
Memory
3 Description
PART NUMBER
Functional Block Diagram
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
Telecommunications Switches
Servers
Networking Equipment
Test Equipment
Industrial
Any System Requiring Sequencing of Multiple
Voltage Rails
VCC
ROSC
10 kW
3.3 V
Error Log
Flash
Memory
3.3 V
1 mF
SCL
10 kW
3.3 V
VSS
SDA
EN8/
ADDR1/
GPO1
2
To I C
Master Device
ADDR2/ ADDR3/
GPO3
GPO2
VOUTX
ADDR4/
GPO4
3.3 V
2
I C
Engine
2
Slave I C
Address
A1
A2
A3
A4
Digital
Outputs
Copyright © 2016, Texas Instruments Incorporated
SCL
SDA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD9081
SLVS813C – JUNE 2008 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements: I2C Interface..........................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
8.5 Programming........................................................... 14
8.6 Register Maps ......................................................... 18
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2010) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 5
•
Moved Timing Parameters for I2C Interface table and I2C Timing diagram to Specifications................................................ 6
•
Moved content in Monitoring the UCD9081 to Register Maps ............................................................................................. 18
Changes from Revision A (September 2008) to Revision B
Page
•
Added Note 1 to the PIN FUNCTIONS table ......................................................................................................................... 3
•
Added Note regarding state of enable and digital I/O pins when the device contains factory configuration ....................... 15
•
Added a reference to the UCD9081 Programming Guide.................................................................................................... 16
Changes from Original (June 2008) to Revision A
Page
•
Changed the data sheet from Product Preview to Production; multiple changes throughout................................................ 1
•
Changed first RAIL voltage equation From: × VREF To: × VR+ ............................................................................................. 19
•
Changed second RAIL voltage equation From: × VREF To: × VR+ ....................................................................................... 19
2
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SLVS813C – JUNE 2008 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
ROSC
NC
VCC
TEST
ADDR4/GPO4
ADDR3/GPO3
ADDR2/GPO2
EN8/ADDR1/GPO1
32
31
30
29
28
27
26
25
RHB Package
32-Pin VQFN
Top View
VSS
1
24
EN2
NC
2
23
EN1
XIN
3
22
SCL
NC
4
21
SDA
RST
5
20
NC
MON1
6
19
MON5
MON2
7
18
MON4
MON3
8
17
NC
9
10
11
12
13
14
15
16
MON6
EN4
EN3
EN5
EN6
EN7
MON7
MON8
PowerPAD
Not to scale
Pin Functions
PIN (1)
NAME
NO.
I/O
DESCRIPTION
ADDR2/GPO2
26
I/O
I2C address select 2, general-purpose digital output 2
ADDR3/GPO3
27
I/O
I2C address select 3, general-purpose digital output 3
ADDR4/GPO4
28
I/O
I2C address select 4, general-purpose digital output 4
EN1
23
I/O
Voltage rail 1 enable (digital output)
EN2
24
I/O
Voltage rail 2 enable (digital output)
EN3
11
I/O
Voltage rail 3 enable (digital output)
EN4
10
I/O
Voltage rail 4 enable (digital output)
EN5
12
I/O
Voltage rail 5 enable (digital output)
EN6
13
I/O
Voltage rail 6 enable (digital output)
EN7
14
I/O
Voltage rail 7 enable (digital output)
EN8/ADDR1/
GPO1
25
I/O
Voltage rail 8 enable (digital output), I2C address select 1, general-purpose digital output 1
MON1
6
I
Analog input for voltage rail 1
MON2
7
I
Analog input for voltage rail 2
MON3
8
I
Analog input for voltage rail 3
MON4
18
I
Analog input for voltage rail 4
(1)
Enable and GPIO pins are in high-impedance state when a device is received from factory and during the first configuration
programming done by customer.
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SLVS813C – JUNE 2008 – REVISED NOVEMBER 2016
www.ti.com
Pin Functions (continued)
PIN
(1)
I/O
DESCRIPTION
NAME
NO.
MON5
19
I
Analog input for voltage rail 5
MON6
9
I
Analog input for voltage rail 6
MON7
15
I
Analog input for voltage rail 7
MON8
16
I
Analog input for voltage rail 8
NC
2
—
Do not connect
NC
4, 17,
20, 31
—
Recommended to connect to VSS, pin is not connected internally
ROSC
32
—
Internal oscillator frequency adjust. Must use 100-kΩ pullup to VCC for minimum drift and maximum
frequency when sampling voltage rails.
RST
5
I
SCL
22
I/O
I2C clock. Must pull up to 3.3 V.
SDA
21
I/O
I2C data. Must pull up to 3.3 V.
TEST
29
I
Connect to VSS
VCC
30
—
Supply voltage
VSS
1
—
Ground reference
XIN
3
—
Connect to VCC
PowerPAD™
—
—
Package pad. Recommended to connect to VSS.
4
Reset input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage applied from VCC to VSS
Voltage applied to any pin
(2)
MIN
MAX
UNIT
–0.3
4.1
V
–0.3
VCC + 0.3
V
±2
mA
85
°C
ESD diode current at any device terminal
Storage temperature, Tstg
(1)
(2)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
6.2 Recommended Operating Conditions
VCC
Supply voltage during operation and configuration changes
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
V
85
°C
–40
UNIT
6.3 Thermal Information
UCD9081
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
32.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.1
°C/W
RθJB
Junction-to-board thermal resistance
6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics
These specifications are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IS
Supply current into VCC
TA = 25°C, excluding external current
3
4
mA
IC
Supply current during configuration
VCC = 3.6 V
3
7
mA
STANDARD INPUTS (RST, TEST)
VIL
Low-level input voltage
VCC = 3 V
VSS
VSS + 0.6
V
VIH
High-level input voltage
VCC = 3 V
0.8 × VCC
VCC
V
SCHMITT TRIGGER INPUTS (SDA, SCL, EN[1...7], EN8/ADDR1, ADDR[2...4])
VIT+
Positive-going input threshold voltage
VCC = 3 V
1.5
1.9
V
VIT–
Negative-going input threshold voltage
VCC = 3 V
0.9
1.3
V
Vhys
Input voltage hysteresis
VCC = 3 V, VIT+ – VIT–
0.5
1
V
Ilkg
High-impedance leakage current
±50
nA
V
ANALOG INPUTS (MONx, ROSC)
VCC
Analog supply voltage
VMON
Analog input voltage
VSS = 0 V
3
3.6
Internal voltage reference selected
0
2.5
External voltage reference selected
(VCC used as reference)
0
VCC
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SLVS813C – JUNE 2008 – REVISED NOVEMBER 2016
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Electrical Characteristics (continued)
These specifications are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
CI
(1)
Input capacitance
Only one terminal can be selected at a time
(MON1 to MON8)
RI
(1)
Input MUX ON resistance
0 V ≤ VMONx ≤ VCC, VCC = 3 V
Ilkg
High-impedance leakage current
MON1 to MON8
VREF+
Positive internal reference voltage
Internal voltage reference selected,
VCC = 3 V
VTUE
ADC total unadjusted error
Temperature coefficient of internal voltage
reference
TREF+ (1)
VCC = 3 V
MIN
TYP
MAX
27
2.35
2.5
UNIT
pF
2000
Ω
±50
nA
2.65
V
VR+ = 2.5 V
(internal reference)
±12.2
VR+ = VCC
(external reference)
±14.7
mV
I(VREF+) is a constant in the range of
0 mA ≤ I(VREF+) ≤ 1 mA, VCC = 3 V
±100
ppm/°C
MISCELLANEOUS
Tretention
Retention of configuration parameters
TJ = 25°C
100
Years
POR, BROWNOUT, RESET (2) (3)
td(BOR)
Brownout
VCC(start)
Brownout
dVCC/dt ≤ 3 V/s
V(B_IT–)
Brownout
dVCC/dt ≤ 3 V/s
Vhys(B_IT–)
Brownout
dVCC/dt ≤ 3 V/s
Brownout
Pulse length required at RST pin to accept
reset internally, VCC = 3 V
t(reset)
2000
0.7 × V(B_IT–)
70
130
µs
V
1.71
V
180
mV
2
µs
DIGITAL OUTPUTS (EN8/GPO1, GPO[2...4], EN[1...7], SDA, SCL)
VOH
High-level output voltage
VOL
Low-level output voltage
Ilkg
High-impedance leakage current
(1)
(2)
(3)
(4)
(5)
IOHmax = –1.5 mA (4), VCC = 3 V
VCC – 0.25
VCC
IOHmax = –6 mA (5), VCC = 3 V
VCC – 0.6
VCC
IOLmax = 1.5 mA (4), VCC = 3 V
VSS
VSS + 0.25
IOLmax = 6 mA (5), VCC = 3 V
VSS
VSS + 0.6
VCC = 3 V
±50
V
V
nA
Not production tested. Limits verified by design.
The current consumption of the brown-out module is already included in the ICC current consumption data.
During power up, device initialization starts following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–).
The maximum total current, IOHmax and IOLmax, for all outputs combined, must not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOHmax and IOLmax, for all outputs combined, must not exceed ±48 mA to hold the maximum voltage drop
specified.
6.5 Timing Requirements: I2C Interface
MIN
MAX
UNIT
tofof
Output fall time from VOH to VOL (1) with a bus capacitance from 10 pF to 400 pF
CI
Capacitance for each pin
fSCL
SCL clock frequency
tHD;STA
Repeated hold time START condition (after this period, the first clock pulse is generated)
tHD;DAT
Data hold time
0 (3)
tLOW
LOW period of the SCL clock
4.7
µs
tHIGH
HIGH period of the SCL clock
4
µs
tSU;STA
Setup time for repeated start condition
4.7
µs
tSU;DAT
Data setup time
250
ns
(1)
(2)
(3)
(4)
6
10
250 (2)
ns
10
pF
100
kHz
4
µs
3.45 (4)
µs
See Electrical Characteristics
The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This
allows series protection resistors, Rs , to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the
maximum specified tf.
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
The maximum tHD;DAT must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
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Timing Requirements: I2C Interface (continued)
MAX
UNIT
tr
Rise time of both SDA and SCL signals
MIN
1000
ns
tf
Fall time of both SDA and SCL signals
300
ns
tSU;STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
C(b)
Capacitive load for each bus line
VnL
Noise margin at the LOW level for each connected device (including hysteresis)
0.1 × VDD
V
VnH
Noise margin at the HIGH level for each connected device (including hysteresis)
0.2 × VDD
V
4
µs
4.7
µs
400
pF
SDA
tf
tLOW
tSU;DAT
tHD;STA
tr
tr
tBUF
tof
SCL
tHIGH
tHD;STA
tSU;STA
tHD;DAT
tSU;STO
Sr
S
P
S
Figure 1. Timing Diagram for I2C Interface
6.6 Typical Characteristics
50
0
VCC = 3 V
P1.0
IOH − Typical High-Level Output Current − mA
IOL − Typical Low-Level Output Current − mA
Digital outputs (only one output is loaded at a time)
o
TA = 25 C
40
o
TA = 85 C
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
VCC = 3 V
P1.0
−10
−20
−30
−40
o
TA = 85 C
−50
−60
o
TA = 25 C
0
0.5
VOL − Low-Level Output Voltage − V
Figure 2. Typical Low-Level Output Current
vs Low-Level Output Voltage
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
Figure 3. Typical High-Level Output Current
vs High-Level Output Voltage
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7 Parameter Measurement Information
VCC
Vhys(B_IT–)
V(B_IT–)
VCC(start)
1
Set signal for
POR circuitry
0
td(BOR)
Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
2
VCC = 3 V
tpw
3V
Typical Conditions
VCC(min) - V
1.5
1
VCC(min)
0.5
0
0.001
1000
1
1 ns
tpw - Pulse Width - mS
1 ns
tpw - Pulse Width - mS
Figure 5. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
tpw
3V
VCC(min) - V
VCC = 3 V
1.5
Typical Conditions
1
VCC(min)
0.5
tfall = trise
0
0.001
1
1000
tpw - Pulse Width - mS
tfall
trise
tpw - Pulse Width - ms
Figure 6. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
8
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8 Detailed Description
8.1 Overview
Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, and so forth, can have multiple voltage
rails and require certain power on and off sequences to function correctly. The UCD9081 device can control up
to 8 voltage rails and ensure correct power sequences during normal condition and fault conditions.
In addition to sequencing, UCD9081 can continuously monitor rail voltages, fault conditions, and report the
system health information to a I2C host, improving the long-term reliability of the system.
Also, UCD9081 can protect electronic systems by responding to power system faults. The fault responses are
conveniently configured by users through PC-based GUI. Fault events are stored in on-chip nonvolatile flash
memory to assist failure analysis.
The UCD9081 can control up to four general-purpose digital outputs through the same sequencing mechanisms
as the power supply enables, which can be used for digital signals for other devices.
8.2 Functional Block Diagram
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
Oscillator
Analog
Inputs
10-bit
SAR ADC
Status
Registers
Sequencing
Engine
Power
Enables
EN1
EN2
EN3
EN4
EN5
EN6
EN7
GeneralPurpose
Outputs
EN8/GPO1
GPO2
GPO3
GPO4
Config
Memory
Error Log
Flash
Memory
2
I C
Engine
SCL
SDA
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8.3 Feature Description
8.3.1 Rail Configuration
A rail includes voltage monitoring pin, a power-supply enable. UCD9081 can support up to 8 rails. Once the
assigned rail is selected, other key monitoring and sequencing criteria are selected for each rail from rail
configuration:
• Enable pin polarity
• Undervoltage (UV) and overvoltage (OV) fault limits
• Maximum time allowed before an alarm is declared
• Maximum time allowed achieving regulation (voltage between UV or OV range)
• Masks glitches from error log windows
• Log errors to flash
• Sequence after shutdown
• Voltage divider
• Sequence conditions selections
• Alarm actions
Figure 7. GUI Rail Configuration
8.3.2 Graphical User Interface (GUI)
UCD9081 designer is provided for device configuration. This PC-based graphical user interface (GUI) offers an
intuitive I2C interface to the device. It allows the design engineer to configure the system operating parameters
for the application without directly using I2C commands, store the configuration to on-chip nonvolatile memory,
and observe system status (voltage, and so forth). The UCD9081 GUI can be downloaded from www.ti.com in
the product folder.
10
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8.4 Device Functional Modes
8.4.1 Power Supply Sequencing
The UCD9081 can be configured to sequence power supply rails using the enable signals (ENx) or the generalpurpose outputs (GPOx) in one of four ways:
1. A rail can be configured to not be sequenced
2. Using a delay time after UCD9081 RESET. The enable or GPO is asserted after UCD9081 RESET plus the
user specified delay
3. Using a delay time after another (parent) rail has achieved regulation (VRAIL is within specified under- and
overvoltage settings). The enable or GPO is asserted after the (parent) rail is in regulation plus the user
specified delay.
4. Using a (parent) rail voltage. The enable or GPO is asserted after the (parent) rail voltage is greater than or
equal to the user specified voltage.
8.4.2 Power-Supply Enables
The UCD9081 can sequence and enable or disable up to eight power supplies through the ENx (EN1 to EN8)
signals. These signals can be configured active-high or active-low, supporting power supplies with either polarity.
EN8 can also be configured as a GPO (GPO1). EN8/ADDR1/GPO1 is also used for I2C address selection
(ADDR1).
While the UCD9081 is in RESET, the enable signals are in a high-impedance state. The enable signals must be
pulled up or down on the board according to the desired default power-supply state (enabled or disabled).
8.4.3 General-Purpose Outputs
The UCD9081 can control up to four general-purpose digital outputs through the same sequencing mechanisms
as the power supply enables. These general-purpose outputs (GPO1–GPO4) can be used for digital signals such
as resets or status inputs to other devices. These signals are multiplexed with other functions (primarily I2C
address selection). See Pin Configuration and Functions to ensure that these signals are used properly by the
application. The GPO1 signal is also multiplexed with EN8.
8.4.4 Device Reset
UCD9081 RESET occurs due to one of the following conditions:
•
•
•
•
External RST pin is asserted
Power is applied to the device (power-on-reset) or power is cycled
A sequence event occurs as a result of a configured rail alarm event
RESTART command is issued over the I2C bus
During RESET, the following takes place:
•
•
•
•
•
•
All ENx and GPOx pins are placed in a high-impedance state
All internal timers are reset to zero
The I2C address pins (ADDR1-ADDR4) are sampled and the device address is assigned accordingly
All ENx and GPOx pins are driven to their inactive levels
The UCD9081 runs a checksum function to validate its memory contents
If there are no errors, the device starts sequencing according to the current sequencer configuration
During this time, the UCD9081 does not respond to host requests made over the I2C bus.
To ensure the integrity of data within the device, the device runs a checksum function during RESET. If the
configuration parameters of the device are valid, the UCD9081 begins operating according to the current
sequencer configuration. If the configuration parameters are invalid, the UCD9081 overwrites the current
configuration parameters with the last known good configuration and the device begins operating with these
parameters. This can cause a delay in the RESET time. To establish a copy of the valid configuration, UCD9081
RESET time is delayed the first time a new configuration is loaded.
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Device Functional Modes (continued)
8.4.5 Voltage Reference
The analog to digital converter in the UCD9081 has a selectable voltage reference, VR+. The voltage reference
can either be an internally generated 2.5-V reference or an external reference derived from VCC. The external
reference is recommended for those systems requiring more accurate voltage readings. See Estimating
UCD9081 Reporting Accuracy Over Variations in ADC Voltage Reference for information on calculating the
accuracy of each reference.
8.4.6 Voltage Monitoring
The UCD9081 can monitor eight voltage rails through the MONx terminals of the device (MON1 to MON8). The
UCD9081 samples these eight input channels and uses the selected reference to convert the voltages to digital
values. These values are accessible through the I2C interface. When monitoring a voltage rail that has a nominal
voltage larger than the selected reference, a resistor divider network is typically used. The design must ensure
that the source impedance of the resistor network is chosen properly to maintain the accuracy of the analog to
digital conversion. For more details, see Application Information.
The UCD9081 allows the user to independently specify the following for each monitored rail:
•
•
•
•
overvoltage (OV) threshold
undervoltage (UV) threshold
out of regulation time or glitch width (OORW)
maximum time for regulation (MTFR)
The MTFR is used to determine whether or not a rail starts successfully after being enabled.
The UCD9081 also has the ability to ignore glitches. Glitches are fault conditions that last less than the specified
OORW for that rail. Ignoring glitches may be useful in the case where the power supply is known to be noisy but
still operates well. Ignoring glitches does not affect the monitoring capability of the UCD9081 with respect to
detecting sustained UV or OV faults. It simply prevents the UCD9081 from logging glitch faults to the error log.
8.4.7 Rail Shutdown
Rail (or GPO) shutdown is the act of setting the ENx (or GPOx) pin to a state which disables the associated
power supply output. A rail can shutdown for one of the following reasons:
•
•
•
A fault condition on the rail itself
A fault condition on a parent rail resulting in a shutdown
An I2C shutdown command
Each rail and GPO can be independently configured to shutdown according to a user-specified time delay from
0 ms to 4095 ms. This is referred to as the system shutdown configuration.
8.4.8 Alarm Processing
Each rail can be independently configured to respond to an alarm or fault in a variety of ways. A fault can be an
UV condition, OV condition, or a rail that did not start (MTFR exceeded before UV threshold achieved). The
options for alarm processing are as follows:
• Ignore
• Log only
• Retry n times (n = 0,1,2,3,4)
• Retry continuously
• Sequence (immediately)
• Sequence after shutdown
In addition to these options, a rail can be independently configured to log errors to FLASH to aid in failure
analysis. For more details, see Error Logging.
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Device Functional Modes (continued)
8.4.8.1 Ignore
The UCD9081 can be configured to ignore all alarms on the rail. This is the recommended option for all unused
power supply rails on the UCD9081.
8.4.8.2 Log Only
The UCD9081 can be configured to log a fault and take no additional action. For more information, see Error
Logging.
8.4.8.3 Retry n Times
The UCD9081 can be configured to attempt to restart a rail up to n times (n = 0,1,2,3, or 4) in response to a
sustained fault condition. With this option, the user can also specify which rails and GPOs are dependent upon
the configured rail. When a sustained fault is detected, the faulty rail is disabled and re-enabled the desired
number of times. The rail remains enabled for the specified MTFR before attempting another retry. If the rail does
not achieve regulation after the desired number of retries, all user-specified dependent rails and GPOs are
shutdown according to the times specified in the system shutdown configuration. If any of the dependent rails
have other rails or GPOs marked as dependents, those dependent rails or GPOs are also forced to shutdown
regardless of their alarm processing configurations.
8.4.8.4 Retry Continuously
The UCD9081 can be configured to continuously attempt to restart a faulty rail. When the UCD9081 detects a
sustained fault condition on the configured rail, the rail is disabled and then re-enabled. The rail remains enabled
for the specified MTFR. The retry process repeats for this rail until it properly achieves regulation.
8.4.8.5 Sequence
The UCD9081 can be configured to sequence the entire system in response to a sustained fault condition. When
the UCD9081 detects a fault on the configured rail, all rails and GPOs are shutdown immediately and UCD9081
RESET occurs (see Device Reset). For this configuration, a shutdown according to the delay times specified by
the system shutdown configuration does not occur prior to UCD9081 RESET.
8.4.8.6 Sequence After Shutdown
Sequence after shutdown is an option that can be used in conjunction with Retry n Times. When a fault occurs
on the configured rail, this option forces a UCD9081 RESET to occur after the procedure outlined in Retry n
Times takes place. If a rail is configured for sequence after shutdown and is forced to shutdown due to a fault on
a parent rail, a sequence after shutdown takes place.
8.4.9 Error Logging
The UCD9081 is capable of logging errors in two ways. The first method uses an eight-deep FIFO located in
volatile memory (SRAM) of the UCD9081. Error conditions are posted to the ERROR registers according to the
configuration for that rail. The UCD9081 logs the type of error, the time (from Reset) when the error occurred, the
rail number, and the rail voltage. If the user has specified ignore glitches as an option for the faulty rail, glitches
are not posted to the error log. If the user has specified Ignore as the alarm response for the faulty rail, no errors
are posted to the error log for that rail. All other alarm responses result in the error condition being logged. Due
to the unknown latency of the host extracting data from the FIFO, the UCD9081 only posts to the FIFO is if it has
room to write. There is no impact to the monitoring operation of the UCD9081 if this FIFO is full and cannot be
written.
The second method of error logging uses the non-volatile memory (FLASH) of the UCD9081. Similar to the error
log in SRAM, faults are posted for all rails that have the appropriate alarm processing options selected. In this
case, errors are posted to both the SRAM log and the FLASH log. The UCD9081 is capable of recording up to
eight entries in the flash error log. Again, the UCD9081 only posts to the log if there is room to write. There is no
impact to the monitoring operation of the UCD9081 if the error log is full and cannot be written.
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Device Functional Modes (continued)
To provide flexibility for a variety of systems, the UCD9081 has two modes for non-volatile error logging. The first
mode configures the UCD9081 to hold in RESET when entries are present in the FLASH error log. This is
advantageous in systems where a master I2C device is available to read the error log following a critical system
failure. When configured for this mode, the UCD9081 checks for a non-empty FLASH error log during RESET. If
there are entries in the FLASH error log, the device waits for a host to clear the error log before sequencing the
device. For information on clearing the FLASH error log, see the section on Resetting the Flash Error Log.
The second mode allows the UCD9081 to sequence (following a RESET of the device) regardless of whether or
not there are entries present in the FLASH error log. This is useful in systems with no master I2C device, or
where power cycles are common and not due to system failure.
For information on reading the error logs in each mode, see Register Maps.
8.4.10 Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
8.5 Programming
8.5.1 I2C Interface
The UCD9081 power-supply sequencer has a 100 kHz, slave mode I2C interface for communication with an I2C
master. The I2C master uses this interface to configure and monitor the UCD9081. The master must support
clock stretching to properly communicate with the UCD9081.
8.5.2 Configuring and Monitoring the UCD9081
The UCD9081 supports both configuration and monitoring using its I2C slave interface. A Microsoft Windows™
GUI is available for configuring and monitoring the UCD9081. This GUI can be downloaded from the TI website
at www.ti.com.
For monitoring the sequencer, an I2C memory map allows an I2C host to perform memory-mapped reads (and in
some cases writes) to obtain status information from the UCD9081. For instance, all rails can report their voltage
through the I2C memory map. For information on which parameters are available through the I2C memory map,
see Register Maps.
To change configuration parameters of the sequencer, a different mechanism is used. The entire set of
configuration parameters must be written at one time to the device as one large transaction over the I2C
interface. This ensures that the configuration of the device is consistent at any given time. The process for
configuring the UCD9081 is described in Configuring the UCD9081.
The UCD9081 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP family as well as ASICs.
The UCD9081 is available in a plastic 32-pin VQFN package (RHB).
8.5.3 Resetting the Flash Error Log
The UCD9081 can be configured to log errors on a critical voltage rail to internal FLASH memory. This
mechanism permits the error log to be read after the device has been reset, or if a loss of power causes nonvolatile memory to be cleared. As outlined in Error Logging, there are two modes for using this feature.
The first mode holds the UCD9081 in RESET (following a RESET of the device) if entries are present in the
FLASH error log. This allows the user to successfully read and clear the FLASH error log before sequencing the
system. When using this mode, the UCD9081 does not sequence until the FLASH error log is cleared. To clear
the FLASH error log and sequence the device, perform the following steps:
•
•
•
•
•
•
14
Write
Write
Write
Write
Write
Write
FLASHLOCK register to a value of 0x02
WADDR register to a value of 0x1000
WDATA register to a value of 0xBADC
WADDR register to a value of 0x107E
WDATA register to a value of 0xBADC
FLASHLOCK register to a value of 0x00
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Programming (continued)
•
Write RESTART register to a value of 0x00
The second mode allows the UCD9081 to sequence (following a RESET of the device) regardless of whether or
not there are entries present in the FLASH error log. When using this mode, the user still may wish to clear the
FLASH error logs some time after RESET. To do this, perform the following steps:
•
•
•
•
•
•
Write
Write
Write
Write
Write
Write
FLASHLOCK register to a value of 0x02
WADDR register to a value of 0x1000
WDATA register to a value of 0xBADC
WADDR register to a value of 0x107E
WDATA register to a value of 0xBADC
FLASHLOCK register to a value of 0x00
Clearing the FLASH error log during run-time causes a delay in monitoring.
8.5.4 Configuring the UCD9081
The UCD9081 has many different configurable parameters such as sequencing options, alarm processing
options, and rail dependencies. A Microsoft Windows™ GUI is available for selecting and generating the
necessary configuration parameters. The UCD9081 GUI can be downloaded from www.ti.com in the product
folder. See UCD9081 EVM User's Guide (SLVU249) for details on installing and using the GUI. Once the userspecific configuration parameters are selected, the GUI generates a hex file that can be loaded into the flash
memory of the UCD9081 through the I2C interface.
NOTE
Because loading a new configuration requires writing to FLASH memory, the UCD9081
does not monitor the MONx inputs while the configuration parameters are being updated.
NOTE
The enable and digital I/O pins of the UCD9081 are in a high impedance state when the
device is not configured (Texas instruments delivers the device in this state).
To download the configuration parameters generated by the GUI into the UCD9081, a contiguous block of
configuration information is sent to the device through the I2C interface. This block is 512 bytes long and starts at
address 0xE000.
This 512-byte block of configuration information is sent to the device in multiple segments. The segment size can
range from 2 to 32 bytes at one time, and must be a multiple of 2 bytes. That is, a master can send 256 2-byte
segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper
sequence, and this operation must be completed by sending the last segment so that the last byte of the
512-byte block is written. If this is not done, the UCD9081 is in an unknown state and does not function as
designed.
The process for sending the configuration information to the UCD9081 is as shown in Figure 8.
I2C Write:
FLASHLOCK =
UNLOCK (0x02)
I2C Write:
WADDR =
0xE000
I2C Write:
WDATA =
0xBADC
I2C Write:
WADDR =
0xE000
I2C Write:
WDATA =
Data (16b)
...
I2C Write:
WDATA =
Data (16b)
I2C Write:
FLASHLOCK =
LOCK (0x00)
Up to 16 times (32 bytes)
- OR Repeat as necessary with WADDR updated
to write 512 bytes
Figure 8. Configuration Information
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Programming (continued)
As
1.
2.
3.
4.
5.
shown in Figure 8, the process for updating the configuration of the UCD9081 is as follows:
Unlock flash memory by writing the value 0x02 to the FLASHLOCK register
Write the address of the configuration section of memory (WADDR = 0xE000)
Write the constant 0xBADC to update memory (WDATA = 0xBADC)
Write the address of the configuration section of memory again (WADDR = 0xE000)
Write the data (WDATA = ). Repeat steps 4 and 5 as necessary, depending on the data segment
size used, to write 512 bytes. Increment the address as necessary.
6. Lock flash memory after the last byte of the last segment is written by writing the value 0x00 to the
FLASHLOCK register
At the conclusion of this process, the configuration of the UCD9081 is updated with the configuration changes, as
represented by the values from the data segments. See UCD9081 Programming Guide (SLVA275) for more
details on programming the UCD9081.
8.5.5 User Data
User data (128 bytes) can be stored in the UCD9081 FLASH memory at location 0x1080 to 0x10FF. Writes to
the User Data section of memory are performed as follows:
1.
2.
3.
4.
5.
Unlock flash memory by writing the value 0x02 to the FLASHLOCK register
Write the address of the USER DATA section of memory (WADDR = 0x1080)
Write the constant 0xBADC to update memory (WDATA = 0xBADC)
Write the address of the USER DATA section of memory again (WADDR = 0x1080)
Write the data (WDATA = ). Repeat steps 4 and 5 as necessary depending on the data segment
size used. Increment the address as necessary.
6. Lock flash memory after the last byte of the last segment is written by writing the value 0x00 to the
FLASHLOCK register
To read the User Data section of memory, follow the procedure for reading memory outlined in WADDR and
WDATA.
8.5.6 I2C Address Selection
The UCD9081 supports 7-bit I2C addressing. The UCD9081 selects an I2C address by sampling the logic level of
the four digital inputs to the device (ADDR1–ADDR4) during the RESET interval. When the UCD9081 is released
from RESET, the ADDRx logic levels are latched and the I2C address is assigned as shown in Figure 9.
A7 = 1
A6 = 1
A5 = 0
A4 = ADDR4/GPO4
A3 = ADDR3/GPO3
A2 = ADDR2/GPO2
A1 = EN8/ADDR1/GPO1
2
Figure 9. I C Address = 0x60–0x6F
External pullup or pulldown resistors are required to configure the I2C address; the UCD9081 does not have
internal bias resistors. The 7-bit I2C address refers to the address bits only, not the read/write bit in the first byte
of the I2C protocol. The base I2C address is 0x60 and the I2C general call address (0x00) is not supported.
After the initialization process of the UCD9081 is complete, these four pins can be used for general-purpose
outputs.
8.5.7 I2C Transactions
The UCD9081 can be configured and monitored through I2C memory-mapped registers. Registers that are
configurable (can be written) through an I2C write operation are implemented using an I2C unidirectional data
transfer, from the master to slave, with a stop bit between transactions.
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8.5.7.1 I2C Unidirectional Transfer
1
7
1
1
8
1
8
1
1
S
SLAVE
ADDRESS
R/W
A
REGISTER
ADDRESS
A
DATA
A/A
P
0 (write)
From master to slave
A = acknowledge (SDA low)
A
= Not acknowledge (SDA high)
S = START condition
From slave to master
P = STOP condition
Figure 10. I2C Register Access With START or STOP
Registers that can be read are implemented using an I2C read operation, which can use the I2C combined format
that changes data direction during the transaction. This transaction uses an I2C repeated START during the
direction change.
8.5.7.2 I2C Combined Format
1
S
7
1
SLAVE
ADDRESS R/W
1
A
8
1
REGISTER
A ADDRESS
1
Sr
A
A
7
1
1
SLAVE
ADDRESS R/W
A
A
8
1
1
DATA
A/A
P
DATA
(n bytes +
acknowledge)
0 (write)
1 (read)
A = acknowledge (SDA low)
From master to slave
A
= Not acknowledge (SDA high)
S = START condition
From slave to master
P = STOP condition
Sr = Repeated START
Figure 11. I2C Register Access With Repeated START
The UCD9081 also supports a feature that auto-increments the register address pointer for increased efficiency
when accessing sequential blocks of data. It is not necessary to issue separate I2C transactions.
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8.6 Register Maps
The UCD9081 allows all monitoring of the system through the I2C interface on the device. The following is the
memory map of the supported registers in the system. The detail of each of these registers is given in the next
section as well.
The UCD9081 supports functionality to increment the I2C register address value automatically when a register is
being accessed to more efficiently access blocks of like registers. Table 1 also shows the amount that the
register address is incremented for each register access.
Table 1. Register Access Adjustment
REGISTER NAME
ADDRESS
ACCESS
ADJUSTMENT AFTER ACCESS
RAIL1H
0x00
r
+1 (0x01)
RAIL1L
0x01
r
+1 (0x02)
RAIL2H
0x02
r
+1 (0x03)
RAIL2L
0x03
r
+1 (0x04)
RAIL3H
0x04
r
+1 (0x05)
RAIL3L
0x05
r
+1 (0x06)
RAIL4H
0x06
r
+1 (0x07)
RAIL4L
0x07
r
+1 (0x08)
RAIL5H
0x08
r
+1 (0x09)
RAIL5L
0x09
r
+1 (0x0A)
RAIL6H
0x0A
r
+1 (0x0B)
RAIL6L
0x0B
r
+1 (0x0C)
RAIL7H
0x0C
r
+1 (0x0D)
RAIL7L
0x0D
r
+1 (0x0E)
RAIL8H
0x0E
r
+1 (0x0F)
RAIL8L
0x0F
r
–15 (0x00)
ERROR1
0x20
r
+1 (0x21)
ERROR2
0x21
r
+1 (0x22)
ERROR3
0x22
r
+1 (0x23)
ERROR4
0x23
r
+1 (0x24)
ERROR5
0x24
r
+1 (0x25)
ERROR6
0x25
r
–5 (0x20)
STATUS
0x26
r
0 (0x26)
VERSION
0x27
r
0 (0x27)
RAILSTATUS1
0x28
r
+1 (0x29)
RAILSTATUS2
0x29
r
–1 (0x28)
FLASHLOCK
0x2E
rw
0 (0x2E)
RESTART
0x2F
w
0 (0x2F)
WADDR1
0x30
rw
+1 (0x31)
WADDR2
0x31
rw
–1 (0x30)
WDATA1
0x32
rw
+1 (0x33)
WDATA2
0x33
rw
–1 (0x32)
8.6.1 Register Descriptions
The following are the detailed descriptions of each of the UCD9081 I2C registers.
The following register bit conventions are used. Each register is shown with a key indicating the accessibility of
each bit, and the initial condition after device initialization.
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8.6.2 RAIL
For each of eight voltage rails, the UCD9081 has two registers that contain the rolling average voltage for the
associated rail as measured by the device. This average voltage is maintained in real-time by the UCD9081 and
is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One holds the
least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage. This is shown in
Table 2.
Table 2. RAIL Register
REGISTER NAME
ADDRESS
RAIL1H
0x00
RAIL1 voltage, bits 9:8
REGISTER CONTENTS
RAIL1L
0x01
RAIL1 voltage, bits 7:0
RAIL2H
0x02
RAIL2 voltage, bits 9:8
RAIL2L
0x03
RAIL2 voltage, bits 7:0
RAIL3H
0x04
RAIL3 voltage, bits 9:8
RAIL3L
0x05
RAIL3 voltage, bits 7:0
RAIL4H
0x06
RAIL4 voltage, bits 9:8
RAIL4L
0x07
RAIL4 voltage, bits 7:0
RAIL5H
0x08
RAIL5 voltage, bits 9:8
RAIL5L
0x09
RAIL5 voltage, bits 7:0
RAIL6H
0x0A
RAIL6 voltage, bits 9:8
RAIL6L
0x0B
RAIL6 voltage, bits 7:0
RAIL7H
0x0C
RAIL7 voltage, bits 9:8
RAIL7L
0x0D
RAIL7 voltage, bits 7:0
RAIL8H
0x0E
RAIL8 voltage, bits 9:8
RAIL8L
0x0F
RAIL8 voltage, bits 7:0
A rail voltage is read with a 16b access. The auto-increment feature of the UCD9081 allows multiple rail voltages
to be read with a single access.
A rail voltage is provided as a 10-bit binary value in an unsigned format, as shown in Figure 12.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
RAILVn
r0
r0
r0
r0
r0
r0
r
r
r
r
r
Figure 12. RAILVn Binary
The following formulas can be used to calculate the actual measured rail voltage.
Use Equation 1 for the actual measured rail voltage without an external voltage divider.
VRAILn =
RAILVn
x V
R+
1024
(1)
Use Equation 2 for the actual measured rail voltage with an external voltage divider.
VRAILn =
RAILVn
R
+ RPULLUP
x V
x PULLDOWN
R+
1024
RPULLDOWN
(2)
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8.6.3 ERROR
Error conditions are logged by the UCD9081 and are accessible to the user through reading the ERROR register.
This is a 6-byte register is shown in Figure 13.
0x20
7
6
5
4
0x21
3
2
1
0
6
5
4
3
2
1
0
Data (dependent on error code)
RAIL
Error Code
7
RAIL
Meaning
Rail #(n) – 1, RAIL = 0 through 7
Error Codes
Meaning
Data
0
0
0
0
1
1
1
1
Null alarm
Supply did not start
Sustained overvoltage detected
Sustained undervoltage detected
Overvoltage glitch detected
Undervoltage glitch detected
Reserved
Reserved
0x0000
Average voltage on rail
Average voltage on rail
Average voltage on rail
Glitch voltage level on rail
Glitch voltage level on rail
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NOTE: When error code = Null Alarm, then the Hours,
Minutes, Seconds, and Milliseconds fields are zero.
0x23
7
7
6
6
5
5
4
3
0x22
2
1
0
7
6
5
4
3
Hour
Minutes
0x25
0x24
4
3
2
1
0
7
6
5
Seconds
4
3
2
1
0
2
1
0
Milliseconds
Figure 13. ERROR Register
Faults encountered during operation post error logs as described in Error Logging. This register set is used for
reading the SRAM error log. They can also be used to read the FLASH error log when the UCD9081 is held in
RESET. If the error log is empty, the ERROR register set returns all 0's (NULL ALARM) when read.
The values in registers 0x22 through 0x25 are reset to a value of 0 during UCD9081 RESET.
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8.6.4 STATUS
STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the
UCD9081. Figure 14 shows the bit definitions.
7
6
5
4
3
IIC Error
RAIL Error
NVERRLOG
FW Error
PARAM Error
rc-0
rc-0
r
r
r
IIC Error
0
1
2
Register Status
r-0
2
2
I C PHY layer error
Meaning
No error
Invalid address
Read access error
Write access error
00
01
10
11
No I C PHY layer error
0
1
rc-0
Register
Status
Meaning
RAIL Error
0
1
Meaning
No RAIL error pending
RAIL error pending
NVERRLOG
0
1
Meaning
ERROR points to run-time error log
ERROR points to non-volatile log (if held in RESET)
and entries present in non-volatile log
FW Error
0
1
Meaning
No Error (normal operation)
Device firmware error detected, device is idle
PARAM Error
0
1
Meaning
No Error (normal operation)
Parameters invalid, last config loaded
Figure 14. STATUS Register
Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the
device is reset. Descriptions of the different errors are below.
The IICERROR bit is set when an I2C access fails. This is most often a case where the user has accessed an
invalid address or performed an illegal number of operations for a given register (for example, reading 3 bytes
from a 2-byte register). In the event of an I2C error when the IICERROR is set, bits 1:0 of the STATUS register
further define the nature of the error as shown in the preceding figure.
The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is
advised to query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The user may
then query the ERROR registers to get further information about the nature of the error condition.
The NVERRLOG bit is set to 1 upon device RESET if the UCD9081 contains entries in the FLASH error log. This
bit is the only bit that is not automatically cleared by a read of the STATUS register; this bit is only cleared during
UCD9081 RESET (if the nonvolatile error log is empty).
The FW Error bit is set to 1 if the device firmware memory contents are corrupted.
The PARAM Error bit is set to 1 if the contents of the UCD9081 configuration memory are invalid. If this occurs,
the UCD9081 loads the last known good configuration to ensure device reliability.
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8.6.5 VERSION
The VERSION register provides the user with access to the device revision of the UCD9081. The format of this
register is a nibble-based major/minor format as shown in Figure 15.
7
6
5
4
3
2
Major
r
r
1
0
r
r
Minor
r
r
r
r
Figure 15. VERSION Major/Minor Register
8.6.6 RAILSTATUS
The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to
represent the error status of the rails as indicated in Figure 16.
15
14
13
12
11
rc-0
rc-0
rc-0
rc-0
rc-0
10
9
8
7
6
5
4
3
2
1
0
RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
rc-0
rc-0
rc-0
rc-0
rc-0
RAILn Meaning
0
No alarm pending for RAILn
1
Alarm pending for RAILn
rc-0
rc-0
rc-0
rc-0
rc-0
rc-0
Figure 16. RAILSTATUS Registers
Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a single
16-bit register.
If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the
RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.
8.6.7 FLASHLOCK
The FLASHLOCK register is used to lock and unlock the configuration memory on the UCD9081 when updating
the configuration. Configuring the UCD9081 details this process.
Figure 17 shows the format for the FLASHLOCK register.
7
6
rw-0
rw-0
5
4
3
2
1
0
rw-0
rw-0
rw-0
FLASHLOCK
rw-0
rw-0
rw-0
FLASHLOCK
0x00
Lock flash (default)
0x01
Flash is being updated
0x02
Unlock flash (before configuration)
Figure 17. FLASHLOCK Register
8.6.8 RESTART
The RESTART register provides the capability for the I2C host to force a RESET or Shutdown of the UCD9081.
This is an 8-bit register, and when a value of 0x00 is written to the register, the UCD9081 RESET occurs and the
rails are re-sequenced. To respond to this I2C request properly, there is a 50-µs delay before the system is
restarted, so that the I2C ACK can take place.
When a value of 0xC0 is written to the register, all rails and GPOs are shutdown according to the time delays
specified in the system shutdown configuration. Once this procedure is complete, the UCD9081 continues
monitoring.
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8.6.9 WADDR and WDATA
To update the configuration on the UCD9081, four registers are provided. WADDR2 (address 15:8) and
WADDR1 (address bits 7:0) specify the memory address. WDATA2 (data bits 15:8) and WDATA1 (data bits 7:0)
specify the data written to or read from that memory address.
Figure 18 shows the format for the WADDR registers.
15
8 7
0
Address
rw-0x00
rw-0x00
WADDR2
(0x31)
WADDR1
(0x30)
Figure 18. WADDR Registers
To set the memory address that is accessed, write the LSB of the address to the WADDR1 register and the MSB
of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set WADDR1 =
0x34 and WADDR2 = 0x12. Because these addresses support the auto-increment feature, the user can perform
a single 16-bit write to WADDR1 to write the entire address.
Figure 19 shows the format for the WDATA registers.
15
8 7
0
Data
rw
rw
WDATA2
(0x33)
WDATA1
(0x32)
Figure 19. WDATA Registers
To set the value of the data that is written to the UCD9081, write the LSB of the data to the WDATA1 register
and the MSB of the data to the WDATA2 register. For example, to write the data 0xBEEF to the device, set
WDATA1 = 0xEF and WDATA2 = 0xBE. Because these addresses support the auto-increment feature, the user
can perform a single 16-bit write to WDATA1 to write the entire data. To read the value of the data at the
specified address, read the LSB from WDATA1 and the MSB from WDATA2.
These registers are used for updating the UCD9081 configuration as explained in Configuring the UCD9081.
8.6.10 Reading the FLASH Error Log
There are two ways to read the FLASH error log in the UCD9081. While the device is in RESET and the
NVERRLOG bit in the STATUS register is set to a 1 (FLASH error logs present), the user may use the ERROR
registers to read the log. During run-time, the FLASH error log can be accessed by performing an I2C read
transaction starting at address 0x1000 with a length of 48 bytes.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Considerations for MONX Input Series Resistance, RS
RS is the series impedance between the sampled voltage source (low impedance power supply output) and the
UCD9081 MONx input pin. This resistance can affect UCD9081 sampling accuracy if it is too large. In most
cases (when the power supply being monitored has a lower VOUT than the UCD9081 voltage reference being
used) this resistance is low and can be ignored. In cases where a voltage divider is used to scale the monitored
voltage below the voltage reference, the impedance of this network must be chosen so that it does not adversely
affect the analog to digital converter (ADC) conversion accuracy. The equivalent series impedance (RS) of the
divider network is just the parallel combination of the pullup and pulldown resistors.
The UCD9081 has an internal clock (DCO) whose frequency is set by ROSC on pin 32. The DCO frequency can
be affected by several factors including supply voltage and temperature. This clock is used by the ADC to set up
an ADC sample or gate time (TGATE) at each MONx pin. The voltage sampled must be allowed to settle
sufficiently during TGATE. The settling time is affected by the UCD9081 internal capacitance and RS. To allow for
sufficient settling time over DCO frequency, supply voltage, and temperature variation, choose RS < 6 kΩ.
9.1.2 Estimating UCD9081 Reporting Accuracy Over Variations in ADC Voltage Reference
The UCD9081 uses a 10-bit ADC. The ADC in the UCD9081 derives its reference voltage (VR+ ) from either the
external (VCC pin) or internal (VREF+) reference voltage to scale the digitally reported voltage. The least significant
bit (LSB) voltage value is VLSB = VR+/2n where n = 10 and VR+ is the reference voltage used (either external VCC
= 3.3 V nominal, or internal VREF+ = 2.5 V nominal). For external VR+ = VCC = 3.3 V, VLSB = 3.3 / 1024 = 3.22 mV
and for internal VR+ = VREF+ = 2.5 V, VLSB = 2.5 / 1024 = 2.44 mV.
The error in the reported voltage is a function of the ADC linearity error(s) as well as variations in the ADC
reference voltage. The total unadjusted error (ETUE) for the ADC in the UCD9081 is ±5 LSB and the variation of
the internal 2.5-V reference is ±6% maximum. VTUE is calculated as VLSB × ETUE for the particular reference
voltage used. The reported voltage error is the sum of the reference voltage error and the ADC total unadjusted
error. At lower monitored voltages, ETUE may dominate reported error while at higher monitored voltages VR+
dominates the reported error. Reported error (percent) can be calculated using Equation 3.
RPTERR = [(1 + REFTOL) / VACT] × [VR+ × ETUE / 1024 + VACT] – 1
where
•
•
•
REFTOL is VR+ tolerance
VACT is actual voltage monitored (at the UCD9081 MONx pin)
VR+ is the nominal voltage of the ADC reference
(3)
Listed below are four examples using Equation 3 to estimate reported error:
• VR+ = 2.5 V, REFTOL = 6%, VACT = 0.25 V, RPTERR = 11.2%
• VR+ = 2.5 V, REFTOL = 6%, VACT = 2.25 V, RPTERR = 6.6%
• VR+ = 3.3 V, REFTOL = 1%, VACT = 0.25 V, RPTERR = 7.5%
• VR+ = 3.3 V, REFTOL = 1%, VACT = 2.25 V, RPTERR = 1.7%
In addition to the reporting errors due to ADC and voltage reference, there can be additional errors due to divider
resistor tolerance when monitoring voltages higher than VR+. These errors can be added to the reporting error
described above.
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9.2 Typical Application
Figure 20 illustrates a typical power supply sequencing configuration. Power Supply 1 and Power Supply X
require active low enables while Power Supply 2 and Power Supply 3 require active high enables. VOUT1 and
VOUT3 exceed the selected A/D reference voltage so their outputs are divided before being sampled by the MON1
and MON3 inputs. VOUT2 and VOUTX are within the selected A/D reference voltage so their outputs can be
sampled directly by the MON2 and MON7 inputs. Figure 20 illustrates the use of the GPO digital output pins to
provide status and power on reset to other system devices.
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VBUS
VBUS
RTN
6
3.3V
3.3V
Regulator
MON1
EN1
7
MON2
EN2
24
8
MON3
EN3
11
18
MON4
EN4
10
19
MON5
EN5
12
9
MON6
EN6
13
15
MON7
EN7
14
16
MON8
NC
2
10kW
Power
Supply
1
EN
3.3V
Power
Supply
2
EN
VOUT1
VOUT2
UCD9081
5
3.3V
0.01mF
23
3.3V
RST
3
XIN
NC
17
29
TEST
NC
20
4
NC
NC
31
32
ROSC
VCC
30
Power
Supply
3
EN
VOUT3
*
*
100kW
3.3V
10kW
2
I C
Master
3.3V
22
SCL
21
SDA
*
3.3V
Power
Supply
X
EN
1 mF
3.3V
VOUTX
10kW
3.3V
3.3V
3.3V
10kW
3.3V
10kW
3.3V
10kW
VSS
ADDR4/
G PO4
ADDR3/
G PO3
28
27
1
EN8/
ADDR2/ ADDR1/
G PO2
G PO1
26
POR1
POR2
25
10kW
POR3
System
Device
Resets
POR4
1kW
DNP
1kW
2
DNP
EX: Slave I C Address = 0x65
(Internal ADDR[7:5] = 0b110)
330W
Status
LEDs
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Figure 20. Typical Power Supply Sequencing Application
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9.2.1 Design Requirements
RST pin must have a 10-kΩ pullup resistor to 3.3 V and 10-nF decoupling capacitor to ground. The component
must be placed as close to the RST pin as possible.
9.2.2 Detailed Design Procedure
UCD9081 GUI can be used to design the device configuration. An USB-to-I2C Adapter from Texas Instruments
can be used to connect GUI to I2C.
General design steps include:
1. General rail setup
2. Rail sequencing conditions setup
3. Alarm action (fault response) setup
4. System conditions setup
5. General GPO setup
6. GPO sequence setup
After configuration changes, click Store to Buffer to save the current entries to a GUI. Click Update Parameters
and Sequence to permanently store the new configuration into the device data flash.
9.2.3 Application Curve
Figure 21. Example Power-On Sequence
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10 Power Supply Recommendations
Use a 3.3-V power supply with the UCD9081.
11 Layout
11.1 Layout Guidelines
The power pad provides a thermal and mechanical interface between the device and the printed-circuit board
(PCB). Connect the power pad to the device VSS pins. Pin 2 must not be connected. Pin (4, 17, 20, 31) are
recommended to connect to VSS because these pins are not connected internally.
11.2 Layout Example
[
[
[
[
PIN20 Connected
To VSS
PIN17 Connected
To VSS
PIN4 Connected
To VSS
[
[
[
PIN2 Not
Connected
[
[
[
PIN31 Connected
To VSS
Power Pad Connected to VSS
Figure 22. UCD9081 Layout, Top Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• UCD9081 EVM User's Guide (SLVU249)
• UCD9081 Programming Guide (SLVA275)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, TMS320, E2E are trademarks of Texas Instruments.
Windows is a trademark of Microsoft Corporation.
I2C is a trademark of Phillips Electronics.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCD9081RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCD
9081
UCD9081RHBRG4
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCD
9081
UCD9081RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCD
9081
UCD9081RHBTG4
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UCD
9081
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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