V62/05602-01XE

     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 D Controlled Baseline D D D D D D D D ESD Protection Exceeds JESD 22 − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Bidirectional Voltage Translator 2.3 V to 3.6 V on A Port and 3 V to 5.5 V on B Port Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD 17 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) DB, DW, OR PW PACKAGE (TOP VIEW) VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB NC OE B1 B2 B3 B4 B5 B6 B7 B8 GND NC − No internal connection description/ordering information This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and vice versa. The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are isolated. The control circuitry (DIR, OE) is powered by VCCA. ORDERING INFORMATION −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING SOIC − DW Reel of 2000 CLVCC3245AIDWREP LVCC3245A SSOP − DB Reel of 2000 CLVCC3245AIDBREP LH245AEP TSSOP − PW Reel of 2000 CLVCC3245AIPWREP LH245AEP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated   !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 FUNCTION TABLE (each transceiver) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) 2 DIR 22 OE A1 3 21 B1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Input voltage range, VI: All A ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V All B ports (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V Output voltage range, VO (see Note 2): All A ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V All B ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCCA, VCCB, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 4.6 V maximum. 2. This value is limited to 6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 recommended operating conditions (see Note 4) VCCA VCCA VCCB MIN NOM MAX Supply voltage 2.3 3.3 3.6 V Supply voltage 3 5 5.5 V 2.3 V VIHA VIHB VILA VILB VIH VIL 3V 1.7 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3V 2 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 3.85 2.3 V 3V 0.7 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V 0.8 2.3 V 3V 0.8 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V 2.3 V 3V 1.7 2.7 V 3V 2 3V 3.6 V 2 3.6 V 5.5 V 2 2.3 V 3V 0.7 2.7 V 3V 0.8 3V 3.6 V 0.8 3.6 V 5.5 V High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage High-level input voltage (control pins) (Referenced to VCCA) Low-level input voltage (control pins) (Referenced to VCCA) VCCB UNIT V V V V 1.65 V V 0.8 VIA VIB Input voltage 0 Input voltage 0 VOA VOB Output voltage 0 Output voltage 0 VCCA VCCB V VCCA VCCB V V V NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 recommended operating conditions (see Note 4) (continued) IOHA IOHB IOLA VCCA 2.3 V VCCB 3V 2.7 V 3V −12 3.3 V 3V −24 High-level output current High-level output current Low-level output current IOLB Low-level output current ∆t/∆v Input transition rise or fall rate MIN NOM MAX UNIT −8 2.3 V 3.3 V −12 2.7 V 3.3 V −12 3.3 V 3V −24 2.3 V 3V 8 2.7 V 3V 12 3.3 V 3V 24 2.3 V 3.3 V 12 2.7 V 3.3 V 12 3.3 V 3V 24 10 mA mA mA mA ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 µA IOH = −8 mA VOHA VCCA VCCB MIN TYP 3 3V 3V 2.9 2.3 V 3V 2 2.7 V 3V 2.2 2.5 3V 3V 2.4 2.8 2.2 2.6 IOH = −12 mA VOLA VOLB 3V 3V 2.7 V 4.5 V 2 2.3 IOH = −100 µA 3V 3V 2.9 3 2.3 V 3V 2.4 2.7 V 3V 2.4 2.8 3V 3V 2.2 2.6 IOH = −24 mA 2.7 V 4.5 V 3.2 4.2 IOL = 100 µA IOL = 8 mA 3V 3V 2.3 V 3V IOL = 12 mA 2.7 V 3V 0.1 0.5 3V 3V 0.2 0.5 IOL = 24 mA 2.7 V 4.5 V 0.2 0.5 IOL = 100 µA IOL = 12 mA 3V 3V 2.3 V 3V 3V IOL = 24 mA 3V 3.6 V V 0.1 0.6 0.4 0.2 0.5 4.5 V 0.2 0.5 3.6 V ±0.1 ±1 5.5 V ±0.1 ±1 Control inputs VI = VCCA or GND IOZ† A or B ports VO = VCCA/B or GND, VI = VIL or VIH 3.6 V 3.6 V ±0.5 ±5 A port = VCCA or GND, IO = 0 3.6 V Open 5 50 ICCA B to A 3.6 V 5 50 5.5 V 5 50 3.6 V 5 50 5.5 V 8 80 B port = VCCB or GND, IO = 0 3.6 V A to B A port = VCCA or GND, IO = 0 3.6 V A port VI = VCCA − 0.6 V, Other inputs at VCCA or GND, OE at GND and DIR at VCCA 3.6 V 3.6 V 0.35 0.5 OE VI = VCCA − 0.6 V, Other inputs at VCCA or GND, DIR at VCCA 3.6 V 3.6 V 0.35 0.5 DIR VI = VCCA − 0.6 V, Other inputs at VCCA or GND, OE at GND 3.6 V 3.6 V 0.35 0.5 ∆ICCB‡ B port VI = VCCB − 2.1 V, Other inputs at VCCB or GND, OE at GND and DIR at GND 3.6 V 5.5 V 1 1.5 Ci Control inputs Open Open 4 ∆ICCA‡ VI = VCCA or GND VO = VCCA/B or GND V 0.1 II ICCB UNIT V IOH = −24 mA IOH = −12 mA VOHB MAX V µA A µA µA µA A mA mA pF Cio A or B ports 3.3 V 5V 18.5 pF † For I/O ports, the parameter IOZ includes the input leakage current. ‡ This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) PARAMETER FROM (INPUT) TO (OUTPUT) tPHL tPLH A B tPHL tPLH B A tPZL tPZH OE A tPZL tPZH OE B tPLZ tPHZ OE A tPLZ tPHZ OE B VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ± 0.3 V VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ± 0.5 V MIN MAX MIN 1 9.4 1 9.1 1 1 VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ± 0.3 V MAX MIN MAX 1 6 1 7.1 1 5.3 1 7.2 11.2 1 5.8 1 6.4 9.9 1 7 1 7.6 1 14.5 1 9.2 1 9.7 1 12.9 1 9.5 1 9.5 1 13 1 8.1 1 9.2 1 12.8 1 8.4 1 9.9 1 7.1 1 7 1 6.6 1 6.9 1 7.8 1 6.9 1 8.8 1 7.3 1 7.5 1 8.9 1 7 1 7.9 UNIT ns ns ns ns ns ns operating characteristics, VCCA = 3.3 V, VCCB = 5 V, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd Power dissipation capacitance per transceiver Outputs disabled TYP UNIT 38 CL = 50, f = 10 MHz 4.5 pF power-up considerations† TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. To guard against such power-up problems, take these precautions: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (VCCA for all four of these devices). 3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. † Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A PORT VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B PORT VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B PORT VCCA = 3.6 V AND VCCB = 5.5 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC B-Port Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION VCC 1.5 V Input 1.5 V B-Port Output 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPLZ t Output PZL Waveform 1 50% VCC S1 at 2 × VCC (see Note B) 0V tPHL tPLH 2.7 V Output Control VCC VOL + 0.3 V VOL tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
     

    
    
 
SCAS773A − JUNE 2004 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT VCCA AND VCCB = 3.6 V 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT tw 2.7 V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 2.7 V 1.5 V Input 1.5 V Output Waveform 1 S1 at 7 V (see Note B) 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 2.7 V Output Control 1.5 V 1.5 V 0V tPLZ tPZL 3.5 V 1.5 V tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLVCC3245AIDBREP ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP CLVCC3245AIDWREP ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A CLVCC3245AIPWREP ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP V62/05602-01XE ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP V62/05602-01YE ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH245AEP V62/05602-01ZE ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC3245A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of