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VCA824
SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
VCA824 Ultra-Wideband, > 40-dB Gain Adjust Range, Linear in V/V Variable Gain Amplifier
1 Features
•
•
•
•
•
•
•
1
710-MHz Small-Signal Bandwidth (G = 2 V/V)
320 MHz, 4-VPP Bandwidth (G = 10 V/V)
0.1-dB Gain Flatness to 135 MHz
2500-V/µs Slew Rate
> 40-dB Gain Adjust Range
High Gain Accuracy: 20-dB ±0.3-dB
High Output Current: ±90 mA
2 Applications
•
•
•
•
•
Differential Line Receivers
Differential Equalizers
Pulse Amplitude Compensation
Variable Attenuators
Voltage-Tunable Active Filters
The VCA824 internal architecture consists of two
input buffers and an output current feedback amplifier
stage integrated with a multiplier core to provide a
complete variable gain amplifier (VGA) system that
does not require external buffering. The maximum
gain is set externally with two resistors, providing
flexibility in designs. The maximum gain is intended
to be set between 2 V/V and 40 V/V. Operating from
±5-V supplies, the gain control voltage for the
VCA824 adjusts the gain linearly in V/V as the control
voltage varies from 1 V to –1 V. For example, set for
a maximum gain of 10 V/V, the VCA824 provides
10 V/V, at 1-V input, to 0.1 V/V at –1-V input of gain
control range. The VCA824 offers excellent gain
linearity. For a 20-dB maximum gain, and a gaincontrol input voltage varying between 0 V and 1 V,
the gain does not deviate by more than ±0.3-dB
(maximum at 25°C).
Device Information(1)
3 Description
PART NUMBER
The VCA824 is a DC-coupled, wideband, linear-in
V/V, continuously variable, voltage-controlled gain
amplifier. The device provides a differential input to
single-ended conversion with a high-impedance gain
control input used to vary the gain down 40 dB from
the nominal maximum gain set by the gain resistor
(RG) and feedback resistor (RF).
VCA824
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Differential Equalization of an RC Load
Differential Equalizer
VIN1
9
+VIN
0
FB
RG
Gain (dB)
R1
VCA824
C1
-VIN
Initial Frequency Response
of the VCA824 with RC Load
-3
-6
-9
-12
RGVIN2
3
RG+
RS
Equalized Frequency Response
6
RF
20W
-15
-18
RS
-21
-24
1M
10M
100M
1G
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
VCA824
SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = ±5 V......................... 5
Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V... 7
Typical Characteristics: VS = ±5 V, AVMAX = 10
V/V ........................................................................... 11
7.8 Typical Characteristics: VS = ±5 V, AVMAX = 40
V/V ........................................................................... 15
8
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 28
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................ 30
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
Changes from Revision D (January 2016) to Revision E
Page
•
Changed Output Voltage Swing parameter RL = 100 Ω specifications ................................................................................. 6
•
Changed Output Current parameter specifications ................................................................................................................ 6
Changes from Revision C (December 2008) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Deleted Thermal Characteristics rows from Electrical Characteristics .................................................................................. 5
Changes from Revision B (August 2008) to Revision C
•
Revised second paragraph in the Wideband Variable Gain Amplifier Operation section describing pin 9.......................... 28
Changes from Revision A (December 2007) to Revision B
•
Page
Page
Changed storage temperature range rating in Absolute Maximum Ratings table from – 40 ° C to 125 ° C to – 65 ° C
to 125 ° C .............................................................................................................................................................................. 4
Changes from Original (November 2007) to Revision A
Page
•
Added typical value for output impedance ............................................................................................................................. 6
•
Changed wording of explanation for X2Y capacitor usage at end of paragraph.................................................................. 28
2
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SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
5 Device Comparison Table
SINGLES
DUALS
GAIN ADJUST RANGE (dB)
INPUT NOISE (nV/√Hz)
SIGNAL BANDWIDTH (MHz)
VCA810
—
80
2.4
35
—
VCA2612
45
1.25
80
—
VCA2613
45
1
80
—
VCA2615
52
0.8
50
—
VCA2617
48
4.1
50
VCA820
—
40
8.2
150
VCA821
—
40
6.0
420
VCA822
—
40
8.2
150
VCA824
—
40
6.0
420
6 Pin Configuration and Functions
D Package
14-Pin SOIC
Top View
DGS Package
10-Pin VSSOP
Top View
+VCC
1
14 +VCC
VG
2
+VIN
FB
1
10 GND
13 NC
+VCC
2
9
VOUT
3
12 FB
VG
3
8
-VCC
+RG
4
11 GND
+VIN
4
7
-VIN
-RG
5
10 VOUT
+RG
5
6
-RG
-VIN
6
9
VREF
-VCC
7
8
-VCC
NC = No Connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SOIC
VSSOP
VCC
1,14
2
P
Positive supply voltage
VG
2
3
I
Gain control voltage
+VIN
3
4
I
noninverting input
+RG
4
5
I
Gain set resistor noninverting input
–RG
5
6
I
Gain set resistor inverting input
–VIN
6
7
I
Inverting input
–VCC
7,8
8
P
Negative supply voltage
VREF
9
—
I
Output reference voltage (Non- Inverting input of output buffer)
VOUT
10
9
O
Output voltage
GND
11
10
P
Ground
FB
12
1
I
Feedback resistor (inverting input of output buffer)
NC
13
—
—
Not connected
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SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Power supply
Internal power dissipation
MAX
UNIT
±6.5
V
See Thermal Information
Input voltage
±VS
V
Junction temperature (TJ)
260
°C
140
°C
125
°C
Junction temperature (TJ), continuous operation
Storage temperature
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating voltage
Operating temperature
MIN
NOM
MAX
7
10
12
UNIT
V
–40
25
85
°C
7.4 Thermal Information
VCA824
THERMAL METRIC
(1)
D (SOIC)
DGS (VSSOP)
14 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
90.3
173.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.8
46.6
°C/W
RθJB
Junction-to-board thermal resistance
44.9
94.3
°C/W
ψJT
Junction-to-top characterization parameter
13.8
2.2
°C/W
ψJB
Junction-to-board characterization parameter
44.6
92.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
7.5 Electrical Characteristics: VS = ±5 V
At AVMAX = 10 V/V, VG = 1V, RF = 402 Ω, RG = 80 Ω, and RL = 100 Ω, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TEST LEVEL (1)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
AVMAX = 2 V/V, VG = 1 V , VO = 500 mVPP
Small-Signal Bandwidth
AVMAX = 10 V/V, VG = 1 V, VO = 500 mVPP
710
C
420
AVMAX = 40 V/V, VG = 1 V, VO = 500 mVPP
Large-Signal Bandwidth
AVMAX = 10 V/V, VG = 1 V, VO = 4 VPP
C
TA= 25°C
Gain Control Bandwidth
VO = 200 mVPP, TA= 25°C
TA = 0°C to 70°C
AVMAX = 10 V/V, VG = 1 V, VO = 2 VPP
B
AVMAX = 10 V/V, VG = 1 V, VO =
4 V Step
TA= 0°C to 70°
235
C
B
TA = 0°C to 70°C
V/μs
1700
1.5
B
AVMAX = 10 V/V, VG = 1 V, VO = 4 V Step
2nd-Harmonic
VO = 2 VPP, f = 20 MHz
TA = 0°C to 70°C
C
B
TA = 0°C to 70°C
ns
-66
–64
dBc
–64
TA = 25°C
VO = 2 VPP, f = 20 MHz
11
–64
TA = –40°C to 85°C
3rd-Harmonic
ns
1.9
TA = 25°C
Harmonic
Distortion
1.8
1.9
TA = –40°C to 85°C
Settling Time to 0.01%
MHz
2500
1700
TA = 25°C
AVMAX = 10 V/V, VG = 1 V, VO =
4 V Step
MHz
135
1800
TA = –40°C to 85°C
Rise-and-Fall Time
MHz
330
235
TA= 25°C
Slew Rate
320
240
TA = –40°C to 85°C
Bandwidth for 0.1-dB Flatness
MHz
170
–61
B
TA = –40°C to 85°C
–63
–61
dBc
–61
Input Voltage Noise
f > 100 kHz
C
6
nV/√Hz
Input Current Noise
f > 100 kHz
C
2.6
pA/√Hz
GAIN CONTROL
TA = 25°C
Gain Error
AVMAX = 10 V/V, VG = 1 V
TA = 0°C to 70°C
±0.1
A
±0.5
TA = –40°C to 85°C
AVMAX = 10 V/V, 0 < VG < 1
TA = 0°C to 70°C
±0.05
A
TA = 0°C to 70°C
±1.06
A
TA = 0°C to 70°C
–26
A
22
A
TA = 0°C to 70°C
Gain Control Input Impedance
TA = 25°C
30
35
TA = –40°C to 85°C
Average Gain Control Bias Current
Drift
dB
–23
TA = 25°C
TA = 0°C to 70°C
–24
–24
TA = –40°C to 85°C
Gain Control Bias Current
dB
±2.2
TA = 25°C
Relative to max gain
±1.9
±2.1
TA = –40°C to 85°C
Gain at VG = –0.9V
dB
±0.37
TA = 25°C
AVMAX = 10 V/V, -0.8 < VG < 1
±0.3
±0.34
TA = –40°C to 85°C
Gain Deviation
dB
±0.6
TA = 25°C
Gain Deviation
±0.4
μA
37
±100
B
nA/°C
TA = –40°C to 85°C
±100
C
1.5 || 0.6
MΩ || pF
DC PERFORMANCE
TA = 25°C
Input Offset Voltage
AVMAX = 10 V/V, VCM = 0 V,
VG = 1 V
TA = 0°C to 70°
±4
A
TA = –40°C to 85°C
Average Input Offset Voltage Drift
AVMAX = 10 V/V, VCM = 0 V,
VG = 1 V
TA = 0°C to 70°C
AVMAX = 10 V/V, VCM = 0V,
VG = 1 V
±30
B
±30
19
A
TA = –40°C to 85°C
(1)
μV/°C
TA = –40°C to 85°C
TA = 0°C to 70°C
mV
±19
TA = 25°C
Input Bias Current
±17
±17.8
25
29
μA
31
Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
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Electrical Characteristics: VS = ±5 V (continued)
At AVMAX = 10 V/V, VG = 1V, RF = 402 Ω, RG = 80 Ω, and RL = 100 Ω, unless otherwise noted.
PARAMETER
Average Input Bias Current Drift
TEST CONDITIONS
AVMAX = 10 V/V, VCM = 0 V,
VG = 1 V
TA = 0°C to 70°C
TEST LEVEL (1)
MIN
B
±90
±0.5
A
AVMAX = 10 V/V, VCM = 0 V,
VG = 1 V
TA = 0°C to 70°C
±16
B
nA/°C
TA = –40°C to 85°C
±16
±2.6
TA = 0°C to 70°C
μA
±3.5
TA = 25°C
Max Current Through Gain Resistance
±2.5
±3.2
TA = –40°C to 85°C
Average Input Offset Current Drift
UNIT
nA/°C
TA = –40°C to 85°
TA = 0°C to 70°C
MAX
±90
TA = 25°C
AVMAX = 10 V/V, VCM = 0 V,
VG = 1 V
Input Offset Current
TYP
B
±2.55
±2.55
TA = –40°C to 85°C
mA
±2.5
INPUT
TA = 25°C
Most Positive Common-Mode Input
Voltage
RL = 100 Ω
TA = 0°C to 70°C
1.6
A
TA = –40°C to 85°C
RL = 100 Ω
TA = 0°C to 70°C
V
1.6
TA = 25°C
Most Negative Common-Mode Input
Voltage
1.6
1.6
–2.1
A
–2.1
TA = –40°C to 85°C
VCM = ±0.5 V
TA = 0°C to 70°C
V
–2.1
TA = 25°C
Common-Mode Rejection Ratio
–2.1
80
A
65
60
TA = –40°C to 85°C
dB
60
Differential
C
1 || 1
MΩ || pF
Common-Mode
C
1 || 2
MΩ || pF
Input Impedance
OUTPUT
TA = 25°C
RL = 1 kΩ
TA = 0°C to 70°C
±3.6
A
TA = –40°C to 85°C
3.5
TA = 25°C
Output Current
VO = 0V, RL = 10 Ω
3.6
–3.3
–3.2
A
V
TA = 0°C to 70°C
3.3
TA = –40°C to 85°C
3.2
Source, TA = 25°C
60
Sink, TA = 25°C
AVMAX = 10 V/V, f > 100 kHz
–3
–2.9
90
–55
–50
A
TA = 0°C to 70°C
mA
50
TA = –40°C to 85°C
Output Impedance
V
±3.3
Output Voltage Swing
RL = 100 Ω
±3.9
±3.4
–42
45
C
–38
0.01
Ω
±5
V
POWER SUPPLY
Specified Operating Voltage
C
TA = 25°C
Minimum Operating Voltage
±4
TA = 0°C to 70°C
B
TA = –40°C to 85°C
±4
V
±4
TA = 25°C
Maximum Operating Voltage
±6
TA = 0°C to 70°C
A
±6
TA = –40°C to 85°C
TA = 25°C
Maximum Quiescent Current
VG = 0 V
TA = 0°C to 70°C
36.5
A
TA = 0°C to 70°C
36.5
A
TA = 0°C to 70°C
–61
A
TA = –40°C to 85°C
6
mA
34
TA = 25°C
VG = 1 V
35
34.5
TA = –40°C to 85°C
Power-Supply Rejection Ratio
(-PSRR)
mA
38.5
TA = 25°C
VG = 0 V
37.5
38
TA = –40°C to 85°C
Minimum Quiescent Current
V
±6
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–59
-68
dB
–58
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7.6 Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V
At TA = 25°C, RL = 100 Ω, RF = 453 Ω, RG = 453 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and 14Pin SOIC package, unless otherwise noted.
3
3
VO = 0.5VPP
VG = 0V
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
VG = +1V
-6
-9
-12
AVMAX = +2V/V
VIN = 1VPP
RL = 100W
-15
-18
-3
VO = 1VPP
-6
VO = 2VPP
-9
VO = 4VPP
-12
VO = 5VPP
-15
-18
1M
10M
100M
1G
1M
10M
Frequency (Hz)
Figure 1. Small-Signal Frequency Response
VIN = 250mVPP
f = 20MHz
VIN = 2VPP
f = 20MHz
3
200
Output Voltage (V)
Output Voltage (mV)
300
100
0
-100
2
1
0
-1
-2
-200
-3
-300
Time (10ns/div)
Time (10ns/div)
Figure 3. Small-Signal Pulse Response
Figure 4. Large-Signal Pulse Response
0
0
-0.020
-dP, VG = 0V
-0.025
-0.5
-0.6
-0.030
-dP, VG = +1V
-0.7
-0.8
-0.035
-0.040
-dG, VG = +1V
-0.045
-0.9
2
3
4
Magnitude (dB)
Differential Gain (%)
-0.015
-0.3
Differential Phase (°)
-0.010
0.15
Left Scale
-0.005
-dG, VG = 0V
-0.2
0.2
0.1
0.10
0
0.05
0
-0.1
Right Scale
-0.2
-0.05
-0.3
-0.10
-0.4
-0.15
AVMAX = +2V/V
VG = +1V
-0.5
0
50
Deviation from Linear Phase (°)
-0.1
1
1G
Figure 2. Large-Signal Frequency Response
4
400
-0.4
100M
Frequency (Hz)
-0.20
100
150
200
Frequency (MHz)
Number of Video Loads
Figure 5. Composite Video dG/dP
Figure 6. Gain Flatness, Deviation From Linear Phase
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Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V (continued)
-60
-60
-65
-65
-70
3rd-Harmonic
-75
-80
AVMAX = +2V/V
VG = +1V
VO = 2VPP
RL = 100W
2nd-Harmonic
-85
-90
0.1
1
10
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
At TA = 25°C, RL = 100 Ω, RF = 453 Ω, RG = 453 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and 14Pin SOIC package, unless otherwise noted.
AVMAX = +2V/V
VG = +1V
VO = 2VPP
f = 20MHz
-70
2nd-Harmonic
-75
-80
3rd-Harmonic
-85
-90
100
100
1k
Frequency (MHz)
Resistance (W)
Figure 7. Harmoneic Distortion vs Frequency
AVMAX = +2V/V
VG = +1V
RL = 100W
f = 20MHz
Harmonic Distortion (dBc)
-35
-40
-45
Figure 8. Harmonic Distortion vs Load Resistance
-10
Maximum Current
Through RG Limited
-50
-55
-60
-65
2nd-Harmonic
-70
-75
3rd-Harmonic
-80
1
Maximum Current
Through RG Limited
-40
-50
3rd-Harmonic
-60
-70
2nd-Harmonic
-90
-0.6
10
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
Output Voltage Swing (VPP)
Gain Control Voltage (V)
Figure 9. Harmonic Distortion vs Output Voltage
Figure 10. Harmonic Distortion vs Gain Control Voltage
38
40
36
35
Intercept Point (+dBm)
Intercept Point (+dBm)
-30
-80
-85
0.1
AVMAX = +2V/V
VO = 2VPP
RL = 100W
f = 20MHz
-20
Harmonic Distortion (dBc)
-30
34
32
30
28
f = 20MHz
At 50W Matched Load
Constant Input Voltage
Constant Output Voltage
30
25
20
15
26
At 50W Matched Load
24
0
8
10
20
30
40
50
60
70
80
90
100
10
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
Frequency (MHz)
Gain Control Voltage (V)
Figure 11. Two-Tone, 3rd-Order Intermodulation Intercept
Figure 12. Two-Tone, 3rd-Order Intermodulation Intercept vs
Gain Control Voltage
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Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 453 Ω, RG = 453 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and 14Pin SOIC package, unless otherwise noted.
2.2
2.0
1.8
1.6
3
VG = 0VDC + 10mVPP
VIN = 0.5VDC
Normalized Gain (dB)
0
Gain (V/V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-3
-6
-9
-0.2
-1.2
-0.8
0
-0.4
0.4
0.8
-12
1.2
1M
10M
Gain Control Voltage (V)
Figure 13. Gain vs Gain Control Voltage
1G
Figure 14. Gain Control Frequency Response
2
1
0
1.5
-1
1.0
10
0
VG = +1V
-10
-20
Gain (dB)
3
Output Voltage (V)
4
VIN = 1VDC
Input Voltage (V)
100M
Frequency (Hz)
-30
-40
-50
VG = -1V
-60
0.5
-70
0
-80
VG = 2VPP
-90
-0.5
-100
1M
-1.0
10M
Time (10ns/div)
Figure 15. Gain Control Pulse Response
Figure 16. Fully-Attenuated Response
1.4
10MHz
1.4
Group Delay (ns)
Group Delay (ns)
1.6
1.2
1.0
0.8
1G
1.6
2.0
1.8
100M
Frequency (Hz)
1MHz
20MHz
0.6
1.2
1.0
0.8
0.6
0.4
0.4
VG = +1V
VO = 1VPP
0.2
0.2
0
-1.0 -0.8 -0.6 -0.4 -0.2
0
0
0.2
0.4
0.6
0.8
1.0
0
20
40
60
80
Gain Control Voltage (V)
Frequency (MHz)
Figure 17. Group Delay vs Gain Control Voltage
Figure 18. Group Delay vs Frequency
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Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 453 Ω, RG = 453 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and 14Pin SOIC package, unless otherwise noted.
9
100
VO = 0.5VPP
CL = 10pF
6
CL = 22pF
CL = 100pF
RS (W)
RS (W)
3
10
CL = 47pF
0
RF
-3
VIN
+
RS
VCA824
-6
0.1dB Flatness Targeted
1
NOTE: (1) 1kW is optional.
10
100
1
1k
10
100
1k
Capacitive Load (pF)
Capacitive Load (pF)
Figure 20. Frequency Response vs Capacitive Load
Figure 19. Recommended RSvs Capacitive Load
200
10
Input Voltage Noise Density (pA/ÖHz)
Output Voltage Noise Density (nV/ÖHz)
(1)
1kW
-9
1
VG = 0V
100
VG = +1V
VG = -1V
10
1
100
10
VOUT
CL
-
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 21. Output Voltage Density
Figure 22. Input Current Noise Density
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7.7 Typical Characteristics: VS = ±5 V, AVMAX = 10 V/V
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 80 Ω, VG = 1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless
otherwise noted.
3
3
VG = 0V
0
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
VG = +1V
-9
-12
AVMAX = +10V/V
VIN = 200mVPP
RG = 100W
-15
-18
VO = 1VPP
-3
VO = 0.5VPP
-6
-9
-12
VO = 4VPP
-15
VO = 2VPP
-18
1M
10M
100M
1G
0
200M
Frequency (Hz)
Figure 23. Small-Signal Frequency Response
VIN = 50mVPP
f = 20MHz
Output Voltage (V)
Output Voltage (mV)
0
-100
VIN = 400mVPP
f = 20MHz
1
0
-1
-2
-200
-3
-300
Time (10ns/div)
Time (10ns/div)
Figure 26. Large-Signal Pulse Response
0.20
0.1
Left Scale
-0.1
0.10
-0.2
0.05
0
-0.3
Right Scale
-0.05
-0.4
-0.10
AVMAX = +10V/V
VG = +1V
50
-0.15
100
150
200
Deviation from Linear Phase (°)
0.15
0
Output Voltage Noise Density (nV/ÖHz)
Figure 25. Small-Signal Pulse Response
Magnitude (dB)
1G
2
100
0
800M
Figure 24. Large-Signal Frequency Response
3
200
-0.6
600M
Frequency (Hz)
300
-0.5
400M
200
VG = +1V
100
VG = -1V
VG = 0V
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (MHz)
Figure 27. Gain Flatness, Deviation from Linear Phase
Figure 28. Output Voltage Noise Density
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Typical Characteristics: VS = ±5 V, AVMAX = 10 V/V (continued)
-50
-66
-55
-68
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 80 Ω, VG = 1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless
otherwise noted.
-60
3rd-Harmonic
-65
-70
-75
AVMAX = +10V/V
VG = +1V
VO = 2VPP
RL = 100W
2nd-Harmonic
-80
-85
0.1
1
10
-70
AVMAX = +10V/V
VG = +1V
VO = 1VPP
f = 20MHz
-72
3rd-Harmonic
-74
-76
-78
2nd-Harmonic
-80
100
100
1k
Frequency (MHz)
Resistance (W)
Figure 29. Harmonic Distortion vs Frequency
AVMAX = +10V/V
VG = +1V
RL = 100W
f = 20MHz
Harmonic Distortion (dBc)
-30
-40
Figure 30. Harmonic Distortion vs Load Resistance
-10
Maximum Current
Through RG Limited
Harmonic Distortion (dBc)
-20
-50
-60
2nd-Harmonic
-70
3rd-Harmonic
-80
AVMAX = +10V/V
VO = 2VPP
RL = 100W
f = 20MHz
-20
-30
Maximum Current
Through RG Limited
-40
3rd-Harmonic
-50
-60
2nd-Harmonic
-90
0.1
1
-70
-0.6
10
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
Output Voltage Swing (VPP)
Gain Control Voltage (V)
Figure 31. Harmonic Distortion vs Output Voltage
Figure 32. Harmonic Distortion vs Gain Control Voltage
34
35
32
30
Intercept Point (+dBm)
Intercept Point (+dBm)
Constant Input Voltage
30
28
Constant Output Voltage
25
20
15
26
f = 20MHz
At 50W Matched Load
At 50W Matched Load
24
0
12
10
20
30
40
50
60
70
80
90
100
10
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
Frequency (MHz)
Gain Control Voltage (V)
Figure 33. Two-Tone, 3rd-Order Intermodulation Intercept
Figure 34. Two-Tone, 3rd-Order Intermodulation Intercept vs
Gain Control Voltage
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Typical Characteristics: VS = ±5 V, AVMAX = 10 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 80 Ω, VG = 1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless
otherwise noted.
3
0
Normalized Gain (dB)
Gain (V/V)
11
10
9
8
7
6
5
4
3
2
1
0
VG = 0VDC + 10mVPP
VIN = 0.1VDC
-3
-6
-9
-12
-1
-1.2
-15
-0.8
0
-0.4
0.4
0.8
1.2
1M
10M
Gain Control Voltage (V)
Figure 35. Gain vs Gain Control Voltage
1
0
1.5
-1
4
3
Output Voltage (V)
2
5
Output Voltage (V)
VIN = 0.2VDC
1.0
0.5
1W Internal
Power
Dissipation
100W
Load
2
1
50W
Load
0
25W
Load
-1
-2
1W Internal
Power
Dissipation
-3
0
-4
-0.5
-5
-150
-1.0
Time (10ns/div)
-50
0
50
100
150
Figure 38. Output Voltage and Current Limitations
0.4
0.3
Input Voltage (V)
VG = +1V
VG = -1V
AVMAX = +10V/V
VG = -0.3V
Input Voltage
Left Scale
2.0
1.5
0.2
1.0
0.1
0.5
0
-0.1
0
Output Voltage
Right Scale
-0.5
-0.2
-1.0
-0.3
-1.5
Output Voltage (V)
Gain (dB)
-100
Output Current (mA)
Figure 37. Gain Control Pulse Response
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1G
Figure 36. Gain Control Frequency Response
3
Input Voltage (V)
100M
Frequency (Hz)
Input Referred
VO = 2VPP
1M
10M
100M
1G
-0.4
Frequency (Hz)
Figure 39. Fully-Attenuated Response
-2.0
Time (40ns/div)
Figure 40. IRG Limited Overdrive Recovery
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Typical Characteristics: VS = ±5 V, AVMAX = 10 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 80 Ω, VG = 1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless
otherwise noted.
Output Voltage
Right Scale
6
1.65
4
1.60
10MHz
0.2
2
0
0
-0.2
-0.4
-2
Input Voltage
Left Scale
Output Voltage (V)
Input Voltage (V)
0.4
AVMAX = +10V/V
VG = +1V
Group Delay (ns)
0.6
1MHz
1.50
20MHz
1.45
-4
-0.6
1.55
1.40
-1.0 -0.8 -0.6 -0.4 -0.2
-6
0
0.2
0.4
0.6
0.8
1.0
Gain Control Voltage (V)
Time (40ns/div)
Figure 42. Group Delay vs Gain Control Voltage
Figure 41. Output Limited Overdrive Recovery
1.8
1.6
Group Delay (ns)
1.4
1.2
1.0
0.8
0.6
0.4
VG = +1V
VO = 1VPP
0.2
0
0
20
40
60
80
100
Frequency (MHz)
Figure 43. Group Delay vs Frequency
14
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7.8 Typical Characteristics: VS = ±5 V, AVMAX = 40 V/V
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 18 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and SO-14
package, unless otherwise noted.
3
3
0
VG = 0V
-3
Normalized Gain (dB)
Normalized Gain (dB)
0
-6
VG = +1V
-9
-12
-3
-18
VO = 1VPP
-9
-12
VO = 2VPP
AVMAX = +40V/V
VIN = 50mVPP
RL = 100W
-15
VO = 0.5VPP
VO = 4VPP
-6
-15
-18
1M
10M
100M
1G
0
100
Frequency (Hz)
200
200
400
500
600
Frequency (MHz)
Figure 44. Small-Signal Frequency Response
Figure 45. Large-Signal Frequency Response
400
2.5
VIN = 12.5mVPP
f = 20MHz
300
VIN = 100mVPP
f = 20MHz
2.0
Output Voltage (V)
Output Voltage (mV)
1.5
200
100
0
-100
1.0
0.5
0
-0.5
-1.0
-1.5
-200
-2.0
-2.5
-300
Time (10ns/div)
Time (10ns/div)
0.15
0.2
0.10
0.05
0
0
-0.1
-0.2
-0.05
-0.3
-0.10
-0.4
-0.15
-0.20
-0.5
0
20
40
60
200
Deviation from Linear Phase (°)
AVMAX = +40V/V
VG = +1V
0.1
Magnitude (dB)
Figure 47. Large-Signal Pulse Response
Output Voltage Noise Density (nV/ÖHz)
Figure 46. Small-Signal Pulse Response
1000
VG = +1V
VG = 0V
100
VG = -1V
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (MHz)
Figure 48. Gain Flatness, Deviation from Linear Phase
Figure 49. Output Voltage Noise Density
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Typical Characteristics: VS = ±5 V, AVMAX = 40 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 18 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and SO-14
package, unless otherwise noted.
-35
-45
-55
Harmonic Distortion (dBc)
-40
Harmonic Distortion (dBc)
-50
AVMAX = +40V/V
VG = +1V
VO = 2VPP
RL = 100W
-50
-55
-60
2nd-Harmonic
-65
-60
-70
-75
-80
3rd-Harmonic
-70
-85
0.1
1
10
3rd-Harmonic
-65
100
AVMAX = +40V/V
VG = +1V
VO = 1VPP
f = 20MHz
100
1k
Frequency (MHz)
Resistance (W)
Figure 50. Harmonic Distortion vs Frequency
AVMAX = +40V/V
VG = +1V
RL = 100W
f = 20MHz
Harmonic Distortion (dBc)
-20
-30
Figure 51. Harmonic Distortion vs Load Resistance
-10
Maximum Current
Through RG Limited
-40
-50
2nd-Harmonic
-60
3rd-Harmonic
-70
-20
-25
-30
-35
-40
3rd-Harmonic
2nd-Harmonic
-45
-50
-80
0.1
1
-55
-0.6
10
-0.4
-0.2
0
0.2
0.6
0.8
1.0
Gain Control Voltage (V)
Figure 52. Harmonic Distortion vs Output Voltage
Figure 53. Harmonic Distortion vs Gain Control Voltage
35
Intercept Point (+dBm)
32
30
28
26
30
Constant Input Voltage
25
Constant Output Voltage
20
15
24
f = 20MHz
At 50W Matched Load
At 50W Matched Load
22
0
16
0.4
Output Voltage Swing (VPP)
34
Intercept Point (+dBm)
AVMAX = +40V/V
VO = 2VPP
RL = 100W
f = 20MHz
Maximum Current
Through RG Limited
-15
Harmonic Distortion (dBc)
-10
2nd-Harmonic
10
20
30
40
50
60
70
80
90
100
10
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
Frequency (MHz)
Gain Control Voltage (V)
Figure 54. Two-Tone, 3rd-Order Intermodulation Intercept
Figure 55. Two-Tone, 3rd-Order Intermodulation Intercept vs
Gain Control Voltage
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Typical Characteristics: VS = ±5 V, AVMAX = 40 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 18 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and SO-14
package, unless otherwise noted.
45
3
0
35
Normalized Gain (dB)
Intercept Point (+dBm)
40
30
25
20
15
10
-3
-6
-9
-12
5
-15
0
-5
-1.2
VG = 0VDC + 10mVPP
VIN = 10mVDC
-18
-0.8
-0.4
0
0.4
0.8
1.2
1M
10M
Gain Control Voltage (V)
Figure 56. Gain vs Gain Control Voltage
-1
40
30
VG = +1V
20
10
0
Gain (dB)
0
Output Voltage (V)
2
1
1.5
Input Voltage (V)
1G
Figure 57. Gain Control Frequency Response
3
VIN = 50mVDC
1.0
-10
-20
-30
-40
0.5
-50
0
-60
VG = -1V
Input Referred
VO = 2VPP
-70
-0.5
-80
1M
-1.0
Time (10ns/div)
0.4
AVMAX = +40V/V
VG = -0.3V
1.2
0.1
0.4
0
0
-0.1
-0.4
-0.2
-0.8
Output Voltage
Right Scale
Output Voltage
Right Scale
2
0
0
-0.1
-2
Input Voltage
Left Scale
-0.2
-1.6
4
0.1
-1.2
-0.4
AVMAX = +40V/V
VG = +1V
-0.3
Output Voltage (V)
0.8
6
0.2
Output Voltage (V)
0.2
-0.3
1G
Figure 59. Fully Attenuated Response
Input Voltage (V)
0.3
100M
0.3
1.6
Input Voltage
Left Scale
10M
Frequency (Hz)
Figure 58. Gain Control Pulse Response
Input Voltage (V)
100M
Frequency (Hz)
-4
-6
Time (40ns/div)
Time (40ns/div)
Figure 60. IRG Limited Overdrive Recovery
Figure 61. Output Limited Overdrive Recovery
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Typical Characteristics: VS = ±5 V, AVMAX = 40 V/V (continued)
At TA = 25°C, RL = 100 Ω, RF = 402 Ω, RG = 18 Ω, VG = 1 V, VIN = single-ended input on +VIN with –VIN at ground, and SO-14
package, unless otherwise noted.
2.5
2.15
10MHz
2.10
2.0
Group Delay (ns)
Group Delay (ns)
20MHz
2.05
2.00
1MHz
1.95
1.90
1.5
1.0
0.5
1.85
1.80
-1.0 -0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
1.0
Gain Control Voltage (V)
VG = +1V
VO = 1VPP
0
0
40
60
80
100
Frequency (MHz)
Figure 62. Group Delay vs Gain Control Voltage
18
20
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Figure 63. Group Delay vs Frequency
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8 Detailed Description
8.1 Overview
The VCA824 is a voltage controlled variable gain amplifier with differential inputs and a single ended output. The
maximum gain is set by external resistors while the gain range is controlled by an external analog voltage. The
maximum gain is designed for gains of 2 V/V up to 100 V/V and the analog control allows a gain range of over
40 dB. The VCA824 Input consists of two buffers, which together create a fully symmetrical, high impedance
differential input with a typical common mode rejection of 80 dB. The gain set resistor is connected between the
two input buffer output pins, so that the input impedance is independent of the gain settings. The bipolar inputs
have a input voltage range of 1.6 and –2.1 V on ±5 V supplies. The amplifier maximum gain is set by external
resistors, but the internal gain control circuit is controlled by a continuously variable, analog voltage. The gain
control is a multiplier stage which is linear in V/V. The gain control input pin operates over a voltage range of
–1 V to 1 V. The VCA824 contains a high-speed, high-current output buffer. The output stage can typically swing
±3.9 V and source/sink ±90 mA. The VCA824 can be operated over a voltage range of ±3.5 V to ±6 V.
8.2 Functional Block Diagram
+VIN
VIN
R1
50W
Source
RF
RG+
50W
RG
VOUT
RGR3
R2
50W
Load
-VIN
50W
VG
8.3 Feature Description
The VCA824 can be operated with both single ended or differential input signals. The inputs present consistently
high impedance across all gain configurations. By using an analog control signal the amplifier gain is
continuously variable for smooth, glitch free gain changes. With a large signal bandwidth of 320 Mhz and a slew
rate of 2500 V/us the VCA824 offers linear performance over a wide range of signal amplitudes and gain
settings. The low impedance/high current output buffer can drive loads ranging from low impedance transmission
lines to high-impedance, switched-capacitor analog-to-digital converters. By using closely matched internal
components, the VCA824 offers gain accuracy of ±0.3 dB.
8.4 Device Functional Modes
The VCA824 functions as a differential input, single maximum gain of operation-ended output variable gain
amplifier. This functional mode is enabled by applying power to the amplifier supply pins and is disabled by
turning the power off. The gain is continuously variable through the analog gain control input. While the gain
range is fixed, the maximum gain is set by two external components, Rf and Rg, as shown in the Functional
Block Diagram. The maximum gain is equal to 2x (Rf / Rg). This gain is achieved with a 1-V voltage on the gain
adjust pin VG. As the voltage decreases on the VG pin, the gain decreases in a linear in dB fashion with over
40 dB of gain range from 1-V to –1-V control voltage. As with most other differential input amplifiers, inputs can
be applied to either one or both of the amplifier inputs. The amplifier gain is controlled through the gain control
pin.
8.4.1 Maximum Gain Of Operation
This section describes the use of the VCA824 in a fixed-gain application in which the VG control pin is set at
VG = 1 V. The tradeoffs described here are with bandwidth, gain, and output voltage range.
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Device Functional Modes (continued)
In the case of an application that does not make use of the VGAIN, but requires some other characteristic of the
VCA824, the RG resistor must be set such that the maximum current flowing through the resistance IRG is less
than ±2.6 mA typical, or 5.2 mAPP as defined in Electrical Characteristics: VS = ±5 V, and must follow Equation 1.
VOUT
IRG =
AVMAX ´ RG
(1)
As Equation 1 illustrates, once the output dynamic range and maximum gain are defined, the gain resistor is set.
This gain setting in turn affects the bandwidth, because in order to achieve the gain (and with a set gain
element), the feedback element of the output stage amplifier is set as well. Keeping in mind that the output
amplifier of the VCA824 is a current-feedback amplifier, the larger the feedback element, the lower the bandwidth
because the feedback resistor is the compensation element.
Limiting the discussion to the input voltage only and ignoring the output voltage and gain, Equation 2 illustrates
the tradeoff between the input voltage and the current flowing through the gain resistor.
8.4.2 Output Current And Voltage
The VCA824 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic VCA.
Under no-load conditions at 25°C, the output voltage typically swings closer than 1 V to either supply rails; the
25°C swing limit is within 1.2 V of either rails. Into a 15-Ω load (the minimum tested load), the VCA824 device is
tested to deliver more than ±160 mA.
The specifications described above, though familiar in the industry, consider voltage and current limits
separately. In many applications, it is the voltage × current, or V-I product, that is more relevant to circuit
operation (See Figure 38). The X- and Y-axes of this graph show the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the VCA824
output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1-W maximum internal
power dissipation. Superimposing resistor load lines onto the plot shows that the VCA824 can drive ±2.5 V into
25-Ω or ±3.5 V into 50-Ω without exceeding the output capabilities or the 1-W dissipation limit. A 100-Ω load line
(the standard test circuit load) shows the full ±3.9-V output swing capability, as shown in Typical Characteristics.
The minimum specified output voltage and current overtemperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup do the output current and voltage decrease to the numbers shown in
Electrical Characteristic. As the output transistors deliver power, the respective junction temperatures increase,
thereby increasing the available output voltage swing and output current.
In steady-state operation, the available output voltage and current are always greater than the temperature
shown in the overtemperature specifications because the output stage junction temperatures are higher than the
specified operating ambient.
8.4.3 Input Voltage Dynamic Range
The VCA824 has a input dynamic range limited to 1.6 V and –2.1 V. Increasing the input voltage dynamic range
can be done by using an attenuator network on the input. If the VCA824 is trying to regulate the amplitude at the
output, such as in an AGC application, the input voltage dynamic range is directly proportional to Equation 2.
VIN(PP) = RG ´ IRG(PP)
(2)
As such, for unity-gain or under-attenuated conditions, the input voltage must be limited to the CMIR of ±1.6 V
(3.2 VPP) and the current (IRQ) must flow through the gain resistor, ±2.6 mA (5.2 mAPP). This configuration sets a
minimum value for RE such that the gain resistor must be greater than Equation 3.
3.2VPP
RGMIN =
= 615.4W
5.2mAPP
(3)
Values lower than 615.4 Ω are gain elements that result in reduced input range, as the dynamic input range is
limited by the current flowing through the gain resistor RG (IRG). If the IRG current limits the performance of the
circuit, the input stage of the VCA824 goes into overdrive, resulting in limited output voltage range. Such IRGlimited overdrive conditions are shown in Figure 40 for the gain of 10V/V and Figure 60 for the gain of 40 V/V.
20
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Device Functional Modes (continued)
8.4.4 Output Voltage Dynamic Range
With its large output current capability and its wide output voltage swing of ±3.9 V typical on 100-Ω load, it is
easy to forget other types of limitations that the VCA824 can encounter. For these limitations, careful analysis
must be done to avoid input stage limitation: either voltage or IRG current. Note that if control pin VG varies, the
gain limitation may affect other aspects of the circuit.
8.4.5 Bandwidth
The output stage of the VCA824 is a wideband current-feedback amplifier. As such, the feedback resistance is
the compensation of the last stage. Reducing the feedback element and maintaining the gain constant limits the
useful range of IRG, and therefore, reduces the gain adjust range. For a given gain, reducing the gain element
limits the maximum achievable output voltage swing.
8.4.6 Offset Adjustment
As a result of the internal architecture used on the VCA824, the output offset voltage originates from the output
stage and from the input stage and multiplier core. Figure 67 shows how to compensate both sources of the
output offset voltage. Use this procedure to compensate the output offset voltage: starting with the output stage
compensation, set VG = –1 V to eliminate all offset contribution of the input stage and multiplier core. Adjust the
output stage offset compensation potentiometer. Finally, set VG = 1 V to the maximum gain and adjust the input
stage and multiplier core potentiometer. This procedure effectively eliminates all offset contribution at the
maximum gain. Because adjusting the gain modifies the contribution of the input stage and the multiplier core,
some residual output offset voltage remains.
8.4.7 Noise
The VCA824 offers 6 nV/√Hz input-referred voltage noise density at a gain of 10 V/V and 2.6-pA/√Hz inputreferred current noise density. The input-referred voltage noise density considers that all noise terms (except the
input current noise but including the thermal noise of both the feedback resistor and the gain resistor) are
expressed as one term.
This model is formulated in Equation 4 and Figure 68.
eO = AVMAX ´
2 ´ (RS ´ in)2 + en2 + 2 ´ 4kTRS
(4)
A more complete model is shown in Figure 69. For additional information on this model and the actual modeled
noise terms, please contact the High-Speed Product Application Support team at www.ti.com.
8.4.8 Input and ESD Protection
The VCA824 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings.
All pins on the VCA824 are internally protected from ESD by means of a pair of back-to-back reverse-biased
diodes to either power supply, as shown in Figure 64. These diodes begin to conduct when the pin voltage
exceeds either power supply by about 0.7 V. This situation can occur with loss of the amplifier power supplies
while a signal source is still present. The diodes can typically withstand a continuous current of 30 mA without
destruction. To ensure long-term reliability, however, diode current should be externally limited to 10 mA
whenever possible.
+VS
ESD protection diodes internally
connected to all pins.
External
Pin
Internal
Circuitry
-VS
Figure 64. Internal ESD Protection
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Difference Amplifier
Because both inputs of the VCA824 are high-impedance, a difference amplifier can be implemented without any
major problem. Figure 65 shows this implementation. This circuit provides excellent common-mode rejection ratio
(CMRR) as long as the input is within the CMRR range of –2.1 V to 1.6 V. Note that this circuit does not make
use of the gain control pin, VG. Also, it is recommended to choose RS such that the pole formed by RS and the
parasitic input capacitance does not limit the bandwidth of the circuit. Figure 66 shows the common-mode
rejection ratio for this circuit implemented in a gain of 10 V/V for VG = 1 V. Note that because the gain control
voltage is fixed and is normally set to 1V, the feedback element can be reduced in order to increase the
bandwidth. When reducing the feedback element, make sure that the VCA824 is not limited by common-mode
input voltage, the current flowing through RG, or any other limitation described in this data sheet.
RF
VIN+
+VIN
RG+
RS
RG
FB
VCA824
RG-VIN
VIN-
20W
RS
Figure 65. Difference Amplifier
Common-Mode Rejection Ratio (dB)
85
80
Input Referred
75
70
65
60
55
50
45
40
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 66. Common-Mode Rejection Ratio
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Application Information (continued)
+5V
Output Stage Offset
Compensation Circuit
10kW
0.1mF
4kW
-5V
RF
VIN
+VIN
RG+
50W
RG
FB
VOUT
VCA824
RG-VIN
+5V
50W
1kW
10kW
0.1mF
Input Stage and Multiplexer Core
Offset Compensation Circuit
-5V
Figure 67. Adjusting the Input and Output Voltage Sources
RF
in
RS
+VIN
RG+
eO
RG
FB
VCA824
eO
RG-VIN
*
4kTRS
in
RS
*
4kTRS
NOTE: RF and RG are noiseless.
Figure 68. Simple Noise Model
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Application Information (continued)
VG
inINPUT
VG
+VIN
V+
RS1
*
*
enINPUT
4kTRS1
FB
x1
RF
+RG
*
inINPUT
VOUT
RG
(Noiseless)
ICORE
eO
iinOUTPUT
-RG
VREF
x1
RF
enOUTPUT
-VIN
V-
4kTRF
*
*
RS2
enINPUT
iniOUTPUT
*
4kTRF
inINPUT
GND
*
4kTRS2
Figure 69. Full Noise Model
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Application Information (continued)
9.1.2 Differential Equalizer
If the application requires frequency shaping (the transition from one gain to another), the VCA824 can be used
advantageously because its architecture allows the application to isolate the input from the gain setting elements.
Figure 70 shows an implementation of such a configuration. The transfer function is shown in Equation 5.
RF
1 + sRGC1
´
G=2´
RG
1 + sR1C1
(5)
VIN1
RF
+VIN
RG+
RS
R1
FB
RG
VCA824
C1
RGVIN2
-VIN
20W
RS
Figure 70. Differential Equalizer
This transfer function has one pole, P1 (located at RGC1), and one zero, Z1 (located at R1C1). When equalizing an
RC load, RL and CL, compensate the pole added by the load located at RLCL with the zero Z1. Knowing RL, CL,
and RG allows the user to select C1 as a first step and then calculate R1. Using RL = 75-Ω, CL = 100pF and
wanting the VCA824 to operate at a gain of 2 V/V, which gives RF = RG = 453-kΩ, allows the user to select
C1 = 15.5 pF to ensure a positive value for the resistor R1. With all these values known, to achieve greater than
300 MHz bandwidth, R1 can be calculated to be 20-Ω. Figure 71 shows the frequency response for both the
initial, unequalized frequency response and the resulting equalized frequency response.
9
Equalized Frequency Response
6
3
Gain (dB)
0
Initial Frequency Response
of the VCA824 with RC Load
-3
-6
-9
-12
-15
-18
-21
-24
1M
10M
100M
1G
Frequency (Hz)
Figure 71. Differential Equalization of an RC Load
9.1.3 Differential Cable Equalizer
A differential cable equalizer can easily be implemented using the VCA824. An example of a cable equalization
for 100 feet of Belden Cable 1694F is illustrated in Figure 73, with Figure 72 showing the result for this
implementation. This implementation has a maximum error of 0.2 dB from DC to 70 MHz.
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Application Information (continued)
1694F Cable Attenuation (dB)
Equalizer Gain (dB)
2.0
1.5
1.0
Cable Attenuation
0.5
VCA824 Equalization
0
-0.5
-1.0
1
10
100
Frequency (MHz)
Figure 72. Cable Attenuation vs Equalizer Gain
Note that this implementation shows the cable attenuation side-by-side with the equalization in the same plot. For
a given frequency, the equalization function realized with the VCA824 matches the cable attenuation. The circuit
in Figure 73 is a driver circuit. To implement a receiver circuit, the signal is received differentially between the
+VIN and –VIN inputs.
VIN
R2
453W
+VIN
R8
50W
RG+
R18
13.6kW
R17
6kW
R21
3kW
R9
432W
RG-VIN
C6
320mF
FB
VREF
VCA824
C7
300mF
GND
VG
R1
20W
VOUT
R10
75W
VOUT
75W Load
R5
50W
C5
4pF
VG = +1VDC
C9
10mF
Figure 73. Differential Cable Equalizer
9.1.4 Voltage-Controlled Lowpass Filter [application sub]
In the circuit of Figure 74, the VCA824 serves as the variable-gain element of a voltage-controlled low-pass filter.
This section discusses how this implementation expands the circuit voltage swing capability over that normally
achieved with the equivalent multiplier implementation. The circuit control voltage, VG, is calculated as according
to the simplified relationship described in Equation 6.
VOUT
R2
1
=´
R 2C
VIN
R1
1+s
G
26
(6)
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Application Information (continued)
R2
332W
24pF
C
R1
332W
RF
1kW
VIN
24pF
+VIN
RG+
OPA690
RG
200W
FB
VCA824 Out
RG-VIN
50W
VOUT
20W
VG
Figure 74. Voltage-Control Low-Pass Filter
The response control results from amplification of the feedback voltage applied to R2. First, consider the case
where the VCA824 produces G = 1V/V. Then this circuit performs as if the amplifier were replaced by a short
circuit. Visually replacing the amplifier by a short leaves a simple voltage-feedback amplifier with a feedback
resistor bypassed by a capacitor. Replacing this gain with a variable gain, G, the pole can be written as shown in
Equation 7.
G
f8 =
2pR2C
(7)
Because the VCA824 is most linear in the midrange, the median of the adjustable pole should be set at VG = 0V
(see Figure 13, Figure 33, Figure 54, and Equation 8). Selecting R1 = R2 = 332Ω, and targeting a median
frequency of 10MHz, the capacitance (C) is 24pF. Because the OPA690 was selected for the circuit of Figure 74,
and in order to limit peaking in the OPA690 frequency response, a capacitor equal to C was added on the
inverting mode to ground. This architecture has the effect of setting the high-frequency noise gain of the OPA690
to 2V/V, ensuring stability and providing flat frequency response.
-0.8V £ VG £ 0.8V
(8)
Once the median frequency is set, the maximum and minimum frequencies can be determined by using VG =
–0.8 V and VG = 0.8 V in the gain equation of Equation 9. Note that this is a first-order analysis and does not
take into consideration the open-loop gain limitation of the OPA690.
RF
VG + 1
G=2´
´
RG
2
(9)
With the components shown, the circuit provides a linear variation of the low-pass cutoff from 2MHz to 20MHz,
using –1V ≤ VG ≤ 1V.
9.1.5 Wideband Variable Gain Amplifier Operation
The VCA824 provides an exceptional combination of high output power capability with a wideband, greater than
40dB gain adjust range, linear in V/V variable gain amplifier. The VCA824 input stage places the
transconductance element between two input buffers, using the output currents as the forward signal. As the
differential input voltage rises, a signal current is generated through the gain element. This current is then
mirrored and gained by a factor of two before reaching the multiplier. The other input of the multiplier is the
voltage gain control pin, VG. Depending on the voltage present on VG, up to two times the gain current is
provided to the transimpedance output stage. The transimpedance output stage is a current-feedback amplifier
providing high output current capability and high slew rate, 2500 V/μs. This exceptional full-power performance
comes at the price of relatively high quiescent current (36.5 mA), but low input voltage noise for this type of
architecture (6 nV/√Hz).
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Application Information (continued)
Figure 75 shows the dc-coupled, gain of 10 V/V, dual power-supply circuit used as the basis of Electrical
Characteristics- Vs = ± 5 V Electrical Characteristics: VS = ±5 V and Typical Characteristics. For test purposes,
the input impedance is set to 50-Ω with a resistor to ground and the output impedance is set to 50-Ω with a
series output resistor. Voltage swings reported in Electrical Characteristics- VS = ± 5 V are taken directly at the
input and output pins, while output power (dBm) is at the matched 50-Ω load. For the circuit in Figure 75, the
total effective load is 100-Ω ∥ 1-kΩ. Note that for the 14-pin, SOIC package, there is a voltage reference pin,
VREF (pin 9). For the 14-pin SOIC package, this pin must be connected to ground through a 20-Ω resistor to
avoid possible oscillations of the output stage. In the 10-pin, MSOP package, this pin is internally connected and
does not require such precaution. An X2Y® capacitor has been used for power-supply bypassing. The
combination of low inductance, high resonance frequency, and integration of three capacitors in one package
(two capacitors to ground and one across the supplies) enables the VCA824 to achieve the low second-harmonic
distortion reported in Electrical Characteristics- VS = ± 5 V.
®
0.1mF
+5V
X2Y Capacitor Detail
X2Yâ
Capacitor
(see detail)
+VS
-5V
A
G1
+
2.2mF
VG
B
-VS
+VIN
VIN
20W
x1
FB
IRG
RG+
RG
200W
G2
+ 2.2mF
RF
1kW
x2
RG-
VOUT
VOUT
x1
20W
VREF
-VIN
SO-14
VCA824
20W
Figure 75. DC-Coupled, AVMAX = 10 V/V, Bipolar Supply Specification and Test Circuit
9.2 Typical Application
A four-quadrant multiplier can easily be implemented using the VCA824. By placing a resistor between FB and
VIN, the transfer function depends upon both VIN and VG, as shown in Equation 10.
VOUT =
RF
RG
´ VG ´ VIN +
RF
RF
RG
-
R1
´ VIN
(10)
Setting R1 to equal RG, the term that depends only on VIN drops out of the equation, leaving only the term that
depends on both VG and VIN. VOUT then follows Equation 11.
RF
VOUT =
´ VIN ´ VG
RG
(11)
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Typical Application (continued)
R1
VG
RF
VIN
+VIN
RG+
FB
VCA824
R2
RS
Source
Impedance
RG
RG-VIN
20W
R3
Figure 76. Four-Quadrant Multiplier Circuit
Figure 77 illustrates the behavior of this circuit. Keeping the input amplitude of a 1-MHz signal constant and
varying the VG voltage (100 kHz, 2 VPP) gives the modulated output voltage shown in Figure 77.
9.2.1 Design Requirements
A multiplier requires two inputs, one for the X input and one for the Y input. The output of the multiplier circuit is
in the form of Vout = aVin1 × bVin2 : where a and b are real numbers and should not be negative. For four
quadrant operation both positive and negative inputs must be supported on the X and Y inputs.
A four-quadrant multiplier can easily be implemented using the VCA824. By placing a resistor between FB and
VIN, the transfer function depends upon both VIN and VG, as shown in Equation 10
9.2.2 Detailed Design Procedure
Setting R1 to equal RG, the term that depends only on VIN drops out of the equation, leaving only the term that
depends on both VG and VIN. VOUT then follows Equation 11.
The behavior of this circuit is illustrated in Figure 77. Keeping the input amplitude of a 1MHz signal constant and
varying the VG voltage (100 kHz, 2 VPP) gives the modulated output voltage shown in Figure 77.
9.2.3 Application Curve
1.5
fIN = 1MHz
fVG = 0.1MHz
Amplitude (V)
1.0
0.5
0
-0.5
VIN
VOUT
-1.0
VG
-1.5
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
Figure 77. Modulated Output Signal of the 4-Quadrant Multiplexer Circuit
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10 Power Supply Recommendations
High-speed amplifiers require low inductance power supply traces and low ESR bypass capacitors. When
possible both power and ground planes should be used in the printed circuit board design and the power plane
should be adjacent to the ground plane in the board stack-up. The power supply voltage should be centered on
the desired amplifier output voltage, so for ground referenced output signals, split supplies are required. The
power supply voltage should be from 7-V to 12-V.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the VCA824 requires careful attention to
printed circuit board (PCB) layout parasitics and external component types. Recommendations to optimize
performance include:
a. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. This recommendation
includes the ground pin (pin 2). Parasitic capacitance on the output can cause instability: on both the
inverting input and the noninverting input, it can react with the source impedance to cause unintentional band
limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise, ground and power planes should be unbroken
elsewhere on the board. Place a small series resistance (greater than 25-Ω) with the input pin connected to
ground to help decouple package parasitics.
b. Minimize the distance (less than 0.25”) from the power-supply pins to high-frequency 0.1-μF decoupling
capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections should always be decoupled with these capacitors.
Larger (2.2-μF to 6.8-μF) decoupling capacitors, effective at lower frequencies, should also be used on the
main supply pins. These capacitors may be placed somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
c. Careful selection and placement of external components preserve the high-frequency performance of the
VCA824. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good highfrequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin is the most sensitive to parasitic
capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other
network components, such as inverting or noninverting input termination resistors, should also be placed
close to the package.
d. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 mm to 2.54 mm) should be used,
preferably with ground and power planes opened up around them.
e. Socketing a high-speed part like the VCA824 device is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network,
which can make it almost impossible to achieve a smooth, stable frequency response. Best results are
obtained by soldering the VCA824 device onto the board.
11.1.1 Thermal Considerations
The VCA824 does not require heatsinking or airflow in most applications. The maximum desired junction
temperature sets the maximum allowed internal power dissipation as described in this section. In no case should
the maximum junction temperature be allowed to exceed 150°C.
Operating junction temperature (TJ) is given by Equation 12:
TJ = TA + PD ´ qJA
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Layout Guidelines (continued)
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in
the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current
times the total supply voltage across the part. PDL depends on the required output signal and load; for a
grounded resistive load, however, it is at a maximum when the output is fixed at a voltage equal to one-half of
either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS 2/(4 × RL), where RL
is the resistive load.
Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a
worst-case example, compute the maximum TJ using a VCA824ID (SO-14 package) in the circuit of Figure 75
operating at maximum gain and at the maximum specified ambient temperature of 85°C.
2
PD = 10V(38.5mA) + 5 /(4 ´ 100W) = 447.5mW
(13)
Maximum TJ = +85°C + (0.449W ´ 80°C/W) = 120.8°C
(14)
This maximum operating junction temperature is well below most system level targets. Most applications should
be lower because an absolute worst-case output stage power was assumed in this calculation of VCC/2, which is
beyond the output voltage range for the VCA824.
11.2 Layout Example
Figure 78. Layout Recommendation
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Product Folder Links: VCA824
31
VCA824
SBOS394E – NOVEMBER 2007 – REVISED JULY 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Demonstration Boards
Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the
VCA824 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered
with a user's guide. The summary information for these fixtures is shown in Table 1.
Table 1. EVM Ordering Information
PRODUCT
PACKAGE
BOARD PART NUMBER
LITERATURE REQUEST NUMBER
VCA824ID
SO-14
DEM-VCA-SO-1B
SBOU050
VCA824IDGS
MSOP-10
DEM-VCA-MSOP-1A
SBOU051
The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the
VCA824 product folder.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
X2Y is a registered trademark of X2Y Attenuators LLC.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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Copyright © 2007–2019, Texas Instruments Incorporated
Product Folder Links: VCA824
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
VCA824ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VCA824ID
VCA824IDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
BOT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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