VSP01M02ZWD

Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras Check for Samples: VSP01M01, VSP01M02 FEATURES – Two Level Drivers (VTRANSFER) × 3 – Two Level Drivers (ESHUTTER) × 1 – 450 pF to 1890 pF with 60 Ω to 240 Ω 1 • • • • • • • • • CCD Signal Processing: – 36-MHz Correlated Double Sampling (CDS) 16-Bit Analog-to Digital Conversion: – 36-MHz Conversion Rate – No Missing Codes Ensured 80-dB Input-Referred SNR (at 12-dB Gain) Programmable Black Level Clamping Programmable Gain Amplifier (PGA): – –9 dB to +44 dB –3 dB to +18 dB by Analog Front Gain –6 dB to +26 dB by Digital Gain Timing Generator: – Fully Programmable VRATE Timing by Serial I/O – Default Timing Supports Standard Operation – Flexible VRATE Pin Assignment – HD/VD Master or Slave Mode – External Trigger, Strobe Function Support – Flexible Draft or Pixel Summing Operation RG and HG Driver: – Programmable Drivability Control – Two Horizontal Transfer Independent Drivers – One Reset Gate Driver CCD Horizontal High-Speed Clock Phase Control: – Fine Step: 0.28 ns – Wide Step: 1/3 Pixel Rate Vertical CCD Driver: – 8-Channel VDRIVER with Sub-Driver – Supports Three-Field CCD Driving – Three Level Drivers (VTRANSFER) × 5 • • Flexible Voltage Operation: – AFET + TG: 2.7 V to 3.6 V – VL: –5.0 V to –9.0 V – VM: GND – VH: 11.5 V to 15.5 V – Low Power: 139 mW at 3.0 V, 36 MHz – Stand-By + Power-Save Mode: 36 mW – Stand-By Mode (MCK Off): 10 mW BGA-100 Package DESCRIPTION The VSP01M01 and VSP01M02 are complete mixedsignal ICs for charge-coupled device (CCD) signal processing with a built-in CCD timing generator, analog-to-digital converter (ADC), and CCD vertical driver. The AFE CCD channel has correlated double sampling to extract image information from the CCD output signal. Signal paths have gains ranging from –9 dB to +44 dB. The black level clamping circuit enables accurate black reference level and quick black level recovery after gain changes. An input signal clamp with CDS offset adjustment function is available. The system synchronizes the master clock, horizontal driver (HD), and vertical driver (VD). The VSP01M01 and VSP01M02 support all signal terminals required by CCD architecture. The RG driver, HG driver, and vertical driver synchronize the ADC clock phase in order to realize ideal performance. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VSP01M01ZWD (2) BGA-100 ZWD –25°C to +85°C VSP01M01 VSP01M01GWD BGA-100 GWD –25°C to +85°C VSP01M01 VSP01M02ZWD (2) BGA-100 ZWD –25°C to +85°C VSP01M02 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY VSP01M01ZWD Tray, 360 VSP01M01ZWDR Tape and Reel VSP01M01GWD Tray, 360 VSP01M01GWDR Tape and Reel VSP01M02ZWD Tray, 360 VSP01M02ZWDR Tape and Reel For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The package is Pb-free. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. PARAMETER Supply voltage VSP01M01, VSP01M02 UNIT AVDD –0.3 to +4.0 V DRVDD –0.3 to +4.0 V VDD5 –0.3 to +6.0 V VL GND to –10 V VH VL + 26 V Supply voltage differences AVDD, DRVDD ±0.1 V Ground voltage differences VSS ±0.1 V Digital input voltage –0.3 to (DVDD + 0.3) V Analog input voltage –0.3 to (AVDD + 0.3) V ±10 mA Ambient temperature under bias –25 to +85 °C Storage temperature –55 to +125 °C Junction temperature +150 °C Package temperature (IR reflow, peak) +250 °C Input current (any pins except supplies) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. PARAMETER Analog supply voltage Digital supply voltage Driver supply voltage MIN TYP MAX AVDD 2.7 3.0 3.6 V DVDD 2.7 3.0 3.6 V VDD5 3.0 5.5 V VL –9.0 –5.0 V VH 11.5 15.5 V Digital input logic family Digital input clock frequency CMOS MCK 12 SCLK Digital output load capacitance Operating free-air temperature 2 UNIT TA –25 Submit Documentation Feedback 36 MHz 20 MHz 10 pF +85 °C Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution VSP01M01 only 10 Bits VSP01M02 only 12 Bits CONVERSION/CLOCK RATE Conversion/clock rate 36 MHz ANALOG INPUT (CCDIN) Input signal level for full-scale out CDS gain = 0 dB, DPGA gain = 0 dB 1000 mV Maximum input range CDS gain = –3 dB, DPGA gain = 0 dB 1300 mV Input capacitance 15 Input limit –0.3 pF 3.3 V TRANSFER CHARACTERISTICS Differential nonlinearity Integral nonlinearity DNL CDS gain = 0 dB, DPGA gain = 0 dB ±0.25 LSB INL CDS gain = 0 dB, DPGA gain = 0 dB ±0.5 LSB No missing codes Ensured Step response settling time Full-scale step input 1 Pixel Step input from 1.8 V to 0 V 2 Pixels 9 Clocks Grounded input capacitor, PGA gain = 0 dB 76 dB Overload recovery time Data latency Signal-to-noise ratio (1) Grounded input capacitor, analog gain = +12 dB CCD offset correction range 68 –200 dB 200 mV INPUT CLAMP Clamp on-resistance 400 Ω Clamp level 1.5 V PROGRAMMABLE ANALOG FRONT GAIN (CDS) Minimum gain Gain code = 111b –3 dB Default gain Gain code = 000b 0 dB Medium gain 1 Gain code = 001b 6 dB Medium gain 2 Gain code = 010b 12 dB Maximum gain Gain code = 011b 18 dB 0.5 dB Gain control error PROGRAMMABLE DIGITAL GAIN (DPGA) Programmable gain range –6 Gain step 26 dB 0.03125 dB 10 Bits OPTICAL BLACK CLAMP LOOP Control DAC resolution Loop time constant Programmable range of clamp level Optical black clamp level (VSP01M01 only) 16 OBCLP level at code = 01000b Optical black clamp level (VSP01M02 only) OBCLP level at code = 01000b OB level program step 78 32 OB level program step Programmable range of clamp level (1) μs 40.7 LSB 2 64 LSB LSB 312 LSB 128 LSB 8 LSB SNR = 20 log (full-scale voltage/rms noise). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 3 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS Logic family Input voltage CMOS VT+ Low to high threshold voltage 1.7 V VT– High to low threshold voltage 1.0 V IIH Logic high, VIN = +3 V ±20 μA IIL Logic low, VIN = 0 V ±20 μA Input current Input capacitance Maximum input voltage –0.3 5 pF DVDD + 0.3 V DIGITAL OUTPUTS (DATA) Logic family CMOS Logic coding Output voltage Straight Binary VOH Logic high VOL Logic low Additional output data delay 2.4 V 0.4 V Output data delay code = 00b 0 ns Output data delay code = 01b 2 ns Output data delay code = 10b 4 ns Output data delay code = 11b 6 ns Logic high (VOH) IOH = 0 mA VDD5 – 0.05 V Logic high (VOH) IOH = –6.8 mA VDD5 – 0.6 HDRIVER OUTPUTS Output voltage RG, HL Logic low (VOL) IOL = 6.8 mA Output voltage (HG1A, HG1B, HG2A, HG2B) V 0.4 V Logic high (VOH) IOH = 0 mA VDD5 – 0.05 V Logic high (VOH) IOH = –13.6 mA (max), –6.8 mA (min) VDD5 – 0.6 V Logic low (VOL) IOL = 13.6 mA (max), 6.8 mA (min) 0.4 V TG OUTPUTS Output voltage (V0N-V12N, P0-P5, SUBN, FIELD, STROBE, MSHUT, SUBSW1, SUBSW2, ADCCK, HD, VD) Logic high (VOH) IOH = –1.7 mA Logic low (VOL) IOL = 1.7 mA Logic high (VOH) IOH = –1.7 mA TP output voltage (TPP, TPD) DVDD – 0.6 V 0.4 DVDD – 0.6 Logic low (VOL) IOL = 1.7 mA V V 0.4 V VDRIVER OUTPUTS Output current (V1, V2, V3A, V3B, V4, V5A, V5B, V6) (VL = –9.0 V, VM = 0 V, VH = 15.5 V) 4 IOL V1, V2, V3A, V3B, V4, V5A, V5B, V6 = –8.1 V IOM1 V1, V2, V3A, V3B, V4, V5A, V5B, V6 = –0.2 V IOM2 V1, V3A, V3B, V5A, V5B = 0.2 V IOH V1, V3A, V3B, V5A, V5B = 14.55 V IOSL SUB = –8.1 V IOSH SUB = 14.55 V Submit Documentation Feedback 10 mA –5.0 5 mA mA –7.2 5.4 mA mA –4 mA Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP01M01ZWD, VSP01M01GWD, VSP01M02ZWD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.7 3.0 3.6 V 5.5 V V POWER SUPPLY AVDD DVDD Supply voltage VDD5 for HG1A, HG1B, HG2A, HG2B, HL, RG VL for V1, V2, V3A, V3B, V4, V5A, V5B, V6 –9 –5 VH for V1, V2, V3A, V3B, V4, V5A, V5B, V6 11.5 15.5 Power dissipation AFE Power dissipation TG + H, RDRIVER Power dissipation VDRIVER 3.0 Normal operation mode: no CCD load (at 3.0 V, 38 MHz) mW 50 mW 4 mW 139 mW Standby + power-save mode (at 3.0 V, 38 MHz) 36 mW Master clock off mode (at 3.0 V) 10 mW Power dissipation (total) without CCD load Power dissipation (total) V 85 TEMPERATURE RANGE Operating temperature Thermal resistance –25 θJA At 165 mW power dissipation with load +85 46.18 °C °C/W SWITCHING CHARACTERISTICS All specifications at TA = +25°C, all power supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. PARAMETER Propagation delay time Rise time Fall time Output noise voltage TEST CONDITIONS MIN TYP MAX UNIT tPLM 15 100 ns tPMH 20 100 ns tPLH 20 100 ns tPML 15 50 ns tPHM 30 50 ns tPHL 30 50 ns tTLM VL → VM 300 ns tTMH VM → VH 300 ns tTLH VL → VH 300 ns tTML VM → VL 300 ns tTHM VH → VM 300 ns tTHL VH → VL 300 ns VCLH 2.0 V VCLL 2.0 V VCMH 2.0 V VCML 2.0 V VCHL 2.0 V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 5 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com PIN CONFIGURATION VSP01M01ZWD, VSP01M01GWD BGA PACKAGE (BOTTOM VIEW) 1 2 3 4 5 6 7 8 9 10 A DAC1 V12N CH2N V6N NC V1N V0N NC NC CH0N B DAC2 V11N V10N V8N V7N CH1N NC CH3N B8 NC C CCDIN CCDGND V9N V3N V4N V2N CH5N B9 B6 B7 D COB BYP BYP2 AVDD DVSS DVSS DRVDD CH4N B4 B5 E CM BYPM REFN AVDD AVSS AVSS DRVDD B3 B1 B2 F REFP V5N NC AVDD AVSS AVSS DRVDD V2 B0 SUB G BYPD V3B TPD DVSS VL VH VDD5 VSS5 VSS5 NC H TPP SYSRST RLOAD V5A V3A STROBE VDD5 V6 RG H1A J SDATA SCLK TRIG VD SUBSW1 MSHUT SUBN HL V4 ADCCK K MCK CS HD SUBSW2 V1 FIELD V5B H2A H1B H2B PIN CONFIGURATION VSP01M02ZWD BGA PACKAGE (BOTTOM VIEW) 6 1 2 3 4 5 6 7 8 9 10 A DAC1 V12N CH2N V6N NC V1N V0N NC NC CH0N B DAC2 V11N V10N V8N V7N CH1N NC CH3N B10 B1 C CCDIN CCDGND V9N V3N V4N V2N CH5N B11 B8 B9 D COB BYP BYP2 AVDD DVSS DVSS DRVDD CH4N B6 B7 E CM BYPM REFN AVDD AVSS AVSS DRVDD B5 B3 B4 F REFP V5N NC AVDD AVSS AVSS DRVDD V2 B2 SUB G BYPD V3B TPD DVSS VL VH VDD5 VSS5 VSS5 B0 H TPP SYSRST RLOAD V5A V3A STROBE VDD5 V6 RG H1A J SDATA SCLK TRIG VD SUBSW1 MSHUT SUBN HL V4 ADCCK K MCK CS HD SUBSW2 V1 FIELD V5B H2A H1B H2B Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Table 2. TERMINAL FUNCTIONS TERMINAL (1) (2) (3) (4) NAME PIN TYPE (1) DAC1 A1 DO DAC1 output V12N A2 DO Vertical rate signal 12N CH2N A3 DO Universal vertical rate signal 2N (for V3A) V6N A4 DO Vertical rate signal 6N (for V6) DESCRIPTION NC A5 — No connection V1N A6 DO Vertical rate signal 1N (for V1) V0N A7 DO Vertical rate signal 0N NC A8 — No connection NC A9 — No connection CH0N A10 DO Universal vertical rate signal 0N DAC2 B1 DO DAC2 output V11N B2 DO Vertical rate signal 11N V10N B3 DO Vertical rate signal 10N V8N B4 DO Vertical rate signal 8N V7N B5 DO Vertical rate signal 7N CH1N B6 DO Universal vertical rate signal 1N (for V1) NC B7 — No connection CH3N B8 DO Universal vertical rate signal 3N (for V5A) B8 B9 DO Data out bit 8 (VSP01M01 only) B10 B9 DO Data out bit 10 (VSP01M02 only) NC B10 — No connection (VSP01M01 only) B1 B10 DO Data out bit 1 (VSP01M02 only) CCDIN C1 AI CCD signal input CCDGND C2 AI CCD signal input ground V9N C3 DO Vertical rate signal 9N V3N C4 DO Vertical rate signal 3N (for V3A, V3B) V4N C5 DO Vertical rate signal 4N (for V4) V2N C6 DO Vertical rate signal 2N (for V2) CH5N C7 DO Universal vertical rate signal 5N (for V5B) B9 C8 DO Data out bit 9 (MSB) (VSP01M01 only) B11 C8 DO Data out bit 11 (MSB) (VSP01M02 only) B6 C9 DO Data out bit 6 (VSP01M01 only) B8 C9 DO Data out bit 8 (VSP01M02 only) B7 C10 DO Data out bit 7 (VSP01M01 only) B9 C10 DO Data out bit 9 (VSP01M02 only) COB D1 AO OB loop feedback capacitor (2) BYP D2 AO Internal reference (3) BYP2 D3 AO Internal reference (4) AVDD D4 P Analog power supply DVSS D5 P Ground DVSS D6 P Ground Designators by type: P: power-supply and ground, DI: digital input, DO: digital output, DI/O: digital input and output, AI: analog input, AO: analog output, and VDO: VDRIVER digital output. Should be connected to ground with a bypass capacitor. The recommended value is 0.1 μF to 0.22 μF; however, actual value depends on the application environment. Refer to the OB Loop and OB Clamp Level section for more detail. Should be connected to ground with a bypass capacitor (0.1 μF). Refer to the Voltage Reference section for more detail. Should be connected to ground with a bypass capacitor. The recommended value is 400 pF to 1000 pF; however, actual value depends on the application environment. Refer to the Voltage Reference section for more detail. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 7 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Table 2. TERMINAL FUNCTIONS (continued) TERMINAL (5) (6) 8 TYPE (1) NAME PIN DESCRIPTION DRVDD D7 P CH4N D8 DO Universal vertical rate signal 4N (for V3B) B4 D9 DO Data out bit 4 (VSP01M01 only) B6 D9 DO Data out bit 6 (VSP01M02 only) B5 D10 DO Data out bit 5 (VSP01M01 only) B7 D10 DO Data out bit 7 (VSP01M02 only) CM E1 AO Internal reference (3) BYPM E2 AO Internal reference (4) REFN E3 AO Internal reference (3) AVDD E4 P Analog power supply AVSS E5 P Ground AVSS E6 P Ground DRVDD E7 P Digital output power supply B3 E8 DO Data out bit 3 (VSP01M01 only) B5 E8 DO Data out bit 5 (VSP01M02 only) B1 E9 DO Data out bit 1 (VSP01M01 only) B3 E9 DO Data out bit 3 (VSP01M02 only) B2 E10 DO Data out bit 2 (VSP01M01 only) B4 E10 DO Data out bit 4 (VSP01M02 only) REFP F1 AO Internal reference (5) V5N F2 DO Vertical rate signal 5N (for V5A, V5B) NC F3 — No connection AVDD F4 P Analog power supply AVSS F5 P Ground AVSS F6 P Ground DRVDD F7 P Digital output power supply V2 F8 VDO B0 F9 DO Data out bit 0 (LSB) (VSP01M01 only) B2 F9 DO Data out bit 2 (VSP01M02 only) SUB F10 VDO BYPD G1 AO DLL bypass (6) VDRIVER out 3B Digital output power supply VDRIVER out 2 VDRIVER out for CCD electric shutter V3B G2 VDO TPD G3 DO DVSS G4 P Ground VL G5 P VDRIVER power supply VH G6 P VDRIVER power supply VDD5 G7 P Digital power supply VSS5 G8 P Digital ground VSS5 G9 P Digital ground NC G10 — No connection (VSP01M01 only) Test pin for SHD, CLPDM, HDIV B0 G10 DO Data out bit 0 (LSB) (VSP01M02 only) TPP H1 DO Test pin for SHP, CLPOB, PBLK, HBLK SYSRST H2 DI Asynchronous reset RLOAD H3 DI Register load Should be connected to ground with a bypass capacitor (0.1 μF). Refer to the Voltage Reference section for more detail. Should be connected to ground with a bypass capacitor. The recommended value is 1000 pF to 0.1 μF; however, actual value depends on the application environment. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Table 2. TERMINAL FUNCTIONS (continued) TERMINAL NAME PIN TYPE (1) V5A H4 VDO VDRIVER out 5A V3A H5 VDO VDRIVER out 3A STROBE H6 DO VDD5 H7 P V6 H8 VDO RG H9 DO CCD reset gate signal DESCRIPTION Strobe signal Digital power supply VDRIVER out 6 H1A H10 DO CCD horizontal transfer signal 1A SDATA J1 DI Serial data SCLK J2 DI Serial data clock TRIG J3 DI External trigger VD J4 DI/O Vertical sync SUBSW1 J5 DO CCD substrate signal switch 1 MSHUT J6 DO Mechanical shutter signal SUBN J7 DO CCD electric shutter (for SUB) HL J8 DO CCD horizontal transfer signal V4 J9 VDO ADCCK J10 DO Clock for digital output buffer MCK K1 DI Master clock CS K2 DI Chip select HD K3 DI/O Horizontal sync SUBSW2 K4 DO CCD substrate signal switch 2 V1 K5 VDO FIELD K6 DO VDRIVER out 4 VDRIVER out 1 Field index signal V5B K7 VDO H2A K8 DO VDRIVER out 5B CCD horizontal transfer signal 2A H1B K9 DO CCD horizontal transfer signal 1B H2B K10 DO CCD horizontal transfer signal 2B Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 9 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com FUNCTIONAL BLOCK DIAGRAM BYP2 COB BYP BYPM REFP CM REFN BYPD VDD5 AVDD DRVDD Internal Reference Buffer Current DAC Decoder Digital Output DPGA and Output Register CCD Out Signal PBLK 16-Bit ADC CDS CCDIN ADCCK CLPOB Gain Setting CCGND SHP/SHD ADCCK Clamp CLPDM RG HL HG1A HG2A HG1 HG2 MCK SDATA Horizontal Timing Generator and Driver SCLK CS Serial Interface and Register TRIG STDBY RLOAD HDIV HBLK Drive HD VD P0-P5 V0N-V12N FIELD STROBE MSHUT SUBSW1 SUBSW2 SYSRST DAC OUTPUT 1 8-Bit DAC DAC OUTPUT 2 8-Bit DAC Vertical Timing Generator SUBN P1 V1N V2N P2 V3N P4 V4N P3 V5N P5 V6N VDRIVER SUB SUB V1 V1 V2 V2 V3A V3A V3B V3B V4 V4 V5A V5A V5B V5B V6 V6 VSS 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs www.ti.com VSP01M01 VSP01M02 SBES016 – MARCH 2009 TIMING CHARACTERISTICS TG HIGH-SPEED PULSE TIMING tMCKP MCK tRGW tCKP/4 tCKP/2 tMCKPG tCKP RG tH1R HG1 HL tH1F HG2 tH2R tH2F tLHR N (pix) CCD tS tPF tPR SHP tS tDR SHD tDF tADCKR tINHIBIT ADCCK tHOLD tOD B[9:0] B[11:0] B[15:0] NOTE: Dashed lines indicate programmable parameters. Figure 1. TG High-Speed Pulse Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 11 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Table 3. Timing Characteristics for Figure 1 PARAMETER tMCKP tMCKRG (3) 12 TYP 27.7 (1) MCK rising edge to RG rising edge MAX UNIT 83.3 ns 14 tCKP Pixel rate 27.7 tRGW RG rising edge to RG falling edge (2) tCKP/4 – 16tCKP/100 tH1R RG rising edge to HG1 rising edge (2) ns 83.3 ns tCKP/4 tCKP/4 + 15tCKP/100 ns –16tCKP/100 0 15tCKP/100 ns tH1F RG rising edge to HG1 falling edge (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 ns tH2R RG rising edge to HG2 rising edge (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 ns tH2F RG rising edge to HG2 falling edge (2) –16tCKP/100 0 +15tCKP/100 ns tLHR RG rising edge to HL rising edge (2) –16tCKP/100 0 +15tCKP/100 ns tLHF RG rising edge to HL falling edge (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 ns tPF RG rising edge to SHP falling edge (2) tCKP/4 – 16tCKP/100 tCKP/4 tCKP/4 + 15tCKP/100 + 6 ns tPR (2) tCKP/2 – 16tCKP/100 tCKP/2 tCKP/2 + 15tCKP/100 + 6 ns tDF RG rising edge to SHD falling edge (2) 3tCKP/4 – 24tCKP/100 3tCKP/4 – 8tCKP/100 3tCKP/4 + 7tCKP/100 + 6 ns tDR RG rising edge to SHD rising edge (2) –24tCKP/100 –8tCKP/100 7tCKP/100 + 6 ns –50tCKP/100 0 49tCKP/100 ns tADCKR (1) (2) MIN MCK clock period RG rising edge to SHP rising edge RG rising edge to ADCCK rising edge tS Sampling delay for SHP and SHD tINHIBIT Inhibited clock period (3) 4 tADC ADCCK duty tDOD Data out delay (register setting 002h) tHOLD Output hold time tOD Output delay (no load) DL Data latency 3 7 ns 10 ns 6 ns 50 0 0 % 2 + tDOD ns 27 + tDOD 9 (fixed) ns tCKP cycles Pulse phase can be programmed through the serial interface. RG pulse width can be programmed through the serial interface. Refer to the High-Speed Pulse Adjustment section of the TG (Timing Generator) Section for details. ADCCK phase can also be programmed as a 90-degree step through the serial interface. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 SLAVE MODE: VD, HD SPECIFICATIONS VD, HD Detect The odd field of the two-field CCD operation and the first field of the even field operation is detected by the VD and HD phase. The delay limit of the VD and HD phase is specified in Figure 2 and Figure 3. tVD VD MCK tODD HD-VD tODD VD-HD VD After HD tHD HD HD After VD HD Figure 2. VD, HD Falling Edge Detect VD MCK tODD HD-VD tODD VD-HD VD After HD HD HD After VD HD Figure 3. VD, HD Rising Edge Detect Table 4. Timing Characteristics for Figure 2 and Figure 3 PARAMETER (1) MIN TYP (1) MAX UNIT tVD VD trail-to-trail 10 τ (MCK cycles) tHD HD trail-to-trail 10 τ (MCK cycles) tODD HD-VD VD trail delay limit for ODD detect (register setting 02Fh[2:0]) 0 1 6 τ (MCK cycles) tODD HD-VD HD trail delay limit for ODD detect (register setting 02Fh[5:3]) 0 1 6 τ (MCK cycles) The VD, HD edge is detected by the rising edge of MCK. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 13 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com HCOUNTER Reset HCOUNTER is reset via HD detection. The timing is shown in Figure 4 and Figure 5. tHCNT-latency HD MCK tCH3 tCH1 N - 1 (pix) P[12:0] N (pix) Start (pix) M (H) H[11:0] M + 1 (H) Figure 4. HD Falling Edge Detect tHCNT-latency HD MCK tCH3 tCH1 N - 1 (pix) P[12:0] N (pix) Start (pix) M (H) H[11:0] M + 1 (H) Figure 5. HD Rising Edge Detect Table 5. Timing Characteristics for Figure 4 and Figure 5 (1) REGISTER PARAMETER 14 MCK EDGE 020h[2] MIN TYP MAX UNIT tCH1 HD falling edge to MCK rising edge 0 (falling) 0 (rising) –6 1 ns tCH2 HD rising edge to MCK rising edge 1 (rising) 0 (rising) –6 1 ns tCH3 HD falling edge to MCK falling edge 0 (falling) 1 (falling) –4 3 ns tCH4 HD rising edge to MCK falling edge 1 (rising) 1 (falling) –4 3 ns tHCNT- HCOUNTER reset latency (register setting 034h[3:0]) — — LATENCY (1) VD, HD EDGE 020h[3] 6 τ (MCK cycles) HCOUNTER reset timing is selected by MCK edge polarity. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 MASTER MODE: HD, VD SPECIFICATIONS The HD, VD MCK timing is shown in Figure 6 and Figure 7. VD tMCK-VD tMCK-VD MCK Figure 6. VD MCK Specification HD tMCK-HD tMCK-HD MCK Figure 7. HD MCK Specification Table 6. Timing Characteristics for Figure 6 and Figure 7 PARAMETER MIN TYP MAX UNIT tMCK-VD MCK rising edge to VD falling edge 10 ns tMCK-HD MCK rising edge to HD falling edge 10 ns SERIAL INTERFACE TIMING SPECIFICATION The serial interface has two writing modes: standard and continuous write. These modes are shown in Figure 8 and Figure 9. tXS tXH tXS CS tXHS tCKH tCKL tCKP SCLK tDS SDATA tDH Address LSB Address MSB 10 Bits Data LSB Data MSB Data Width tDLLC tDLLC tDLLC Activated Sent DATA Toggling of HA Figure 8. Standard Mode Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 15 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com CS SCLK Address LSB SDATA Address MSB Data MSB Data LSB Data Width 10 Bits Activated Sent DATA Data LSB Data MSB Data Width tDLLC tDLLC tDLLC Toggling of HA tDLLC tDLLC Figure 9. Continuous Write Mode Timing Table 7. Timing Characteristics for Figure 8 and Figure 9 PARAMETER MIN TYP MAX UNIT tCKP Clock period 50 ns tCKH Clock high pulse width 25 ns tCKL Clock low pulse width 25 ns tDS Data setup time 15 ns tDH Data hold time 15 ns tXS SLOAD to SCLK setup time 20 ns ns tXH SCLK to CS hold time 20 tXHS CS width 20 tDLLC Data load latency clock ns 10 MCK CLK Data shift operation should decode at the rising edges of SCLK while CS is low. Parallel latch timing for each mode is described in Table 8. Table 8. Parallel Latch MODE PARALLEL LATCH TIMING Standard write Rising edge of CS Continuous write End of data (MSB) In addition to the parallel latch, there are several registers dedicated to the specific features of the device; these registers are synchronized with MCK. It takes less than 10 clock cycles for the data in the parallel latch to be written to these registers. Therefore, to complete the data updates, it requires less than 10 clock cycles after parallel latching. Toggling of HA is inhibited from parallel latch. Refer to the Serial interface (SPI) section of the Common Section for details. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs www.ti.com VSP01M01 VSP01M02 SBES016 – MARCH 2009 EQUIVALENT CIRCUITS Figure 10 shows the HG1A, HG1B, HG2A, and HG2B high-speed driver and load model. The driver supports up to 150 pF. Figure 11 shows the RG and HL high-speed driver and load model. The driver supports up to 10 pF. Figure 10. HG Driver and Load Model RR CR 10pF Figure 11. RG Driver and Load Model Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 17 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com COMMON SECTION REGISTER/MEMORY MAP Figure 12 shows the TG register/memory map, which has 1024 words of 32-bit instruction (max). The 256-word register area enables active instruction, which requires dynamic operation. The 768-word memory area enables static instruction, which is almost fixed during a frame rate. Address Data 22 Bits (maximum) 10-Bit 000h 00 0000 0000b 6-Bit Register (active control) 192 Words (maximum) 0BFh 00 1011 1111b 0C0h 00 1100 0000b 0FFh 00 1111 1111b 100h 01 0000 0000b 16-Bit Register (reserved) 64 Words (maximum) #1 (100h) #2 (120h) #3 (140h) 17Fh 01 0111 1111b #4 (160h) 180h 01 1000 0000b VA1 (180h) Memory [vertical high-speed transfer(HS) #1-4] 128 Words (maximum) VA2 (190h) VA3 (1A0h) VA4 (1B0h) Memory (vertical timing: VA1-VA8) VA5 (1C0h) 128 Words (maximum) (1) VA6 (1D0h) VA7 (1E0h) 1FFh 01 1111 1111b VA8 (1F0h) 200h 10 0000 0000b HA Address 0 Memory (horizontal timing: HA) 512 Words (maximum) 3FFh 11 1111 1111b 511 NOTE: Shaded cells indicate the area under discussion. (1) Refer to the TG Instruction Hierarchy section of the TG (Timing Generator) Section for details. Figure 12. VSP01M01/VSP01M02 TG Register/Memory Map 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 SERIAL INTERFACE (SPI) The SPI functions and timings are controlled through the serial interface, which is composed of three signals: SDATA, SCLK, and CS. SDATA data are sequentially stored to the shift register at the rising edge of SCLK. Before a write operation, CS must go low, and remain low during writing. Refer to Serial Interface Timing Specification for further details. The serial interface command is composed of a 10-bit address and 6-bit, 16-bit, or 22-bit data. Table 9 shows the data width for each address area. Table 9. Address Data Width (1) (1) ADDRESS (10-Bit) DATA WIDTH (Bits) USAGE 000h-0BFh 6 Register 100h-17Fh 16 HS memory 180h-3FFh 22 HA and VA memory Refer to Register/Memory Map for details. The SPI has two write modes: standard and continuous. Standard Write Mode The VSP01M01 and VSP01M02 support a standard write mode, as shown in Figure 13. Normally, a serial interface command is sent by one address and data combination. The 10-bit address should primarily be sent LSB first; the following 6-bit, 16-bit, or 22-bit data should also sent LSB first. 6-bit, 16-bit, or 22-bit data are stored in the respective register by the 10-bit address at the rising edge of CS. The stored serial command data change immediately at rising edge of CS or are reserved by programmable control. If the data bit does not contain either 6-bits, 16-bits, or 22-bits at the end of the data stream, any empty data bits are ignored. CS CS SCLK SCLK SDATA A0 A9 10-Bit Address D0 D5 A0 SDATA A9 10-Bit Address 6-Bit Data D0 D21 22-Bit Data b) 22-Bit Memory Area a) 6-Bit Register Area CS SCLK SDATA A0 A9 10-Bit Address D0 D15 16-Bit Data c) 16-Bit Memory Area Figure 13. SPI Standard Write Mode Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 19 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Continuous Write Mode These devices also support a continuous write mode, as shown in Figure 14. When the input serial data are longer than one set of instructions, the following data stream is automatically recognized as the data of the next address. In this mode, 6-bit, 16-bit, or 22-bit serial command data are stored to the respective registers immediately when those data are fetched. Address and data should be sent LSB first, in the same way as standard write mode. If the data bit does not contain either 6-bits, 16-bits, or 22-bits at the end of the data stream, any empty data bits are ignored. CS SCLK SDATA A0 A9 D0 10-Bit Address D5 D0 6-Bit Data D5 D0 6-Bit Data D5 6-Bit Data a) 6-Bit Register Area CS SCLK SDATA A0 A9 D0 10-Bit Address D15 D0 16-Bit Data D15 D0 16-Bit Data D15 16-Bit Data b) 16-Bit Memory Area CS SCLK SDATA A0 A9 10-Bit Address D0 D21 22-Bit Data D0 D21 D0 22-Bit Data D21 22-Bit Data c) 22-Bit Memory Area Figure 14. SPI Continuous Write Mode 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Mode Confusion If 22 bits of data are sent to a 6-bit register area, the SPI recognizes continuous write mode, because usually only 6-bit data should be sent to 6-bit register area in standard write mode, as shown in Figure 15. The end-ofdata point is recognized by the rising edge of CS. CS A0 SDATA A9 D0 D21 10-Bit Address (6-Bit Register Area) SPI Recognition A0 22-Bit Data A9 D0 10-Bit Address (Add A) D5 D0 D5 D0 D0 6-Bit Data (Store to Add A + 2) 6-Bit Data (Store to Add A + 1) 6-Bit Data (Store to Add A) D5 D3 Ignored Figure 15. Mode Confusion SPI recognition is shown in Table 10. Table 10. SPI Recognition DATA WIDTH (1) (2) (3) ADDRESS AREA 6-BIT 16-BIT 22-BIT 32-BIT 6-bit register Standard (1) (one word) Continuous (2) (two words) Continuous (three words) Continuous (five words) 16-bit memory Ignored Standard (one word) Standard (3) (one word) Continuous (two words) 22-bit memory Ignored Ignored Standard (one word) Standard (one word) Shaded cells indicate standard operation. Continuous = continuous write mode. Standard = standard write mode. Read and Write Batting Address 100h-3FFh is the memory area. HA, VA, and HS access this memory area to read programs. If the SPI writes to the memory area during a program read, the programmed operation is cancelled. SPI operation should be done with TG disable. If SPI operation must be done with TG enable (TG operating), the SPI must write for a no-read term (no toggling term). For the register area (000h-0FFh), this precaution is not necessary. REGISTER UPDATE The update timing of each register is specified in Table 11. Table 11. Updated Timing REGISTER ADDRESS 000h UPDATE TIMING Real time 001h-01Fh Timing specified at bits 0-2 of 000h (AFE update) 020h-035h Real time 036h[2:0] VD; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details. 036h[5:3] TRIG; refer to the CCD Timing Composition section of the TG (Timing Generator) Section for details. 037h-0FFh Timing specified at bit 3 of 000h (TG update) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 21 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com The AFE register is updated in real time by the RLOAD pin or VD, as shown in Table 12. Table 12. Update Select Register (AFE) PARAMETER REGISTER ADDRESS AFE UPDATE 000h[0] AFE UP POL 000h[2:1] DESCRIPTION 0 = Real-time update (default) 1 = Updated by RLOAD pin or VD AFE register update signal and polarity 00b = RLOAD rising edge (default) 10b = VD rising edge 01b = RLOAD falling edge 11b = VD falling edge The TG register can be updated at a specified line number through VA instruction. The update method selection is described in Table 13. In general, this function is used for SUBN control. Table 13. Update Select Register (TG) PARAMETER REGISTER ADDRESS TG UPDATE 000h[3] DESCRIPTION 0 = Real-time update (default) 1 = Updated by VA instruction line number Refer to the Vertical Sequence section for VA instruction details. MCK STOP DETECT The MCK stop detect function is supported, as shown in Table 14. If an MCK stop was detected, all register values are cleared. After an MCK stop detect, a SYSRST is required. Table 14. MCK Stop Detect Register PARAMETER REGISTER ADDRESS MCK detect 020h[4] DESCRIPTION 0 = Disabled 1 = Enabled (default) STANDBY FUNCTION For increased power savings, this device can be put into a standby mode (power-down mode) through serial interface control when the device is not in use. In this mode, all function blocks are disabled. Current consumption drops to about 2 mA. Because all the bypass capacitors discharge during this mode, a substantial time (usually on the order of 200 ms to 300 ms) is required to return from standby mode. A four-part standby is selected independently, as described in Table 15. Table 15. Standby Control Register SECTION REGISTER ADDRESS DESCRIPTION SIGNAL STATUS IN STANDBY TG 020h[0] 0 = Standby (default) 1 = Normal operation Refer to the Signal section of the TG (Timing Generator) Section . AFE 001h[0] 0 = Normal operation (default) 1 = Standby Digital output = high impedance DAC1 001h[1] 0 = Enabled 1 = Disabled (Standby) (default) Analog output = low DAC2 001h[2] 0 = Enabled 1 = Disabled (Standby) (default) — AFE standby, DAC1 standby, or DAC2 standby should be completed before TG standby if using the VD update method for the the AFE section. If the AFE standby is completed after TG standby, the AFE standby, DAC1 standby, or DAC2 standby are not activated. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 SYSTEM RESET All parameters are reset to the respective default values when the SYSRST pin goes low asynchronously with respect to the system clock. All register and memory values are cleared by SYSRST. SYSRST should be pulled up for operation. Figure 16 shows typical SYSRST implementation with a pull-up resistor. SYSRST Figure 16. SYSRST Pin POWER-UP SEQUENCE When the device is powered up, follow this recommended sequence: 1. Turn on the power supplies for the device. 2. Apply the master clock input to the MCK, VD, and HD signals. 3. Input the serial data for the 6-bit register setting. Input SRG for 16-bit serial data. (10-bit address + 6-bit data). TG disable must be complete. (020h[0] = 0) 4. Input the serial data for VHIGH SPEED transfer toggling. Input SRG for 26-bit serial data. (10-bit address + 16-bit data) 5. Input the serial data for VRATE toggling. Input SRG for 32-bit serial data. (10-bit address + 22-bit data) 6. Input the serial data for HRATE toggling. Input SRG for 32-bit serial data. (10-bit address + 22-bit data) 7. Input the serial data for TG enable. Input SRG for 16-bit serial data. (10-bit address + 16-bit data) TG enable must be complete. (020h[0] = 1) Figure 17 shows the timing for the power-up sequence. Power SDATA CS SCLK MCK VD 1 1 HD 100 200 100 Vertical Output HG1A, HL = High, HG1B = Z High-Speed Output HG2A, RG = Low, HG2B = Z Figure 17. Power-Up Sequence Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 23 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com AFE (ANALOG FRONT-END) SECTION OVERVIEW Composition The VSP01M01/VSP01M02 are complete mixed-signal ICs that contain all of the key features associated with processing of the CCD imager output signal in video cameras, digital still cameras, security cameras, or similar applications. A simplified block diagram of the AFE section is shown in Figure 18. The AFE section includes these features: • Correlated double sampler (CDS) • Programmable gain amplifier (PGA) • Analog-to-digital converter (ADC) • Input clamp • Optical black (OB) level clamp loop • Timing control • Internal reference voltage generator It is recommended that an off-chip emitter follower buffer be placed between the CCD output and the device CCDIN input. The serial interface controls PGA gain, clock polarity setting, and operation mode. BYP2 COB Buffer Current DAC Decoder From Serial Interface Gain Control CCD Out Signal CDS 16-Bit ADC Digital Output 10-/12-/16-Bit DPGA CCDIN Clamp Internal Clocks (SHP/SHD, ADCCK, CLPOB, CLPDM) From TG Section Figure 18. Simplified Block Diagram of the AFE Section Function Table 16 shows the major functions of the AFE section. Table 16. AFE Functional Summary 24 FUNCTION RELATED REGISTER Selectable CDS (analog) gain 008h Programmable digital gain 006h, 007h SECTION Programmable Gain Programmable OB clamp level 004h Standby mode 001h[2:0] Standby Function Hot pixel rejection 005h Hot Pixel Rejection Selectable register update 000h[2:0] AFE Register Update Function Data output enable control 002h[2] Data Output Enable Submit Documentation Feedback OB Loop and OB Clamp Level Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 CORRELATED DOUBLE SAMPLER (CDS) The output signal of the CCD image sensor is sampled twice during one pixel period: once at the reference interval and again at the data interval. Subtracting these two samples extracts the video information of the pixel as well as removes any noise, which is common to both intervals. Thus, CDS is very important to reduce the reset noise and the low-frequency noise that are present on the CCD output signal. Figure 19 shows the block diagram of the CDS section. SHP, SHD, CLPDM, and CLPOB are supplied from the TG section; these signals are active low (close). SHP/SHD CCD Input CINP C1 CCDIN SHP CCGND C2 CCD GND CLPDM SHP REFP 1.5 V Figure 19. Block Diagram of CDS and Input Clamp INPUT CLAMP The buffered CCD output is capacitively coupled to this device. The purpose of the input clamp is to restore the dc component of the input signal, which was lost with the ac coupling, and to establish the desired dc bias point for the CDS. Figure 19 also shows the block diagram of the input clamp. The input level is clamped to the internal reference voltage, CM (1.25 V), during the dummy pixel interval. More specifically, the clamping function becomes active when both CLPDM and SHP are active. Immediately after power on, the clamp voltage of the input capacitor is not charged. For fast charge-up for clamp voltage, these devices provide a boost-up circuit. ANALOG-TO-DIGITAL CONVERTER (ADC) These devices provide a high-speed, 16-bit analog-to-digital converter (ADC). This ADC uses a fully differential pipelined architecture with a correction feature. The ADC error correction architecture is very advantageous to realize a better linearity for lower signal levels. Large linearity errors tend to occur at specific points in the fullscale range and the linearity improves for a signal level below that specific point. The ADC ensures 16-bit resolution across the entire full-scale range. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 25 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com OB LOOP AND OB CLAMP LEVEL This device has a built-in OB offset self-calibration circuit (OB loop) that compensates the OB level by using optical black (OB) pixels output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown in Figure 20. OB Clamp Level CCDIN CDS Data Out DPGA 16-Bit ADC BYP2 Current DAC COB Decoder CPLOB Figure 20. OB Loop and OB Clamp Level CCD offset is compensated by the convergence of this calibration circuit while activating CLPOB during a period when OB pixels are output from the CCD. Note that the total number of effective pixels is (the CLPOB period –6 pixels). At the CDS circuit, CCD offset is compensated as a difference between reference level and data level of the OB pixel. These compensated signal levels are recognized as actual OB levels, and the outputs are clamped to the OB levels set by the serial interface. These OB levels are the base of black for the effective pixel period thereafter. Because DPGA, which is a gain stage, is outside the OB loop, OB levels are not affected even if the gain is changed. Converging time of the OB loop is determined by the capacitor value connected to the COB terminal and output from the current output DAC of the loop. The time constant can be obtained from Equation 1: C T= (16384 ´ IMIN) Where: C is the capacitor value connected to COB, IMIN is the minimum current (0.15 μA) of the current DAC which is an equivalent current to 1 LSB of the DAC output. When C = 0.1 μF, T is 40.8 μs. (1) Slew rate (SR) can be obtained from Equation 2: SR = IMAX C Where: C is the capacitor value connected to COB, IMAX is the maximum current (76 μA) of the current DAC which is an equivalent current to 511 LSB of the DAC output. (2) 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Immediately after power-on, the COB capacitors are not charged. For fast start-up, a COB voltage boost-up circuit is provided. The OB clamp level (digital output value) can be set externally through the serial interface by inputting a digital code to the OB clamp level register. The digital codes to be input and the corresponding OB clamp levels are shown in Table 17. Table 17. Input Code and OB Clamp Level to Be Set CLAMP LEVEL (LSB) CODE (Register = 004h) VSP01M01 (10-Bit) VSP01M02 (12-Bit) 00000b 16 64 00001b 18 72 — — — 00110b 28 112 00111b 30 120 01000b (default) 32 128 01001b 34 136 — — — 11110b 76 304 11111b 78 312 PROGRAMMABLE GAIN The VSP01M01 and VSP01M02 gain ranges from –9 dB to 44 dB. The desired gain is set as a combination of CDS gain and the digital programmable gain amplifier (DPGA). CDS gain can be programmed in the range of –3 dB to 18 dB (–3 dB, 0 dB, 6 dB, 12 dB, 18 dB). –3 dB gain supports large input levels ranging from 1 V to 1.3 V. Digital gain can be programmed in the range of –6 dB to 26 dB in 0.03125-dB steps. Both gains are controlled through the serial interface. Gain changes linearly in proportion to the setting code, as shown in Figure 21. Table 18. Programmable Gain Register (1) PARAMETER (1) REGISTER ADDRESS CDS (analog) gain 008h DPGA 006h, 007h Refer to the Configuration Register section for details. 30 25 Gain (dB) 20 15 10 5 0 -5 -10 0 128 256 384 512 640 768 896 1024 Input Code for Gain Control (0 to 1023) Figure 21. DPGA Setting Code vs Gain Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 27 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com PRE-BLANKING AND DATA LATENCY These devices have a pre-blanking function. When PBLK = low, all digital outputs are set to '0' after the latching ADCCK clocks counting from PBLK go low to accommodate the clock latency of these devices. CLOCK TIMINGS FOR THE AFE SECTION The CDS and the ADC are operated by SHP and SHD; the derivative timing clocks are generated by the on-chip timing generator. The output register and decoder are operated by ADCCK. The digital output data are synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and the output data is described in the Timing Characteristics . CLPOB is used to activate the black level clamp loop during the OB pixel interval and CLPDM is used to activate the input clamping during the dummy pixel interval. In standby mode, ADCCK, SHP, SHD, CLPOB, and CLPDM are internally masked and pulled high. Refer to the Standby Function section of the Common Section and the Signal section of the TG (Timing Generator) Section for details. VOLTAGE REFERENCE All reference voltages and bias currents used on the device are created from an internal band-gap circuitry. The VSP01M01 and VSP01M02 have symmetrically independent voltage references. CDS and the ADC primarily use three reference voltages: REFP (1.5 V), REFN (1.0 V), and CM (1.25 V) of the individual reference. REFP and REFN are buffered on-chip. CM is derived as the mid-voltage of the register chain connecting REFP and REFN internally. Twice the difference voltage between REFP and REFN [that is, 2(REFP – REFN)] determines the ADC full-scale range. REFP, REFN, and CM should be heavily decoupled with appropriate capacitors. Refer to the Terminal Functions section for details. HOT PIXEL REJECTION Sometimes the OB pixel output signal from the CCD includes an unusual level signal that causes pixel defection. If this level reaches a full-scale level, is may affect OB level stability. These devices have a function that rejects this large unusual pixel level (hot pixel) at the OB pixel. Through this function, these devices improve the CCD yield at camera manufacturing. The rejection level for hot pixels can be programmed through the serial interface. When a hot pixel comes from the CCD, the VSP01M01 and VSP01M02 omit it and replace it with the previous pixel level from the OB level calculation. Table 19. Hot Pixel Rejection Register (1) (1) 28 PARAMETER REGISTER ADDRESS Hot pixel rejection 005h Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 AFE REGISTER UPDATE FUNCTION Some registers for the AFE section can be selected during update timing. Refer to the Register Update section of the Common Section for details. DATA OUTPUT ENABLE Data out is enabled or disabled by the Data Output Enable register, as shown in Table 20. When disabled, the output level is high impedance. Table 20. Data Output Enable Register PARAMETER REGISTER ADDRESS OE 002h[2] DESCRIPTION 0 = Enabled (default) 1 = Disabled (high impedance) DAC The VSP01M01 and VSP01M02 provide a two-channel, general-purpose, 8-bit DAC, as shown in Table 21. This DAC can be used for various applications such as CCD bias control, iris control, etc. Table 21. DAC Input Register (1) (1) PARAMETER REGISTER ADDRESS DAC1 00Ah, 00Bh DAC2 00Ch, 00Dh Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 29 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com TG (TIMING GENERATOR) SECTION OVERVIEW Composition The VSP01M01 and VSP01M02 support variable CCD timing. For horizontal and vertical sequencing, full programming is available. These devices include a counter, high-speed signal generator, VA selector for frame mode change, output controller, and a TRIG function section. High-speed signal rise and fall timing are generated through the high-speed signal generator. For each signal, enabling and initial polarity are controlled by the output controller. Counter Table 22 shows the operation of each counter. Table 22. Counter Operation COUNTER INCREASED BY RESET BY Reset (VA) VA instruction TRIG Reset (HA) VD EOF (VA) TRIG Frame VA (vertical) OUTPUT/OPERATION Frame count Line count Instruction: Frame count reset Initialize Event number start/stop EOF Call HA Address HA (horizontal) HS (VHIGH SPEED transfer) Event MCK MCK Trigger V HD EOL (HA) TRIG HS number start (HA) Repeat (HS) Pixel count Signal toggling V0N-12N, P0-5, CLPDM, CLPOB, PBLK, HBLK, HDIV, HD, VD Instruction: HS number start/stop EOL VSIGNAL toggling Repeat instruction Event number start (VA) VSIGNAL control The HA counter controls the horizontal sequence with the pixel counter. Some signal toggling is controlled by the pixel step. The VA counter controls the vertical sequence with the line counter. The VA calls the HA address by a line step. HS controls the VHIGH SPEED transfer sequence with a pixel counter. VSIGNAL toggling is controlled by a pixel step. This counter is started by the HA start command. The loop cycle continues until an HA stop command is issued. An event counter controls VHIGH-SPEED transfer for an electrical zoom function. This counter operates between the VA start and stop commands. TRIG Function Section TRIG has the following functionality: • Frame counter reset function • Load frame function • TG stop function These functions are activated by a register setting. 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 CCD Support The VSP01M01 and VSP01M02 TG are designed for various kinds of CCD sensor operation, including IT-CCD as well as FT-CCD, IT progressive CCD, FIT-CCD, and motion CCD, as shown in Figure 22. OB OB OB Active Area OB OB OB OB OB OB FD Active Area OB Active Area OB OB HV PIX Summing Area Horizontal CCD FD Dummy Horizontal CCD Memory Area Dummy a) IT/IT Progressive c) Motion CCD FD Horizontal CCD Dummy b) CCD FT/FIT-CCD NOTE: Shaded cells indicate the area under discussion. Figure 22. CCD Support Applications The CCD operation supports these functions: • Vertical format: – IT-CCD: two, three, or four field types – IT-progressive CCD – FT-CCD – FIT-CCD – Motion CCD • Horizontal transfer format: – Four channels, two phases • Floating diffusion reset: – One floating diffusion or single phase reset Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 31 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Timing Range The VSP01M01 and VSP01M02 have a horizontal 13-bit counter and a vertical 12-bit counter. The counter synchronizes the pixel rate master clock (MCK). The reference signal (HD/VD) has flexibility that can select either the master or slave mode. The timing is programmable so that the TG generates every signal. Apply the program through the serial interface. Refer to the Register/Memory Map section of the Common Section for details. Line Counter VD 1 3 M PIX CCD 5 M PIX CCD 4095 13-Bit (8191 Pixels) x 12-Bit (4095 Lines) Timing Area 1 Pixel Counter 8191 1 1 HD Figure 23. TG Handling Time Range Operating Mode The primary operating mode consists of a combination of normal mode, monitor mode, still mode, and motion picture mode. 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs www.ti.com VSP01M01 VSP01M02 SBES016 – MARCH 2009 Normal Mode Normal mode operates as a basic function with an electric shutter, integration, readout, vertical transfer, and horizontal transfer. IT-CCD, FT-CCD, and progressive-CCD use a horizontal sequence (see the Horizontal Sequence section), vertical sequence (see the Vertical Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD use an electric shutter function (see the Electric Shutter Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P55 SUBN Figure 24. Normal Mode Timing Example Monitor Mode Monitor mode operates vertically over several pixel intervals, with an electric shutter, integration, readout, vertical transfer, and horizontal transfer. IT-CCD, FT-CCD, and progressive-CCD use a horizontal sequence (see the Horizontal Sequence section), vertical sequence (see the Vertical Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD use an electric shutter function (see the Electric Shutter Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P55 SUBN Figure 25. Monitor Mode Timing Example Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 33 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Still Mode Still mode operates as a smear dump operation and SUBSW control. IT-CCD, FT-CCD, and progressive-CCD use a vertical sequence (see the Vertical Sequence section), horizontal sequence (see the Horizontal Sequence section), vertical high-speed transfer sequence (see the Vertical HighSpeed Transfer (HS) Sequence section), and an HBLK function (see the HBLK Function section). IT-CCD, progressive-CCD, and most of the FT-CCD uses an electric shutter function (see the Electric Shutter Function section). IT-CCD and progressive-CCD use a SUBSW function (see the SUBSW Function section) for CCD substrate bias control. VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN SUBSW Figure 26. Still Mode Timing Example Motion Picture Mode Motion picture mode adds up the pixels in the CCD horizontal and vertical transfer. IT-CCD is dedicated to this mode and uses a vertical sequence (see the Vertical Sequence section), horizontal sequence (see the Horizontal Sequence section), an HBLK function (see the HBLK Function section), and HDIV function (see the HDIV Function section). VD HD HG1A, HG1B HG2A, HG2B V0N-V12N P0-P5 SUBN Figure 27. Motion Picture Mode Timing Example 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs www.ti.com VSP01M01 VSP01M02 SBES016 – MARCH 2009 Function Table 23 summarizes the primary TG section functionality. Table 23. TG Function FUNCTION RELATED REGISTER SECTION Adjustable high-speed pulse 002h, 003h, 010h-01Ah High-Speed Pulse Adjustment Programmable horizontal pattern 200h-3FFh Horizontal Sequence Vertical Sequence Programmable vertical pattern 180h-1FFh Programmable VCCD high-speed transfer pattern 100h-17Fh Electrical zoom function 030h-033h, 037h-03Eh Sync signal selectable (master or slave) 020h Field index for two-field CCD 022h, 02Fh, 035h[0] Programmable electrical shutter 08Ch-0A3h Vertical High-Speed (HS) Transfer Sequence Synchronous Function Electric Shutter Function Programmable strobe 04Ch-07Bh Strobe Function Programmable MECH shutter 040h-04Bh MSHUT Function Programmable SUBSW 07Ch-08Bh SUBSW Function Programmable frame sequence for strobe, MECH shutter, and SUBSW 021h[4], 022h[2] Frame Count Function Frame mode control by trigger 021h[3:2], 036h[5:3] Waiting mode by trigger 020h[4], 021h[1:0] Frame sequence (for strobe, MECH shutter, and SUBSW) control by trigger 021h[4:3], 022h[2] Standby mode 020h[0] Standby Function Programmable HG signal for horizontal blank — HBLK Function Flexible pixel summing operation 01Bh[2:0] HDIV Function Monitor out for internal signal 001h[3], 0B5h Selectable HG power 01Ch[1:0] Flexible register update 000h[3] Trigger Function Signal TG Register Update Function Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 35 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com SIGNAL This device has 32 vertical signals and nine horizontal signals. The universal-purpose signal has flexible usage. Refer to the Terminal Functions table for details. Pin enabling of vertical signals is set by register address 023h-028h. Pin initial polarity is set by register address 029h-02Eh. The initial polarity is applied by the VA initialize instruction. (The initial polarity is not applied by the TG operation start). Refer to the Configuration Register section for details. V13 Signals Universal Purpose (19 Signals) External Use (19 Signals) Read Out (6 Signals) Vertical (32 Signals) Sync I/O (2 Signals) Specific Purpose (13 Signals) External Use (6 Signals) Internal Use (5 Signals) Horizontal (9 Signals) Specific Purpose (9 Signals) External Use (6 Signals) Internal Use (3 Signals) Test (Monitor) (2 Signals) Universal Test Purpose (2 Signals) V0N V1N V2N V3N V4N V5N V6N V7N V8N V9N V10N V11N V12N P0 P1 P2 P3 P4 P5 HD VD SUBN FIELD STROBE MSHUT SUBSW1 SUBSW2 HDIV CLPDM CLPOB PBLK HBLK HG1A HG1B HL HG2A HG2B RG SHP SHD ADCCK TPP TPD External Use (2 Signals) Figure 28. Signal Overview 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Programmed Signal (Memory Assignment) The signal timing (described in Table 24) is specified by the HA (horizontal address) program. Terminal assignment numbers are used by the HA command (data[17:13]). The default output level is fixed except for an MCK stop condition. These signals are disabled with a power-up default. The CLPDM, CLPOB, PBLK, HBLK, and HDIV signal active polarity is low. Table 24. Memory Assignment Signal REGISTER ADDRESS TERMINAL NAME SIGNAL FUNCTION TERMINAL ASSIGNMENT V[0:12]N Vertical transfer signal (highspeed transfer) P[0:5] ENABLE INITIAL 00001b-01101b (113) 023h-025h 029h-02Bh Vertical transfer signal (general signal) 10000b-10101b (16-21) 025h-026h 02Bh-02Ch CLPDM Clump dummy signal 11000b (24) 026h[5] 02Ch[5] CLPOB Clump OB signal 11001b (25) [0] [0] PBLK Pre-blanking signal (digital out = low) 11010b (26) [1] [1] HBLK Horizontal transfer pulse blank 11011b (27) HDIV Horizontal transfer pulse divide 11100b (28) VD Vertical sync signal (master mode) 11101b (29) [4] [4] HD Horizontal sync signal (master mode) 11110b (30) [5] [5] LEVEL POWERUP DEFAULT AFE STANDBY TG STANDBY High [2] 027h [3] [2] 02Dh TRIG STOP MCK High No effect No effect Low Low [3] Decoded Signal (Register Assignment) The signal timing of Table 25 is specified by the decoder. The decoder refers to the register value of the frame number, line number, or pixel number. Default output levels are fixed except for an MCK stop condition. These signals are disabled with a power-up default. Table 25. Register Assignment Signal REGISTER ADDRESS TERMINAL NAME SIGNAL FUNCTION ENABLE INITIAL SUBN Electric shutter [0] [0] FIELD Field index [1] [1] STROBE Strobe signal MSHUT Mechanical shutter SUBSW1 CCD substrate bias control 1 [4] [4] SUBSW2 CCD substrate bias control 2 [5] [5] 028h [2] [3] 02Eh LEVEL POWER-UP DEFAULT High [2] [3] AFE STANDBY Low TG STANDBY TRIG STOP MCK High No effect Low No effect Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 37 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Phase Controlled Signal (Register Assignment) The high-speed signal timing is specified by a register. Default output levels are shown in Table 26. Table 26. Horizontal Signal REGISTER ADDRESS LEVEL ENABLE TERMINAL NAME SIGNAL FUNCTION HG1A, HL HG1B HG2A HG2B Horizontal transfer signal 1 01Bh[3] Horizontal transfer signal 2 RG CCD reset signal SHP Reference level sampling SHD Data level sampling ADCCK ADCCK buffer POWER-UP DEFAULT DISABLE 01Bh[2] AFE STANDBY TG STANDBY TRIG STOP MCK — High 01Ch[2] Z 01Bh[4] 0 = Low 1 = High High High High — Low 01Ch[2] Z Low Low Low Low Toggling Toggling ENABLE Low Always enable Toggling No effect High Low HG Drive The HG drive power for HG1A, HG1B, HG2A, and HG2B is selected by the HG power select register (01Ch[1:0]), as shown in Table 27. Table 27. HG Power Select Register TERMINAL NAME REGISTER 01Ch[1:0] HG1A 00 = Minimum HG1B 01 = Default HG2A 10 = Mid-range HG2B 11 = Maximum The HG drive power can be doubled by a connection between HGAx and HGBx. However, this setting is typically used for power dissipation. If HGBx is not used, disable and do not connect HGBx. HG1A HG1B HG2A HG2B Figure 29. HG Double Power Connection 38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Monitor Signal The test pin (TPP, TPD) is set up by address 001h, data bit [3] = 1, as shown in Table 28. Table 29 describes TPP and TPD. Table 28. Monitor Pin Enable Register (1) (1) PARAMETER REGISTER ADDRESS VALUE Monitor pin 001h[3] 1 = Enable Refer to the Configuration Register section for details. Table 29. Test Pin Output Select REGISTER 0B5h[3:0] TPP TPD 1000b (8) SHP SHD 1001b (9) CLPOB CLPDM 1010b (10) PBLK HDIV 1011b (11) HBLK — SHP and SHD are monitored at the TG section output, as shown in Figure 30. The actual sampling point is delayed from the monitor point. The delay time is shown in Figure 30. The actual sampling point delay = delay controller value (003h[1:0] = 0 ns-6 ns) + sampling delay (3 ns). TG Section AFE Section 3-ns Delay SHP High-Speed Signal Generator Delay Controller SHD 015h-018h Sampling Circuit 003h[1:0] TPP Signal Selector TPD Figure 30. SHP/SHD Monitor Out HIGH-SPEED PULSE ADJUSTMENT The high-speed pulse can be adjusted in steps of one pixel clock cycle per 100. The assignment register for each pulse is shown in Table 30. The rising edge of the RG pulse as a reference. Table 30. High-Speed Pulse Adjustment Register REGISTER ADDRESS CONTROL ITEM TERMINAL NAME FALLING RISING RG RG 014h[4:0] — G1h G1Ah G1Bh HL 011h[4:0] 010h[4:0] G2h G2Ah G2Bh 012h[4:0] 013h[4:0] DELAY — SHP SHP 015h[4:0] 016h[4:0] SHD SHD 017h[4:0] 018h[4:0] 003h[1:0] ADCCK ADCCK — — 019h[5:0] 019h[6] Data out B0-B15 — — 002h[1:0] Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 39 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com RG Control RG control is described in Figure 31 and Table 31. tCKP tCKP/4 RG tRGW tRGW Figure 31. RG Fall Timing Table 31. RG Fall Register ADDRESS NAME DESCRIPTION RG falling edge from RG rising edge (tCKP/4 – 16tCKP/100 < tRGW < tCKP/4 + 15tCKP/100) 00 0001 0100b (014h) RG FALL[4:0] DATA (DEC) STEP 10000b 10001b — 11111b 00000b 00001b — 01110b 01111b (16) (17) — (31) (0) (1) — (14) (15) –16 –15 — –1 0 (default) 1 — 14 15 STEP is twos complement of data. 1 step = (1 pixel clock term)/100 HG1 Control HG1 control is described in Figure 32 and Table 32. tCKP RG tH1R tH1R HG1A, HG1B, HL Rising tCKP/2 HG1A, HG1B, HL Falling tCKP/2 tH1F Figure 32. HG1 Timing Table 32. HG1 Register 40 ADDRESS NAME DESCRIPTION 00 0001 0000b (010h) HG1 RISE[4:0] HG1A, HG1B, and HL rising edge from RG rising edge (–tCKP16/100 < tH1R < tCKP15/100) Same step control as for Table 31. Default = 00000b. 00 0001 0001b (011h) HG1 FALL[4:0] HG1A, HG1B, and HL falling edge from RG rising edge (tCKP/2 – 16tCKP/100 < tH1F < tCKP/2 + 15tCKP/100) Same step control as for Table 31. Default = 00000b. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 HG2 Control HG2 control is described in Figure 33 and Table 33. tCKP RG tCKP/2 tCKP/2 tH2R HG1A, HG1B, HL Rising tH2F tH2F HG1A, HG1B, HL Falling Figure 33. HG2 Timing Table 33. HG2 Register ADDRESS NAME DESCRIPTION 00 0001 0011b (013h) HG2 RISE[4:0] HG2A and HG2B rising edge from RG rising edge (tCKP/2 – 16tCKP/100 < tH2R < tCKP/2 + 15tCKP/100) Same step control as for Table 31. Default = 00000b. 00 0001 0010b (012h) HG2 FALL[4:0] HG2A and HG2B falling edge from RG rising edge (–tCKP16/100 < tH2F < tCKP15/100) Same step control as for Table 31. Default = 00000b. SHP Control SHP control is described in Figure 34 and Table 34. tCKP tCKP/4 tCKP/2 RG tPR SHP Rising tPF tPR = tPR1 + tSDLY tPF SHP Falling tPF = tPF1 + tSDLY Figure 34. SHP Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 41 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Table 34. SHP Register ADDRESS NAME 00 0001 0110b (016h) 00 0001 0101b (015h) 00 0000 0011b (003h) DESCRIPTION SHP RISE[4:0] SHP rising edge from RG rising edge (tCKP/2 – 16tCKP/100 < tPR1 < tCKP/2 + 15tCKP/100) Same step control as for Table 31. Default = 00000b. SHP FALL[4:0] SHP falling edge from RG rising edge (tCKP/4 – 16tCKP/100 < tPF1 < tCKP/4 + 15tCKP/100) Same step control as for Table 31. Default = 00000b. S-DELAY[1:0] Sampling delay for SHP/SHD (0 ns < tSDLY < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns SHD Control SHD control is described in Figure 35 and Table 35. tCKP +3tCKP/4 - 8tCKP/100 -8tCKP/100 RG tDR tDR SHD Rising tDR = tDR1 + tSDLY SHD Falling tDF tDF = tDF1 + tSDLY Figure 35. SHD Timing Table 35. SHD Register ADDRESS DESCRIPTION 00 0001 1000b (018h) SHD RISE[4:0] SHD rising edge from RG rising edge (–24tCKP/100 < tDR1 < 7tCKP/100) Same step control as for Table 31. Default = 00000b. 00 0001 0111b (017h) SHD FALL[4:0] SHD falling edge from RG rising edge (3tCKP/4 – 24tCKP/100 < tDF1 < 3tCKP/4 + 7tCKP/100) Same step control as for Table 31. Default = 00000b. S-DELAY[1:0] Sampling delay for SHP/SHD (0 ns < tSDLY < 6 ns) (0 ns < tSDLY < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns 00 0000 0011b (003h) 42 NAME Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 ADCCK Control ADCCK control is described in Figure 36 and Table 36. tCKP tCKP/2 tCKP/2 tADCKR tADCKR RG ADCCK Figure 36. ADCCK Delay Timing Table 36. ADCCK Delay Register ADDRESS NAME DESCRIPTION 00 0001 1001b (019h) ADCCK DELAY[5:0] ADCCK rising edge from RG rising edge (–50tMCKP/100 < tADCKR < 49tMCKP/100) Default = 00 0000b. Data[6:0] = 01Ah[0] × 26 + 019h[5:0] 00 0001 1010b (01Ah) ADCCK DELAY[6] DATA[6] 01Ah[0] 019h[5:0] (DEC) STEP 100 0000b 1 00 0000b (64) Reserved 100 1101b 1 00 1101b (77) Reserved 100 1110b 1 00 1110b (78) –50 100 1111b 1 00 1111b (79) –49 — — — — — 111 1111b 1 11 1111b (127) –1 000 0000b 0 00 0000b (0) 0 (default) 000 0001b 0 00 0001b (1) 1 — — — — — 011 0000b 0 11 0000b (48) 48 011 0001b 0 11 0001b (49) 49 011 0010b 0 11 0010b (50) Reserved 011 1111b 0 11 1111b (63) Reserved STEP is twos complement of data. 1 step = (1 pixel clock term)/100. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 43 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Data Out Delay Control Data out delay control is described in Figure 37 and Table 37. tCKP ADCCK tHOLD (tDOD = 6 ns) tOD (tDOD = 6 ns) tHOLD (tDOD = 0 ns) tOD (tDOD = 0 ns) tDOD tDOD B[15:0] Figure 37. Data Out Delay Timing Table 37. Data Out Delay Register ADDRESS 00 0000 0010b (002h) NAME DATA OUT DELAY[1:0] DESCRIPTION Data out delay 00b to 11b (0 ns < tDOD < 6 ns) 00b = 0 ns (default) 01b = 2 ns 10b = 4 ns 11b = 6 ns TG INSTRUCTION HIERARCHY Figure 38 shows the instruction hierarchy. The VA number corresponds to the frame template, and the HA number corresponds to the line template. Each VA has a set of HA number instructions in the vertical timing memory; each HA number has a set of toggling instructions in the horizontal memory. The frame mode is selected by a register (036h). 44 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Frame Data Set Data Fixed Address HA Address Call 0 HA Address = 0 Vertical Data Set VA1-1: HA1 Start at Line 1 (Blanking) VA1-2: HA2 Start at Line 37 (Readout1) VA1-3: HA3 Start at Line 38 (Readout2) 180h Frame Mode (VA1) 190h Frame Mode (VA2) VA1-16: HA4 Start at Line 39 (OB) 1B0h HA1-2: CPOB at Pixel 40 2 HA1-3: PBLK¯ at Pixel 51 3 HA1-4: V3N at Pixel 52 9 HA1-10: EOL at Pixel 1023 10 HA2-1: CPOB¯ at Pixel 10 11 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 13 HA2-4: V1N at Pixel 100 16 HA2-7: EOL at Pixel 1023 Call HA Address = 10 Frame Mode (VA4) 128 Words 1 ¼ Frame Mode (VA3) HA1-1: CPOB¯ at Pixel 10 ¼ 16 Words 1A0h Horizontal Data Set 1C0h Frame Mode (VA5) 1D0h Frame Mode (VA6) ¼ 1E0h Frame Mode (VA7) 1F0h Frame Mode (VA8) NOTE: Line number, pixel number, and start of HA address are programmable. Figure 38. Instruction Hierarchy (Standard Sequence Sample) CCD TIMING COMPOSITION TG timing is composed of a vertical data set (VA) that contains eight frames. VA has a horizontal data set (HA), which has several numbers of lines for specific functions. Frame mode is provided by VA. Table 38 shows the frame number for each VA number. Table 38. Frame Number PARAMETER FRAME VA number 1 2 3 4 5 6 7 8 Frame number 0 1 2 3 4 5 6 7 Operated VA is updated to the Frame Now register by VD. Operated VA is updated to Frame TRIG by the TRIG signal with a Load TRIG frame function. This updating process is shown in Table 39. Table 39. Frame Mode Register PARAMETER REGISTER ADDRESS DESCRIPTION Frame now 036h[2:0] Set current frame number Default = 000b. Frame TRIG 036h[5:3] Set frame number when trigger input Default = 000b. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 45 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Figure 39 shows the TG mode transition. Power Off · Power ON · Serial Code Input TG Disable TG Standby VD TG Enable Frame Now VA (n) Frame TRIG TRIG VD VA (m) Figure 39. TG Mode Transition Figure 40 shows the CCD timing composition example, which consists of frames for several operation modes. Each frame counts the line count. VD (master/slave) or TRIG (external trigger) signal the reset line counter and change during the next frame. Table 40. TRIG Frame Function Register Setting (1) (1) (2) 46 (2) PARAMETER REGISTER ADDRESS VALUE VD frame 022h[0] 1 = Enabled TRIG frame INCR 021h[2] 1 = Enabled TRIG counter RST 021h[3] 1 = Enabled Static frame number 036h[2:0] — TRIG frame number 036h[5:3] 7 If the TRIG function is not used, TRIG Frame INCR and TRIG Counter RST should be disabled. Refer to the TRIG Function Section of this document Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Frame Number By Frame Now Register (036h[2:0]) Frame Number By Frame TRG Register (036h[5:3]) Operated VA Number VD (Master/Slave) TRIG (External) Line Counter HD 1H 1 Standard Function Monitor Mode V-Blanking HA #1 Readout HA #2 OB HA #3 Active Signal HA #4 0 (VA #1) VA #1 HA #3 HA #5 Readout HA #6 VHIGH-SPEED Transfer HA #12 Active Signal HA #7 1 VHIGH-SPEED Transfer HA #5 1 Readout HA #8 OB HA #9 Active Signal HA #10 1 OB VHIGH-SPEED Transfer E-Zoom Function Monitor Mode VA #3 7 (VA #8) 2 (VA #3) VA #3 Standard Function Still Mode VA #8 3 (VA #4) 1 OB HA #9 VBLANKING HA #11 VA #4 Figure 40. CCD Timing Composition (Example) SYNCHRONOUS FUNCTION The system follows either the HD/VD master or slave mode. Select the master/slave mode through register setting (020h[1]: 0 = Slave, 1 = Master), as shown in Table 41. The default setting is slave mode. TG also follows an external HD/VD signal. The master mode generates HD/VD timing according to HA instruction. Table 41. Sync Mode MODE REGISTER 020h[1] HD AND VD PIN Slave 0 (default) Input Master 1 Output HD AND VD TIMING HCYCLE VCYCLE Synchronous HA command EOL of HA EOF of VA Slave Mode The system synchronizes the external master clock, HD, and VD. Note that the HD and VD pins are input modes. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 47 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com VD, HD Detection VD- and HD-detected edge polarity are selected by register 020h[3]. The selected edge is detected as a rising edge of MCK. VD is detected by the HD phase. If the pixel count between the VD edge and HD edge is within the selected range, VD is detected. The range is selected as shown in Table 42. Table 42. VD HD Detect Register (1) PARAMETER (1) REGISTER ADDRESS DESCRIPTION VD HD TRG edge 020h[3] 0 = Falling edge (default) 1 = Rising edge ODD HD-VD 02Fh[2:0] VD after HD detect range 0-7 pixel delay Default = 001b ODD VD-HD 02Fh[5:3] HD after VD detect range 0-8 pixel delay Default = 001b Refer to the Slave Mode: VD, HD Specifications section for details. HCOUNTER Reset HCOUNTER reset is selected by MCK edge polarity (020h[2]). Table 43 shows the register. Table 43. MCK Edge Polarity (1) PARAMETER VH, HD, and MCK edge (1) REGISTER ADDRESS 020h[2] DESCRIPTION 0 = MCK rising edge (default) 1 = MCK falling edge Refer to the Slave Mode: VD, HD Specifications section for details. Field Index Field for two-field operation is detected. The detection method is selected to the VD and HD phase or Register. The Field output signal is selected by a register, as shown in Table 44. ODD detect range is selected by register 02Fh[5:0]. More than seven enabled instructions will always odd detect. Refer to the Configuration Register and Slave Mode: VD, HD Specifications section for details. Table 44. ODD/EVEN Detect Register PARAMETER REGISTER ADDRESS DESCRIPTION Detect method 022h[3] 0 = VD/HD phase (default) 1 = Register (035h[0]) Register select 035h[0] 0 = ODD (default) 1 = EVEN Field POL 022h[4] 0 = Low at ODD, high at EVEN (default) 1 = High at ODD, low at EVEN VD even 022h[5] 0 = Disabled (default) 1 = Enabled Master Mode The system synchronizes the external master clock, internal HD, and internal VD. Note that the HD and VD pins are output modes. HD and VD timing are provided by the HA command. HCYCLE is provided by an end-of-line instruction of the HA command. VCYCLE is provided by the end-of-frame instruction of the VA command. 48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 HORIZONTAL SEQUENCE The horizontal sequence contains toggling information for 1H. Each word describes toggling information. The user must input 2-bit delay information, 2-bit toggling information, 5-bit terminal assignment, and 13-bit pixel count. TG decodes the pixel count and precedes each event sequentially according to the address. A maximum of four signals toggling at the same pixel counter are allowed using the 2-bit delay instruction. Horizontal Address (HA) Memory The HA memory area is shown in Table 45. Table 45. HA Memory Area PARAMETER DESCRIPTION Address 200h-3FFh Memory area 512 words Data width 22-bit Basic Functionality Table 46 defines the terminal assignment (5-bit) command and pixel address for toggling. Table 46. HA Bit Function 21 20 19 Delay 18 17 16 Toggle 15 14 13 12 11 10 9 8 7 Terminal 6 5 4 3 2 1 0 Pixel count BITS NAME 21-20 DELAY DESCRIPTION 19-18 TOGGLE 17-13 TERMINAL Terminal assignment using five bit. Terminal: V0N-12N, P0-5, CLPDM, CLPOB, PBLK, HBLK, HDIV, HD (master mode), and VD (master mode) Refer to the Signal section for details. 12-0 PIXEL CNT Toggling of the pixel count using 13 bits (10-8191). Bits below 9 are prohibited. Order in one HA part must be added order. Same pixel count is prohibited. Toggling delay pixel number using two bits (0-3) Toggling set to high/low using two bits 00b = Low, 01b = High General Instruction Table 47 details the VCCD high-speed start and end-of-line commands. Table 47. HA Instruction Bit Function 21 20 19 18 17 1 General instruction GENERAL INSTRUCTION 16 15 14 13 1 1 1 1 12 11 10 General instruction fix 9 8 7 6 5 4 3 2 1 0 Pixel count (same as for Table 46) NAME DESCRIPTION The end-of-line reset pixel counter is at the pixel number. Mode Pixel Number Master Target HCYCLE – 1 + register 034h[3:0] Slave 8191 1111b EOL 0001b Start HS 1 Start VCCD high-speed transfer (HS 1) 0010b Start HS 2 Start VCCD high-speed transfer (HS 2) 0011b Start HS 3 Start VCCD high-speed transfer (HS 3) 0100b Start HS 4 Start VCCD high-speed transfer (HS 4) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 49 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com GENERAL INSTRUCTION NAME 0101b Stop HS DESCRIPTION Stop VCCD high-speed transfer VHIGH-SPEED Transfer (HS) Instruction Two sets of commands specify the HS start/stop information and the HS toggling pixel address information. As shown in Table 48, HS start/stop information is part of the horizontal memory. Four types of HS are available using the [21:18] bit instruction. An HA programming example is shown in Table 48. Note that sync mode is a slave mode. Table 48. Horizontal Memory Example MEMORY ADDRESS FIXED [31] SEQUENTIAL [30:22] DELAY [21:20] TOGGLING [19:18] TERMINAL ASSIGNMENT [17:13] PIXEL COUNT [12:0] 1 0 0000 0000b (A1h-1h) 00b 00b 11001b (CLPOB) 0 0000 0000 1010b (10) 1 0 0000 0001b (A1h-2h) 00b 01b 11001b (CLPOB) 0 0000 0010 1000b (40) 1 0 0000 0010b (A1h-3h) 00b 00b 11011b (HBLK) 0 0000 0011 0011b (51) 1 0 0000 0011b (A1h-4h) 01b 01b 00001b (V0N flexible) 0 0000 0011 1111b (63) 1 0 0000 0100b (A1h-5h) 00b 01b 00010b (V1N flexible) 0 0000 0100 0000b (64) 1 0 0000 0101b (A1h-6h) 00b 00b 00001b (V0N flexible) 0 0000 0110 0100b (100) 1 0 0000 0110b (A1h-7h) 00b 00b 00010b (V1N flexible) 0 0000 1001 0110b (150) 1 0 0000 0111b (A1h-8h) 00b 01b 11011b (HBLK) 0 0000 1111 0001b (241) 1 0 0000 1000b (A1h-9h) 00b 00b 11000b (CLPDM) 0 0000 1111 1010b (250) 1 0 0000 1001b (A1h-10h) 00b 01b 11000b (CLPDM) 0 0001 0001 1000b (280) 1 0 0000 1010b (A1h-11h) 11111b (general instruction) 1 1111 1111 1111b (8191) 1111b (EOL) Figure 41 shows the horizontal timing. Sequentially input 22-bit data for each toggling position. HA1-10 HA1-8 HA1-9 HA1-7 HA1-6 HA1-5 HA1-4 HA1-3 HA1-2 HA1-1 CCD Format Dummy Active OB 2000 1 Active HD HG1 51 241 HBLK 10 40 CLPOB 250 CLPDM 64 280 100 V0N 64 150 V1N Figure 41. Horizontal Timing Example 50 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 VERTICAL SEQUENCE The vertical sequence consists of elements of the Horizontal Sequence . Each word contains a horizontal memory address and a line number, which is applied for the operation. The user must input 1-bit loading information, 9-bit HA address, and 12-bit line number. The TG decodes the line count and precedes each event sequentially according to the address. Vertical Address (VA) Memory The VA is detailed in Table 49 and Table 50. Table 49. VA Memory Area PARAMETER DESCRIPTION Address 180h-1FFh Memory area 128 words Data width 22-bit Table 50. VA Number Start Address VA NUMBER 1 2 3 4 5 6 7 8 Start address 180h 190h 1A0h 1B0h 1C0h 1D0h 1E0h 1F0h Basic Functionality Table 51 defines the HA (horizontal address) command and HA pattern apply line number command. Table 51. VA Bit Function 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 (1) (1) HA ADD LINE VLOAD. BITS NAME 21 VLOAD 20-12 HA ADD 11-0 LINE DESCRIPTION Vertical timing load, fixed at '0' HA address load using 9-bit, HA address = (HA physical memory address) – 512 Line count using 12-bit (1-4095). Order in one VA must be added order. Same line count is prohibited. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 51 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com MISC Instruction Table 52 shows the vertical command apply line number command. Table 52. VA Instruction Bit Function 21 20 19 18 0 (1) (1) 17 16 15 14 13 12 X X X X X Instruction 11 10 9 8 7 Don't care 6 5 4 3 2 1 0 LINE VLOAD. BITS NAME 21 VLOAD Vertical timing load, fixed at '0' 11-0 LINE Line count using 12-bit (1-4095). Order in one VA must be added order. Same line count is not prohibited. INSTRUCTION DESCRIPTION NAME DESCRIPTION End of frame, reset line counter. In master mode, renew frame mode. 1111b 52 EOF MODE LINE NUMBER Master Slave Target VCYCLE + 1 4095 Initialize pin output at line 1. (V0N-12N, P0-5, SUBN, CLPDM, CLPOB, PBLK, HBLK, HDIV, FIELD, STROBE, MSHUT, SUBSW1, and SUBSW2) 0001b Initialize 0010b Reserved Reserved 0011b RUPDATE Register update. Renew TG register (H037-H0A3) at line number. 0100b Start event 1 Start VCCD high-speed transfer (dynamic mode) 1 at line number. 0101b Start event 2 Start VCCD high-speed transfer (dynamic mode) 2 at line number. 0110b End event 0111b Frame counter reset Stop VCCD high-speed transfer (dynamic mode) at line number. Frame counter reset. Reset and start frame counter at line 1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 VA programming is shown in Table 53. Sync mode is a slave mode. Table 53. Vertical Memory Example MEMORY ADDRESS SEQUENTIAL [29:22] LOAD [21] HA ADDRESS (0-511) OR INSTRUCTION [20:12] LINE COUNT [11:0] 01b 1000 0000b (VA10) 0 0 0000 0000b (A1h) 0000 0000 0001b (01) 01b 1000 0001b (VA11) 1 0 0010 0000b (initialize) 0000 0000 0001b (01) 01b 1000 0010b (VA12) 1 0 1110 0000b (frame count reset) 0000 0000 0001b (01) 01b 1000 0011b (VA13) 0 0 0001 0000b (A2h) 0000 0010 0001b (33) 01b 1000 0100b (VA14) 0 0 0001 1101b (A3h) 0000 0010 0010b (34) 01b 1000 0101b (VA15) 0 0 0011 0011b (A4h) 0000 0010 0011b (35) 01b 1000 0110b (VA16) 0 0 0000 0001b (A1h) 0000 0010 0100b (36) 01b 1000 0110b (VA17) 1 1 1110 0000b (end of frame) 1111 1111 1111b (4095) FIXED [31:30] HA1 HA1 HA1 HA1 HA1 HA1 HA1 38 39 40 41 42 43 44 45 37 HA1 36 HA1 35 32 VA1-6 HA1 31 VA1-4 HA3 HA1 30 VA1-5 HA4 HA1 29 33 HA1 28 34 HA1 27 VA1-3 HA2 HA1 HA1 HA1 4 3 HA1 HA1 HA1 1 2 VA1-0 HA1 HA1 1259 HA1 1257 HA1 1258 HA1 1256 HA1 1254 HA1 1255 HA1 1253 HD VD V0N P0 Figure 42. Vertical Timing Example VERTICAL HIGH-SPEED (HS) TRANSFER SEQUENCE The vertical high-speed (HS) transfer shifts a charge for a specified number of lines. The still mode and electric zoom use HS. Counter start of HS has three pixel delays from the Start HS command of HA. The vertical highspeed transfer has both a programmed operation mode and register dynamic mode. HS Memory HS memory is described in Table 54 and Table 55. Table 54. HS Memory Area PARAMETER DESCRIPTION Address 100h-17Fh Memory area 128 words Data width 16-bit Table 55. HS Number Start Address HS NUMBER 1 2 3 4 Start address 100h 120h 140h 160h Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 53 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Basic Functionality Table 56 describes the HS basic functionality. Table 56. HS Bit Function 15 14 Delay 13 12 Toggle 11 10 9 8 7 6 5 Terminal 4 3 2 1 0 1 0 Pixel count BITS NAME 15-14 DELAY DESCRIPTION 13 TOGGLE HS delay using two bits (0-3) HS is set to high/low 0 = Low, 1 = High HS pin using four bits (1-13) 12-9 TERMINAL 8-0 PIXEL CNT TERMINAL NUMBER V 1 V0N 13 V12N HS toggling pixel using nine bits (1-511) Instruction Table 57 details the HS instruction. Table 57. HS Instruction Bit Function 15 14 13 12 11 10 9 8 7 6 5 General instruction 54 4 3 2 Pixel count GENERAL INSTRUCTION NAME DESCRIPTION 111 0000b Repeat Reset HS pixel counter, pixel number = target cycle – 1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Programmed Operation Mode The VHIGH-SPEED transfer function is used to clear the VCCD. The HS pattern is supplied in the HS memory area. The pattern can be provided four types. HS start and stop timing is provided in the HA memory area. The operation continues until a decoding stop command of HA. VTOGGLING must not be provided under an HS operation. 1. Provide toggling information in HS memory. 2. Provide HS start and stop instruction in the HA memory with no VTOGGLING of HA. 3. Provide the above HA to the VA memory. VCCD Clear Example Figure 43 shows an example of a programmable operation mode. 0 HA1-1: CPOB¯ at Pixel 10 1 HA1-2: CPOB at Pixel 40 1: V2N¯ at Pixel 1 2 HA1-3: PBLK¯ at Pixel 51 2: V0N at Pixel 21 3 HA1-4: V2N at Pixel 52 (2) (1) VA1-2: HA2 Start at Line 2 (VHIGH-SPEED #1 Blank) ¼ VA1-3: HA3 Start at Line 80 (VHIGH-SPEED #1 End) ¼ VHIGH-SPEED Transfer #1 13: Repeat at Pixel 179 HA1: VHIGH-SPEED #1 Start at Pixel 561 Repeat ¼ VA1-16: HA4 Start at Line150 9 HA1-10: EOL at Pixel 1023 Call HA Address = 10 VHIGH-SPEED Transfer #1 HA2-1: CPOB¯ at Pixel 10 11 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 ¼ 10 16 HA2-7: EOL at Pixel 1023 17 HA3-1: CPOB¯ at Pixel 10 18 HA3-2: CPOB at Pixel 40 19 HA3-3: PBLK¯ at Pixel 51 20 HA3-4: VHIGH-SPEED End at Pixel 2432 26 HA3-10: EOL at Pixel 1023 Do Not Provide VTOGGLING Call HA Address = 17 ¼ 16 Words Transfer #1 ¼ HA Address = 0 VA1-1: HA1 Start at Line 1 (VHIGH-SPEED #1 Start) VHIGH-SPEED Transfer Data Set (HS) Horizontal Data Set (HA) Call Vertical Data Set (VA) Start VHIGH-SPEED HA Address Note (2) VHIGH-SPEED Transfer #1 End VHIGH-SPEED (3) ¼ Transfer NOTE: Shaded cells indicate the area under discussion. (1) The HA command block is called by a VA command. (2) The HS loop sequence is started by an HA command at the selected pixel. (3) The HS loop sequence is stopped by an HA command at the selected pixel. (4) Line number, pixel number, and start of HA address are programmable. Figure 43. Programmed Operation Mode Sequence Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 55 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com As shown in Table 58, VHIGH-SPEED toggling pixel address information is part of the HS memory. Input toggling points for one vertical transfer and one cycle address for repeat. Table 58. V High-Speed Toggling Memory Example MEMORY ADDRESS FIXED SEQUENTIAL DELAY [15:14] SET [13] TERMINAL ASSIGNMENT [12:9] 01b 0000 0000b (HS 1-1) 00b 0 0011b 0 0000 0001b (1) 01b 0000 0001b (HS 1-2) 00b 1 0001b 0 0001 0101b (21) 01b 0000 0010b (HS 1-3) 01b 0 0100b 0 0010 1001b (41) 01b 0000 0011b (HS 1-4) 00b 1 0010b 0 0011 1101b (61) — — — — — — 01b 0000 0100b (HS 1-5) 11b 1 0000b (repeat) 0 1011 0011 (179) PIXEL COUNT [8:0] Vertical High-Speed Transfer, One Cycle 21 81 V0N 61 141 V1N 1 180 101 V2N 41 121 V3N (0) (1) Figure 44. HS One Cycle Example The HS start and stop command of HA is delayed by three pixel terms. Table 59 shows the delay. Table 59. HA and HS Pixel Count ITEM LINE NUMBER HA PIXEL COUNT HS PIXEL COUNT HA1 VHIGH-SPEED transfer start. 1 561 — VHIGH-SPEED transfer counter start and V2 pulled low. 1 564 1 — — — — HA3 VHIGH-SPEED transfer stop. 80 2432 177 VHIGH-SPEED transfer cycle end. 80 2435 180 High-Speed Transfer End Point High-Speed Transfer Start Point (1 H) HD 64 (80 H) 100 584 644 2336 V0N 88 624 124 684 2376 V1N 52 564 112 664 2356 V2N 176 136 604 704 2396 Vn (0) (1) (2) (639) (640) Figure 45. HS Timing Chart Example 56 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Figure 46 shows the programmed operation mode for a still picture. Line (HA Number) Pix Number VHIGH-SPEED VHIGH-SPEED Counter V0N V1N V2N Vn HD CCD Operation Mode Start HA 1 1 1 HA #1 VHIGH-SPEED Transfer #1 HA #2 HA 3 Stop HA #3 Readout HA #6 HA 5 HA #5 Active Signal HA #11 NOTE: Shaded cells indicate the area under discussion. Figure 46. Programmed Operation Mode for A Still Picture Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 57 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com Example for Electrical Zoom Figure 47 shows the programmed operation mode for an electric zoom function. Line (HA Naumber) Pix Number VHIGH-SPEED Enable Pix Number VHIGH-SPEED Counter V0N V1N V2N Vn HD CCD Operation Mode Start HA 1 1 1 HA #1 VHIGH-SPEED Transfer #1 HA #2 Stop HA 3 HA #3 Readout HA #6 HA 5 1 HA #5 Start 1 VHIGH-SPEED Transfer #2 HA #10 HA 11 Stop HA #11 Active Signal NOTE: Shaded cells indicate the area under discussion. Figure 47. Programmed Operation Mode for An Electric Zoom Function 58 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Register Dynamic Operation Mode The HS changes for a specified number of lines. Specifically, the electric zoom requires a dynamic adjustment of the vertical transfer line number. In addition to the programmed operation mode, the HS enables/disables the line number memory and VEVENT counter; the VEVENT start/stop register enables the dynamic adjustment. HS enable/disable memory is included in the vertical memory area. A VEVENT start command resets the VEVENT counter (bit) at a specified line count. Follow this recommended procedure to: 1. Select the VSIGNAL for the event function. All VSIGNALS for a VHIGH-SPEED transfer must be enabled by a register setting, as shown in Table 60. 2. Select the VSIGNAL for the event counter trigger. This signal counts up the event counter, as shown in Table 61. The last signal of the VHIGH-SPEED transfer is useful. 3. Provide toggling information in the HS memory. 4. Provide HS start and stop instruction in the HA memory. Refer to the Horizontal Sequence section for details. 5. Provide Event instruction in the VA memory. Refer to the Vertical Sequence section for details. 6. Set the event count value for an event start and stop, as shown in Table 62. Table 60. VEVENT Pin Register (1) (1) PARAMETER REGISTER ADDRESS VEVENT pin 030h-032h Refer to the Configuration Register section for details. Table 61. Event Counter Trigger Select Register PARAMETER REGISTER ADDRESS TRG pin 033h[4:0] TRG edge 033h[5] DESCRIPTION Terminal number (V0N-12N) Refer to the Signal section for details. Default = 00000b. 0 = Rising edge (default) 1 = Falling edge Table 62. Event Start/Stop Register PARAMETER EVENT 1 EVENT 2 REGISTER ADDRESS Start 037h, 038h Stop 039h, 03Ah Start 03Bh, 03Ch Stop 03Dh, 03Eh Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 59 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com HA Address Call Note (8) HA1-1: CPOB¯ at Pixel 10 VHIGH-SPEED Transfer #1 1 HA1-2: CPOB at Pixel 40 1: V2N¯ at Pixel 1 2 HA1-3: PBLK¯ at Pixel 51 3 HA1-4: V2N¯ at Pixel 52 Note (3) ¼ Note (7) VA1-2: Instruction at Line 1 Start Event 1 VA1-4: HA2 Start at Line 2 (blank) Event Counter 0 VA1-5: HA3 Start at Line 38 (VHIGH-SPEED #1 End) Note (4) HA1: VHIGH-SPEED #1 Start at Pixel 561 VA1-6: Instruction at Line 38 End Event 2: V0N at Pixel 21 0 13: Repeat at Pixel 179 Repeat ¼ Note (2) HA Address = 0 VHIGH-SPEED Transfer Data Set (HS) ¼ VA1-1: HA1 Start at L ine1 (VHIGH-SPEED #1 Start) (1) Start VHIGH-SPEED Transfer#1 VA1-7: HA6 Start at Line 39 9 VA1-8: HA5 Start at Line 120 (VHIGH-SPEED #2 Start) HA1-10: EOL at Pixel 1023 Call HA Address = 10 VA1-9: Instruction at Line 120 Start Event 2 VA1-10: HA2 Start at Line 121 (blank) VA1-11: HA11 Start at Line 157 (VHIGH-SPEED End) VHIGH-SPEED Transfer #1 10 HA2-1: CPOB¯ at Pixel 10 11 HA2-2: CPOB at Pixel 40 12 HA2-3: PBLK¯ at Pixel 51 16 HA2-7: EOL at Pixel 1023 Do Not Provide VTOGGLING ¼ VA1-12: Instruction at Line 157 End Event 1 ¼ Vertical Data Set (VA) Horizontal Data Set (HA) VA1-13: HA4 Start at Line 158 Call HA Address = 17 VHIGH-SPEED Transfer #1 17 HA3-1: CPOB¯ at Pixel 10 HA3-2: CPOB at Pixel 40 19 HA3-3: PBLK¯ at Pixel 51 20 HA3-4: VHIGH-SPEED End at Pixel 2432 Stop Note (7) ¼ 18 26 29 HA3-10: EOL at Pixel 1023 Item Event # Note (5) Event 1 Start 0 Note (6) Event 1 Stop 29 Event 2 Start 0 Event 2 Stop 29 NOTE: Shaded cells indicate the area under discussion. (1) The HA command block is called by the VA command. (2) Event 1 is started by a VA command at same line number as that of note 1. (3) The HS loop sequence is started by an HA command at the selected pixel number. However, the vertical signal does not output. (4) The event counter is increased by one count a trigger vertical signal. (5) When the event counter reaches the value of the Event 1 Start register, the vertical signal starts to output. (6) When the event counter reaches the value of the Event 1 Stop register, the vertical signal stops outputting. (7) The HS loop sequence is stopped by an HA command at the selected pixel number. (8) The event is stopped by a VA command at the same line number as in note 7. (9) Line number, pixel number, and start of the HA address are programmable. The operation of event 2 is the same as event 1. Figure 48. Register Dynamic Operation Mode Sequence 60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 Table 63. Event Start/Stop (1) (1) PARAMETER EVENT NUMBER Event 1 start 0 Event 1 stop 29 Event 2 start 0 Event 2 stop 29 The operation of Event 2 is the same as Event 1. Vertical high-speed transfer has higher priority than any other vertical transfer instruction. Figure 49 shows the register dynamic operation mode for an electric zoom. Line (HA Number) Pix Number VHIGH-SPEED (HA) VHIGH-SPEED Counter V0N V1N V2N Vn HD VEVENT Counter Event Counter Number VA Line Number CCD Operation Mode 0 HA 1 0 Start 1 0 1 VHIGH-SPEED Transfer #1 1 Event #1 Event #1 HA #1 29 29 38 HA #2 Non VSIGNAL HA 3 Stop HA #3 Readout HA #6 HA 5 Start 1 0 120 HA #5 1 1 Event #2 HA #2 2 Event #2 VHIGH-SPEED Transfer #2 HA 11 Stop 29 29 HA #11 157 Non VSIGNAL NOTE: Shaded cells indicate the area under discussion. Figure 49. Register Dynamic Operation Mode for Electric Zoom Function Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 61 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com FRAME COUNT FUNCTION The frame counter counts up by '1' for each VD update event. The frame counter range is from 1 to 63. This counter value is controlled by the following functions: • SUBSW1 and SUBSW2 control • MSHUT control • Strobe control A counter reset is accomplished by the following operation. The counter value is '1' after reset. • VA instruction (Refer to the Vertical Sequence section for details.) • TRIG (Refer to the Trigger Function section for details.) If the counter value reaches the maximum value (63), the value can only be changed with a frame counter reset. Table 64. Frame Counter Register PARAMETER REGISTER ADDRESS Frame Counter 022h[2] DESCRIPTION 0 = Disabled (default) 1 = Enabled TG REGISTER UPDATE FUNCTION Some registers of the TG section can be selected for update timing. Refer to the Register Update section of the Common Section for details. PIXEL COUNTER PRESET The preset value of the horizontal sequence pixel counter is set, as shown in Table 65. Table 65. Pixel Counter Preset Register PARAMETER REGISTER ADDRESS Pixel Counter Preset 034h[3:0] DESCRIPTION Slave = 6 (default) Master = 0 (recommend) ELECTRIC SHUTTER FUNCTION The electric shutter is operated by the SUBN pattern setting and SUBN pattern change setting. SUBN Pattern Setting The SUBN pattern has four types of toggling positions that are stored in the registers shown in Table 66. Patterns 2 and 3 enable fine pitch integration time control. Table 66. SUBN Pattern Register (1) (1) 62 PATTERN REGISTER ADDRESS Point 1 pixel number and polarity 08Ch-08Eh Point 2 pixel number and polarity 08Fh-091h Point 3 pixel number and polarity 092h-094h Point 4 pixel number and polarity 095h-097h Refer to the Configuration Register section for details. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 Not Recommended for New Designs VSP01M01 VSP01M02 www.ti.com SBES016 – MARCH 2009 The SUBN pattern is specified by each point combination, as Table 67 shows. Table 67. SUBN Pattern Description PATTERN DESCRIPTION 0 Non SUBN pulse 1 Operation of point 1 and point 2 2 Operation of point 3 and point 4 3 Operation of points 1 to 4 Table 68 describes an example SUBN pattern. Figure 50 shows a four-pattern example of an electric shutter. Table 68. SUBN Pattern Example TOGGLE POINT PIXEL NUMBER POLARITY 1 50 0 2 80 1 3 180 0 4 210 1 Toggle Point 1 Toggle Point 2 Toggle Point 3 Toggle Point 4 50 80 180 210 HD Pattern 0 Pattern 1 Pattern 2 Pattern 3 Figure 50. Electric Shutter Four-Pattern Example SUBN Pattern Change The electric shutter function has four sequential registers, as shown in Table 69. For each register, the SUBN pattern is assigned among four types of patterns and is selected at the pattern change point. Table 69. SUBN Pattern Change (1) PARAMETER (1) REGISTER ADDRESS Pattern change point 1 line number and SUBN pattern number 098h-09Ah Pattern change point 2 line number and SUBN pattern number 09Bh-09Dh Pattern change point 3 line number and SUBN pattern number 09Eh-0A0h Pattern change point 4 line number and SUBN pattern number 0A1h-0A3h Refer to the Configuration Register section for details. Table 70 lists an electrical shutter example method with the register update function activated. Table 70. Register Update Setting PARAMETER REGISTER ADDRESS VALUE TG Update 000h[3] 1 = VA Internal instruction (R_UPDATE) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Links: VSP01M01 VSP01M02 63 Not Recommended for New Designs VSP01M01 VSP01M02 SBES016 – MARCH 2009 www.ti.com This example method has three cases of exposure time within one frame cycle. Table 71 lists several electrical shutter parameters. Table 71. Electrical Shutter Parameter PARAMETER LINE NUMBER SUBN operation term A Exposure time B Read out C 1 frame cycle D R_UPDATE 1 NOTE Use with calculation of Table 72 Should be provided at the VA internal instruction Table 72. SUBN Start and End Line Number (1) LINE NUMBER CASE (1) DESCRIPTION CONDITION SUBN_START SUBN_END 1 Line number 1 ≤ SUBN_Start < SUBN _End < Read_out C–B–A≥0 C–B–A C–B 2 Line number 1 ≤ SUBN _End < Read_out < SUBN _Start (C – B ≥ 0) and (C – B – A < 0) D + (C – B – A) C–B 3 Line number 1 < Read_out < SUBN _Start < SUBN _End C–B