VSP7500
VSP7502
www.ti.com
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
FOUR-CHANNEL IMAGE SENSOR ANALOG FRONT-END
Check for Samples: VSP7500, VSP7502
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
Four-Channel Signal Paths
– VSP7500: Supports CDS Input
– VSP7502: Supports SH Input
Maximum Data Throughput: 56 MHz
Dual Inputs for Each Signal Path
16-Bit A/D Conversion:
– No Missing Codes Ensured
Programmable Gain Amplifier (PGA):
– Analog Front Gain: 0 dB to +9.6 dB
(0.28-dB Step)
– Digital Gain: 0 dB to +32 dB
(0.032-dB Step)
Wide Range of Input Common Voltage
Operation Voltage and Power Consumption:
– Voltage: 1.65 V to 1.95 V and 2.7 V to 3.6 V
Power: 400 mW
(at VDD = 1.8 V, fMCLK = 50 MHz)
Digital Video Cameras (DVCs)
Digital Still Cameras (DSCs)
Front End for Multichannel Sensors
High-Speed Machine Vision
High-Resolution Surveillance Cameras
High-Speed/High-Resolution Scanners
Medical
DESCRIPTION
The VSP7500/VSP7502 are four-channel analog
front-ends (AFEs) for imaging signals. These devices
include a correlated double sampler (CDS),
programmable gain amplifier (PGA), analog-to-digital
converter (ADC), input clamp, optical black (OB) level
clamp loop, serial interface, and adjustable sampling
timing control. The VSP7502 provides the same
functionality with a sample/hold (S/H) mode to
support
CMOS
and
CIS
sensors.
The
VSP7500/VSP7502 are offered in a BGA-159
package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
VSP7500
VSP7502
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
VSP7500
BGA-159
ZWV
–25°C to +85°C
VSP7500ZWV
VSP7502
BGA-159
ZWV
–25°C to +85°C
VSP7502ZWV
ORDERING
NUMBER
TRANSPORT MEDIA,
QUATITY
VSP7500ZWV
Tray, 360
VSP7500ZWVR
Tape and Reel, 3000
VSP7502ZWV
Tray, 360
VSP7502ZWVR
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VSP7500, VSP7502
UNIT
2.4
V
4
V
Supply voltage differences (among power-supply pins)
±0.1
V
Ground voltage differences (among GND pins)
±0.1
V
–0.15 to (DVDD2 + 0.15)
V
Digital input voltage
(HD, VD, MCLK, RST, SCLK, SCS, SDI)
–0.3 to (DVDD3 + 0.3)
V
Analog input voltage
(IN_W, IN_X, IN_Y, IN_Z, IP_W, IP_X, IP_Y, IP_Z)
–0.3 to (AVDD3 + 0.3)
V
Supply voltage
(AVDD2, DLLVDD2, REFVDD, DRVDD2, DVDD2, DVDD2_SPI)
Supply voltage
(AVDD3, RGVDD3, H1VDD3, H2VDD3, DVDD3, DVDD3_SPI)
Digital input voltage
(ATPG, MN_DM, MN_KBLK, MN_OB, MN_PBLK)
Input current (all pins except supplies)
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Package temperature (reflow, peak)
+260
°C
(1)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
VSP7500
VSP7502
www.ti.com
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS (1)
All specifications at TA = +25°C, all power-supply voltages = +3 V, and conversion rate = 36 MHz, unless otherwise noted.
VSP7500, VSP7502
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.65
1.8
1.95
V
2.7
3
3.6
V
1.65
1.8
1.95
V
2.7
3
3.6
V
2.7
3
3.6
V
POWER SUPPLY
AVDD2
REFVDD
Analog supply
voltage
DLLVDD2
LVAVDD
LVDLLVDD
AVDD3
DVDD2
DVDD2_SPI
DRVDD2
Digital supply
voltage
DVDD2_SPI
LVDVDD
DRVDD2
DVDD3
DVDD3_SPI
H-TG supply
voltage
HVDD3
Power dissipation
VDD = typ, fMCLK = 50MHz
400
mW
Power-down mode (fMCLK = 0 MHz)
10
mW
16
Bits
RESOLUTION
Resolution
THROUGHPUT RATE
Maximum data throughput rate
50
56
MHz
SIGNAL PATHS
Signal paths
VCC = 3 V
4
Channels
DIGITAL INPUTS
Logic family
IIH
CMOS
Input current
IIL
Logic high, VIN = +1.8 V
1
mA
Logic low, VIN = 0 V
1
mA
60
%
MCLK clock duty cycle
40
Input capacitance
50
5
pF
DIGITAL OUTPUT (CMOS Buffer RG, H1, H2, LH)
VOH
Logic high, IOH = –2 mA
Output voltage
VOL
VDD – 0.3
V
Logic low, IOL = 2 mA
VDD + 0.3
V
ANALOG INPUT
Input signal level for full-scale out
Input voltage
Gain = 0 dB
1
for INP pin
VPP
VCC
for INN pin
GND
Input capacitance
V
10
Input limit
V
GND – 0.3
pF
VCC + 0.3
V
REFERENCE
Positive reference voltage
1.25
V
Negative reference voltage
0.75
V
INPUT CLAMP
Clamp-on resistance
2
Clamp level
(1)
1.8
kΩ
V
All values listed are preliminary. Final values to be determined after evaluation.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
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3
VSP7500
VSP7502
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS(1) (continued)
All specifications at TA = +25°C, all power-supply voltages = +3 V, and conversion rate = 36 MHz, unless otherwise noted.
VSP7500, VSP7502
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSFER CHARACTERISTICS
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
No missing codes
±1
LSB
±32
LSB
Ensured
Step response settling time
Overload recovery time
Full-scale step input
1
Step input from 1.8 V to 0 V
2
Data latency
Signal-to-noise ratio (2)
Grounded input capacitor
Pixels
11
Clocks
200
mV
77
Sensor offset correction range
–200
Channel isolation
Pixels
Among each channel
dB
–77
dB
PROGRAMMABLE GAIN (Analog)
Analog gain programmable range
0
Analog gain programmable step
+9.6
0.28
Analog gain step monotonocity
dB
dB
Ensured
Analog gain error
For setting gain
0.5
dB
32
dB
PROGRAMMABLE GAIN (Digital)
Digital gain programmable range
0
Digital gain programmable step
0.032
dB
40.7
ms
OPTICAL BLACK CLAMP (OBCLP) LOOP
Loop time constant
Programmable range of
clamp level
Optical black clamp level
1024
OBCLP level at code =
1000 0000 0000b (center)
OB level program step
3072
LSB
2048
LSB
1
LSB
6
Bits
±250
mV
PRIMARY ANALOG OB CLAMP LOOP
OB DAC resolution
OB DAC full-scale voltage
LVDS BUFFER (D0, D1, CKS)
RL
Differential load impedance
|VOD|
Differential steady-state output voltage
magnitude
90
RL = 100 Ω
Δ|VOD|
Change in the steady-state differential output
voltage magnitude between opposite binary
states
RL = 100 Ω
VOC(SS)
Steady-state common-mode output voltage
VOC(PP)
Peak-to-peak common-mode output
IOS
Short-circuit output current
IOZ
High-impedance state output current
100
90
110
Ω
110
mV
15
mV
V
COM_SEL = 0 (0.9 V mode)
0.7
1.1
COM_SEL = 1 (1.2 V mode)
1
1.4
V
50
mV
20
Output = GND
–6
6
mA
VO = 0 V to VCC
–10
10
mA
–25
+85
°C
TEMPERATURE RANGE
Operating temperature
(2)
4
SNR = 20 log (full-scale voltage/rms noise).
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
VSP7500
VSP7502
www.ti.com
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
Mn_OB
Mn_DM
Mn_HBLK
Mn_PBLK
FUNCTIONAL BLOCK DIAGRAM
HD
VD
MCLK RST SDATA SCLK SCS
Serial Interface and Internal Timing Control
Voltage DAC
Buffer
MCLK
L_W
Decoder
RP_W
Internal
Reference
CM_W
RN_W
IN_W
CDS
S/H
IP_W
Clamp
SHP
OB
Correction
Channel W
16-Bit ADC
ADCK
SHP/SHD A
DIGCK
DW_0+
Digital
Block
D8-D15
LVDS
DW_0-
Serializer
Parallel Load
8-Bit Shift Register
DIGCK
DW_1+
D0-D7
LVDS
DW_1L_X
Voltage DAC
Buffer
RP_X
Decoder
Internal
Reference
CM_X
RN_X
IN_X
CDS
S/H
IP_X
Clamp
SHP
OB
Correction
Channel X
16-Bit ADC
ADCK
SHP/SHD A
DIGCK
DX_0+
Digital
Block
D8-D15
LVDS
DX_0-
Serializer
Parallel Load
8-Bit Shift Register
DIGCK
DX_1+
D0-D7
LVDS
DX_1BYPD
RG
H1
H2
CKS_0+
DLL
LVDS
CKS_0LV_DLL
BYPD_LV
CKS_1+
LVDS
MCLK
CKS_1L_Y
Voltage DAC
Buffer
RP_Y
Decoder
Internal
Reference
CM_Y
RN_Y
IN_Y
CDS
S/H
IP_Y
Clamp
SHP
OB
Correction
Channel Y
16-Bit ADC
ADCK
SHP/SHD A
DIGCK
DY_0+
Digital
Block
DIGCK
D8-D15
DY_0-
Serializer
Parallel Load
8-Bit Shift Register
DY_1+
D0-D7
DY_1L_Z
Voltage DAC
Buffer
RP_Z
Decoder
Internal
Reference
CM_Z
RN_Z
IN_Z
CDS
S/H
IP_Z
Clamp
SHP
OB
Correction
Channel Z
16-Bit ADC
SHP/SHD A
ADCK
DIGCK
DZ_0+
Digital
Block
DIGCK
D8-D15
Serializer
Parallel Load
8-Bit Shift Register
DZ_0-
DZ_1+
D0-D7
DZ_1-
NOTE: VSP7500 = CDS, VSP7502 = SH.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
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5
VSP7500
VSP7502
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
SYSTEM DESCRIPTION
SAMPLE-AND-HOLD (S/H) MODE
In S/H mode, the VSP7502 input circuit is configured for sample-and-hold operation by the serial interface
setting. Figure 1 shows a simplified input circuit of the S/H mode. In this mode, the input signal is sampled by the
SHD signal.
SHD
Sensor Signal
Input
INP
INN
SHD
Figure 1. S/H Input Mode Block Diagram
CORRELATED DOUBLE SAMPLER (CDS) MODE
In CDS mode, the VSP7500/VSP7502 input circuit is reconfigured as a CDS by the serial interface setting.
Figure 2 shows a simplified input circuit of the CDS mode.
SHP/SHD
Sensor Signal
Input
IPINSHP/SHD
CLPDM
CLPDM
SHP
SHP
REF
REF
Figure 2. CDS Input Mode Block Diagram
INPUT CLAMP
In the charge-coupled device (CCD) input mode, the INP pin of the VSP7500/VSP7502 are connected to the
buffered CCD output through capacitive coupling; therefore, an input clamp is necessary. The purpose of the
input clamp is to restore the dc component of the input signal that is lost during ac coupling and establish the
desired dc bias point for CDS. Figure 2 also illustrates the input clamp. The input level is clamped to the internal
reference voltage during the dummy pixel interval. More specifically, the clamping function becomes active when
both CLPDM and SHP are active.
16-BIT ADC
The VSP7500/VSP7502 also provide a high-speed, 16-bit ADC. This ADC uses a fully-differential, pipelined
architecture with a correction feature. This architecture achieves better linearity at lower signal levels because
large linearity errors tend to occur at specific points in the full-scale range, and linearity improves for a signal
level below that specific point. The ADC ensures 16-bit resolution for the entire full-scale range.
6
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Product Folder Link(s): VSP7500 VSP7502
VSP7500
VSP7502
www.ti.com
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
OPTICAL BLACK (OB) LOOP AND OB CLAMP (OBCLP) LEVEL
The VSP7500/VSP7502 have a built-in optical black (OB) offset self-calibration circuit (OB loop) that
compensates the OB level by using OB pixels that are output from the CCD image sensor. This device also
provides a digital OB clamp loop. CCD offset is compensated by converging both OB loops while activating
CLPOB during a period when OB pixels are output from the CCD. 20 pixels of the CLPOB period may be enough
for stable OB loop operation.
CLOCKING AND DLL
The VSP7500/VSP7502 require the following clocks for proper operation: MCLK, the system clock; CLPOB, the
optical black level clamp; and CLPDM, the input clamp.
The HBLK timing signal transmits the horizontal blanking period timing. In this period, high-speed HTG pulses
are masked. The PBLK timing signal transmits the data output blanking period timing. In this period, outputting
the ADC data is masked.
The VSP7500/VSP7502 have built-in DLL circuits that enable the required sampling clocks and the horizontal
timing pulse and logic clocks for outputting LVDS data to be generated.
VOLTAGE REFERENCE
All reference voltages and bias currents used on the VSP7500/VSP7502 are created from internal bandgap
circuitry. The device has a symmetrically independent voltage reference for each channel.
Both channels of the S/H, CDS, and the ADC use three primary reference voltages: REFP (1.25 V), REFN
(0.75 V), and CM (1 V) of individual references. REFP and REFN are buffered on-chip. CM is derived as the
midrange voltage of the resistor chain internally connecting REFP and REFN. The ADC full-scale range is
determined by twice the difference voltage between REFP and REFN.
REFP, REFN, and CM should be heavily decoupled with appropriate capacitors.
HOT PIXEL REJECTION
Sometimes, OB pixel output signals from the CCD include unusual level signals that are caused by pixel
defection. If this level reaches a full-scale level, it may affect OB level stability. The VSP7500/VSP7502 have a
function that rejects the unusually large pixel levels (hot pixels) in the OB pixel. This function may contribute to
CCD yield improvement that is caused by OB pixel failure.
Rejection level for hot pixels is programmable through the serial interface. When hot pixels come from the CCD,
the VSP7500/VSP7502 omit them and replace the previous pixel level with the OB level calculation.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
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7
VSP7500
VSP7502
SBES015A – DECEMBER 2010 – REVISED JANUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2010) to Revision A
•
8
Page
Added last four bullets to Applications section ..................................................................................................................... 1
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): VSP7500 VSP7502
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
VSP7500ZWV
ACTIVE
NFBGA
ZWV
159
348
Pb-Free (RoHS)
SNAGCU
Level-2-260C-1 YEAR
VSP7500ZWVR
ACTIVE
NFBGA
ZWV
159
1000
Pb-Free (RoHS)
SNAGCU
Level-2-260C-1 YEAR
VSP7502ZWV
ACTIVE
NFBGA
ZWV
159
260
TBD
Call TI
VSP7502ZWVR
ACTIVE
NFBGA
ZWV
159
1000
Pb-Free (RoHS)
SNAGCU
Call TI
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSP7500ZWVR
NFBGA
ZWV
159
1000
330.0
16.4
8.3
8.3
1.85
12.0
16.0
Q1
VSP7502ZWVR
NFBGA
ZWV
159
1000
330.0
16.4
8.3
8.3
1.85
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
VSP7500ZWVR
NFBGA
ZWV
159
1000
342.0
336.0
34.0
VSP7502ZWVR
NFBGA
ZWV
159
1000
342.0
336.0
34.0
Pack Materials-Page 2
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