X66AK2G01ZBB60

Product Folder Order Now Technical Documents Tools & Software Support & Community 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 66AK2G0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 Device Overview 1.1 Features • Processor Cores: • ARM® Cortex®-A15 Microprocessor Unit (ARM A15) Subsystem at up to 600 MHz – Supports Full Implementation of ARMv7-A Architecture Instruction Set – Integrated SIMDv2 ( NEON™ Technology) and VFPv4 (Vector Floating Point) – 32KB of L1 Program Memory – 32KB of L1 Data Memory – 512KB of L2 Memory – Error Correction Code (ECC) Protection for L1 Data Memory ECC for L2 Memory – Parity Protection for L1 Program Memory – Global Timebase Counter (GTC) – 64-Bit Free-Running Counter That Provides Timebase for ARM A15 Internal Timers – Compliant to ARM V7 MPCore Architecture for Generic Timers • C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600 MHz – Fully Object-Code Compatible With C67x+ and C64x+ Cores – 32KB of L1 Program Memory – 32KB of L1 Data Memory – 1024KB of L2 Configurable as L2 RAM or Cache – Error Detection for L1 Program Memory – ECC for L1 Data Memory – ECC for L2 Data Memory • Industrial Subsystem: • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRUICSS), Each Supports: – Two Programmable Real-Time Units (PRUs) With Enhanced Multiplier and Accumulator, Each PRU Supports: – 16KB of Program Memory With ECC – 8KB of Data Memory With ECC – CRC32 and CRC16 Hardware Accelerator – 20 × Enhanced GPIO – Serial Capture Unit (SCU), Supporting Direct Connection, 16-bit Parallel Capture, 28-bit Shift, MII_RT, EnDat 2.2 Protocol and SigmaDelta Demodulation – Scratch Pad and XFR Direct Connect – 64KB of General-Purpose Memory With ECC • • • • – One Ethernet MII_RT Module with Two MII Ports Configurable for Connection With Each PRU; Support Multiple Industrial Communication Protocols – Industrial Ethernet Peripheral (IEP) to Manage and Generate Industrial Ethernet Functions – Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, With a Dedicated 192-MHz Clock to Support 12-Mbps PROFIBUS® – Built-In Industrial Ethernet 64-Bit Timer – Built-In Enhanced Capture Module (eCAP) Memory Subsystem: Multicore Shared Memory Controller (MSMC) With 1024KB of Shared L2 RAM – Provides High-Performance Interconnect to Internal Shared SRAM and DDR EMIF for Both ARM A15 and C66x Access – Supports ARM I/O Coherency Where ARM A15 is Cache Coherent to Other System Masters Accessing the MSMC-SRAM or DDR EMIF – Supports ECC on SRAM Up to 36-Bit DDR External Memory Interface (EMIF) – Supports DDR3L at up to 800 MT/s – Supports 4-GB Memory Address Range – Supports 32-Bit SDRAM Data Bus With 4-bit ECC – Supports 16-Bit and 32-Bit SDRAM Data Bus Without ECC General-Purpose Memory Controller (GPMC) – Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Four Chip Selects – Supports NAND, NOR, Muxed-NOR, SRAM – Supports General-Purpose Memory-Port Expansion With the Following Modes: – Asynchronous Read and Write Access – Asynchronous Read Page Access (4-, 8-, 16Word16) – Synchronous Read and Write Access – Synchronous Read Burst Access Without Wrap Capability (4-, 8-, 16-Word16) – Up to 16-Bit ECC Support for NAND Flash Using BCH Code (t = 4, 8, or 16) or Hamming Code 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION 1 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 ADVANCE INFORMATION • Error Location Module (ELM) – Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm – Supports 4-Bit, 8-Bit and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms – Provides ECC Calculation (Up to 16 bits) for NAND Support • Network Subsystem (NSS): • Ethernet MAC Subsystem (EMAC) – One-Port Gigabit Ethernet: RMII, MII, RGMII – Supports 10-, 100-, 1000-Mbps Full Duplex – Supports 10-, 100-Mbps Half Duplex – Supports Ethernet Audio Video Bridging (eAVB) – Maximum Frame Size 2016 Bytes (2020 Bytes With VLAN) – Eight Priority Level QOS Support (802.1p) – IEEE 1588v2 (2008 Annex D, Annex E, and Annex F) to Facilitate Audio Video Bridging 802.1AS Precision Time Protocol – CPTS Module With Timestamping Support for IEEE 1588v2 – DSCP Priority Mapping (IPv4 and IPv6) – MDIO Module for PHY Management – Enhanced Statistics Collection • Navigator Subsystem (NAVSS) – Built-In Packet DMA Controller for Optimized Network Processing – Built-In Queue Manager (QM) for Optimized Network Processing – Supports up to 128 Queues – 2048 Buffers Supported in Internal Queue RAM • Crypto Engine (SA) Supports: – Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations – Block Data Encryption Supported Through Hardware Cores – AES With 128-, 192-, and 256-Bit Key Supports – DES and 3DES With 1, 2, or 3 Different Key Support – Programmable Mode Control Engine (MCE) – Public Key Accelerator (PKA) With Elliptic Curve Cryptography – Elliptic Curve Diffie–Hellman (ECDH) Based Key Exchange and Digital Signature (ECDSA) Applications – Authentication for SHA1, MD5, SHA2-224 and SHA2-256 – Keyed HMAC Operation Through Hardware Core – True Random Number Generator (TRNG) 2 Device Overview www.ti.com • Display Subsystem: • Supports One Video Pipe With In-Loop Scaling, Color Space • Conversion and Background Color Overlay • Input Data Format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8 • Supported Display Interfaces: – MIPI® DPI 2.0 Parallel Interface – RFBI (MIPI-DBI 2.0) up to QVGA at 30fps – BT.656 4:2:2 – BT.1120 4:2:2 up to 1920 × 1080 at 30fps • In-Loop Scaling Capability • LCD Display Interface Supports: – Active Matrix (TFT) – Passive Matrix (STN) – Grayscale – TDM – AC Bias Control – Dither – CPR • High-Speed Serial Interfaces: • PCI Express® 2.0 Port with Integrated PHY: – Single Lane Gen2-Compliant Port – Root Complex (RC) and End Point (EP) Modes • Up to Two USB 2.0 High-Speed Dual-Role Ports With Integrated PHYs, Support: – Dual-role-device (DRD) Capability With: – USB 2.0 Peripheral (or Device) at HS (480Mbps) and FS (12Mbps) Speeds – USB 2.0 Host at HS (480Mbps), FS (12Mbps), and LS (1.5Mbps) Speeds – USB 2.0 Static Peripheral and Static Host Operations – xHCI Controller With the Following Features: – Compatible to the xHCI Specification (revision 1.1) in Host Mode – All Modes of Transfer (Control, Bulk, Interrupt, and Isochronous) – 15 Transmit (TX), 15 Receive (RX) Endpoints (EPs), and One Bidirectional EP0 Endpoint • Flash Media Interfaces: • QSPI™ With XIP and up to Four Chip Selects, Supports: – Memory-Mapped Direct Mode of Operation for Performing FLASH Data Transfers and Executing Code From FLASH Memory (XIP) – Supports up to 96 MHz – Internal SRAM Buffer With ECC – High Speed Read Data Capture Mechanism Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • Two Multimedia Card (MMC) and Secure Digital (SD) Ports – Supports JEDEC JESD84 v4.5-A441 and SD3.0 Physical Layer With SDA3.00 Standards – MMC0 Supports 3.3-V I/O for: – SD DS and HS Mode – eMMC Mode HS-SDR and DDR up to 48 MHz – MMC1 Supports 1.8-V I/O Modes for eMMC, Including HS-SDR and DDR at up to 48 MHz With 4- and 8-Bit Bus Width • Audio Peripherals: • Three Multichannel Audio Serial Port (McASP) Peripherals – Transmit and Receive Clocks up to 50 MHz – Two Independent Clock Zones and Independent Transmit and Receive Clocks per McASP – Up to 16-, 10-, 6-Serial Data Pins for McASP0, McASP1, and McASP2, Respectively – Supports TDM, I2S, and Similar Formats – Supports DIT Mode – Built-In FIFO Buffers for Optimized System Traffic • Multichannel Buffered Serial Port (McBSP) – Transmit and Receive Clocks up to 50 MHz – Two Clock Zones and Two Serial-Data Pins – Supports TDM, I2S, and Similar Formats • Automotive Peripherals: • Two Controller Area Network (CAN) Ports – Supports CAN v2.0 Part A, B (ISO 11898-1) Protocol – Bit Rates up to 1 Mbps – Dual Clock Source – ECC Protection for Message RAM • One Media Local Bus (MLB) – Supports Both 3-Pin (Up to MOST50, 1024 × Fs) and 6-Pin (Up to MOST150, 2048 × Fs) Versions of MediaLB® Physical Layer Specification v4.2 – Supports All Types of Data Transfer Over 64 Logical Channels (Synchronous Stream, Isochronous, Asynchronous Packet, Control Message) – Supports 3-Wire MOST 150 Protocol • Real-Time Control Interfaces: • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter Supports: – Dedicated 16-Bit Time-Base With Period and Frequency Control – Two Independent PWM Outputs With Single Edge Operation – Two Independent PWM Outputs With Dual-Edge Symmetric Operation • • • • • • • • • • – One Independent PWM Output With Dual-Edge Asymmetric Operation Two 32-Bit Enhanced Capture Modules (eCAP): – Supports One Capture Input or One Auxiliary PWM Output Configuration Options – 4-Event Time-Stamp Registers (Each 32-Bits) – Interrupt on Either of the Four Events Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), Each Supports: – Quadrature Decoding – Position Counter and Control Unit for Position Measurement – Unit Time Base for Speed and Frequency Measurement General Connectivity: Three Inter-Integrated Circuit (I2C) Interfaces, Each Supports: – Standard (up to 100 kHz) and Fast (up to 400 kHz) Modes – 7-Bit Addressing Mode – Supports EEPROM Size Up to 4Mbit Four Serial Peripheral Interfaces (SPI), Each Supports: – Operates at up to 50 MHz in Master Mode and 25 MHz in Slave Mode – Two Chip Selects Three UART Interfaces – All UARTs are 16C750-Compatible and Operate at Up to 3M Baud – UART0 Supports 8 Pins With Full Modem Control, With DSR, DTR, DCD, and RI Signals – UART1 and UART2 are 4-Pin Interfaces General-Purpose I/O (GPIO) – Up to 212 GPIOs Muxed With Other Interfaces – Can be Configured as Interrupt Pins Timers and Miscellaneous Modules: Seven 64-Bit Timers: – Two 64-Bit Timers Dedicated to ARM A15 and DSP Cores (One Timer per Core) – Watchdog and General-Purpose (GP) – Four 64-Bit Timers are Shared for General Purposes – Each 64-Bit Timer Can be Configured as Two Individual 32-Bit Timers – One 64-Bit Timer Dedicated for PMMC – Two Timers Input/Output Pin Pairs Interprocessor Communication With: – Message Manager to Facilitate Multiprocessor Access to the PMMC: – Provides Hardware Acceleration for Pushing and Popping Messages to/from Logical Queues Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Device Overview 3 ADVANCE INFORMATION www.ti.com 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com – Supports Up to 64 Queues and 128 Messages – Semaphore Module With Up to 64 Independent Semaphores and 16 Masters (device cores) • EDMA With 128 (2 × 64) Channels and 1024 (2 × 512) PaRAM Entries • Keystone II System on Chip (SoC) Architecture: • Security – Supports General-Purpose (GP) and HighSecure (HS) Devices – Supports Secure Boot – Supports Customer Secondary Keys – 4KB of One-Time Programmable (OTP) ROM for Customer Keys 1.2 ADVANCE INFORMATION • • • Applications Industrial Communications and Controls Automotive Audio Amplifiers Home Audio 1.3 • Power Management – Integrated Power Management Microcontroller (PMMC) Technology • Supports Primary Boot From UART, I2C, SPI, GPMC, SD or eMMC, USB Device Firmware Upgrade v1.1, PCIe®, and Ethernet Interfaces • Keystone II Debug Architecture With Integrated ARM CoreSight™ Support and Trace Capability • Operating Temperature (TJ): • –40°C to 125°C (Automotive) • –40°C to 105°C (Extended) • 0°C to 90°C (Commercial) • • • Professional Audio Power Protection Other Embedded Systems Description 66AK2G0x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s fieldproven Keystone II (KS2) architecture. These devices address applications that require both DSP and ARM performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support. Similar to existing KS2-based SoC devices, the 66AK2G0x enables both the DSP and ARM cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or ARM-centric system designs can be achieved. The 66AK2G0x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G0x parts satisfy a wide range of industrial and automotive requirements. Accompanied by the new Processor SDK, the 66AK2G0x development platform enables unprecedented ease-of-use with main line open source Linux, CCS 6.x, a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and ARM, such as system trace and seamless integration of the ARM CoreSight components. Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative. Table 1-1. Device Information(1) PACKAGE BODY SIZE 66AK2G02 PART NUMBER NFBGA (625) 21.0 mm × 21.0 mm 66AK2G01 NFBGA (625) 21.0 mm × 21.0 mm (1) For more information, see Section 9, Mechanical Packaging and Orderable Information. 4 Device Overview Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 1.4 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Functional Block Diagram Figure 1-1 is a block diagram of the device. 66AK2G0x Industrial Subsystem 1x ARM® Cortex®–A15 1x C66x DSP 2x PRU-ICSS 1MB L2 w/ ECC Network Subsystem Memory Subsystem EMAC MSMC 1MB RAM w/ ECC PMMC eAVB/1588v2 RGMII/RMII/MII 7x Timers 64-bits EMIF 36-bits DDR3L w/ ECC NAVSS Queue Manager PKTDMA EDMA Semaphore ELM Display Subsystem 1x Video Pipeline Blend/Scale/CSC SA Crypto Engine Message Manager GPMC ADVANCE INFORMATION 512KB L2 w/ ECC LCD DPI TeraNet Automotive Interfaces Control Interfaces General Connectivity 6x ePWM 2x GPIO 2x eCAP 3x UART High-Speed Serial Interfaces PCIe® Single Lane Gen 2 3x eQEP 4x SPI 2x USB 2.0 2x DCAN MediaLB® MOST150 Audio Peripherals 3x McASP McBSP 3x I2C Media & Data Storage QSPI Dual Role + PHY 2x MMC/SD intro_001 Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Functional Block Diagram Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Device Overview 5 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.2 Functional Block Diagram 1.1 Features .............................................. 1 6.3 ARM A15........................................... 174 1.2 Applications ........................................... 4 6.4 C66x DSP Subsystem ............................. 175 1.3 Description ............................................ 4 6.5 C66x Cache Subsystem ........................... 176 ........................... 5 Revision History ......................................... 7 Device Comparison ..................................... 8 3.1 Related Products ..................................... 9 Terminal Configuration and Functions ............ 10 4.1 Pin Diagram ......................................... 10 4.2 Pin Attributes ........................................ 10 4.3 Signal Descriptions .................................. 41 4.4 Pin Multiplexing ..................................... 72 4.5 Connections for Unused Pins ....................... 83 Specifications ........................................... 84 5.1 Absolute Maximum Ratings ......................... 84 5.2 ESD Ratings ........................................ 84 5.3 Power-On-Hour (POH) Limits(1)(2)(3) ................ 84 5.4 Recommended Operating Conditions ............... 85 5.5 Operating Performance Points ...................... 86 5.6 Power Consumption Summary...................... 86 5.7 Electrical Characteristics ............................ 87 6.6 PRU-ICSS.......................................... 176 6.7 Memory Subsystem ................................ 178 6.8 Interprocessor Communication 6.9 EDMA .............................................. 183 6.10 Peripherals ......................................... 184 1.4 2 3 4 5 ADVANCE INFORMATION 8 181 Applications, Implementation, and Layout ...... 202 7.1 DDR3L Board Design and Layout Guidelines ..... 202 7.2 7.3 High Speed Differential Signal Routing Guidance . 222 Power Distribution Network Implementation Guidance ........................................... 222 7.4 Single-Ended Interfaces 7.5 Clock Routing Guidelines .......................... 223 ........................... 223 Device and Documentation Support .............. 225 Device Nomenclature .............................. 225 8.2 Tools and Software ................................ 226 8.3 Documentation Support ............................ 226 8.4 Related Links 8.5 Receiving Notification of Documentation Updates. 227 Thermal Resistance Characteristics for ZBB Package ............................................. 93 8.6 Community Resources............................. 227 8.7 Trademarks ........................................ 227 Timing and Switching Characteristics ............... 94 8.8 Electrostatic Discharge Caution Detailed Description.................................. 172 8.9 Glossary............................................ 227 5.9 6.1 6 7 .................... 173 8.1 5.8 6 Functional Block Diagram ......................... Overview ........................................... 172 Table of Contents 9 ...................................... ................... 226 227 Mechanical Packaging and Orderable Information ............................................. 228 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 2 Revision History Changes from April 3, 2017 to June 8, 2017 (from D Revision (April 2017) to E Revision) • • • • • • Changed all instances of „No“ to „Not Supported“. Added a note to Device Comparison table ........................... 8 Updated DDR3_RZQ0 and DDR3_RZQ1 resistor values .................................................................... 44 Added specific resistor values to USBi Analog Kelvin Connection pins in USB Signal Descriptions Table ............ 53 Removed I2C_* PADCONFIG register from Table 4-28 Pin Multiplexing ................................................... 72 Added DDR3_CBDQS_N/P balls to Table 4-29 Unused Balls Specific Connection Requirements ..................... 83 Moved SPI0_SCSn0 and SPI1_SCSn0 signals to the second row of the tie-off specific connection requirements in Table 4-29 ......................................................................................................................... 83 Updated Section 5.3 Power-On-Hour (POH) Limits ........................................................................... 84 Removed voltage references from Power-Up Sequencing diagram.......................................................... 95 Added External Single-ended Input Clock subsection for LVDS input clock operation .................................. 100 Deleted parentheses from stop bit 1.5 and 2 (parameter U3) to consistent with the values for stop bit 1 ............ 169 ADVANCE INFORMATION • • • • Page Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Revision History 7 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 3 Device Comparison Table 3-1 lists the features of the 66AK2G0x devices. Table 3-1. Device Comparison FEATURES REFERENCE NAME 66AK2G02 66AK2G01 PROCESSORS AND ACCELERATORS Speed Grades See Table 5-1 See Table 5-1 ARM Cortex-A15 Microprocessor Subsystem ARM A15 Yes Yes C66x VLIW Digital Signal Processor C66x Yes Yes Power Management Micro Controller PMMC Yes Yes Display Subsystem DSS Yes Not Supported(1) PROGRAM AND DATA STORAGE ADVANCE INFORMATION Multicore Shared Memory Controller MSMC Up to 1MB (On-Chip Shared SRAM With ECC) Up to 1MB (On-Chip Shared SRAM With ECC) General-Purpose Memory Controller GPMC Up to 1GB Up to 1GB DDR External Memory Interface EMIF Error Location Module Up to 4GB (32 Bit data) Up to 2GB (16 Bit data) SECDED/ECC Yes Not Supported(1) ELM Yes Yes PERIPHERALS Dual Controller Area Network Interface DCAN 2 2 Enhanced Direct Memory Access EDMA Yes Yes EMAC RMII, MII, RGMII With eAVB RMII, MII, RGMII With eAVB NAVSS PKTDMA and QM PKTDMA and QM Yes Yes Up to 212 Up to 212 Network Subsystem SA General-Purpose I/O GPIO Inter-Integrated Circuit Interface I2C Message Manager MSGMGR Semaphore SEM Yes Yes Media Local Bus Subsystem MLB Yes (3-pin or 6-pin Modes) Yes (3-pin or 6-pin Modes) Multichannel Buffered Serial Port McBSP Yes Yes McASP0 16 Serializers 16 Serializers McASP1 10 Serializers 10 Serializers McASP2 6 Serializers 6 Serializers MMC0 eMMC, SD (3.3 V) 8-bits eMMC, SD (3.3 V) 8-bits MMC1 eMMC (1.8 V) - 8-bits eMMC (1.8 V) - 8-bits Yes (Single-Lane Mode) Not Supported(1) Multichannel Audio Serial Port MultiMedia Card, Secure Digital Interface (MMC/SD) 3 3 Yes Yes PCI Express 2.0 Port with Integrated PHY PCIESS Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem PRU-ICSS 2 Not Supported(1) Serial Peripheral Interface SPI 4 4 Quad SPI QSPI Yes Yes General-Purpose Timers TIMER_1 to TIMER_4 4 4 General-Purpose or Watchdog Timer Dedicated to ARM TIMER_5 1 1 General-Purpose or Watchdog Timer Dedicated to DSP TIMER_0 1 1 Dedicated to PMMC Timer TIMER_6 1 1 Enhanced PWM Module ePWM 6 6 Enhanced Capture Module eCAP 2 2 8 Device Comparison Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 3-1. Device Comparison (continued) 66AK2G02 66AK2G01 Enhanced Quadrature Encoder Pulse Module FEATURES REFERENCE NAME eQEP 3 3 Universal Asynchronous Receiver and Transmitter UART 3 3 2 1(2) Universal Serial Bus (USB2.0) High Speed Dual-Role-Device USB (DRD) Ports with PHY (1) Features noted as “Not Supported,” must not be used. Their functionality is not supported by TI for this family of devices. These features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions. (2) The USB0 port is NOT supported in the 66AK2G01 device. 3.1 Related Products C6000 Multicore DSP + ARM SoC TI DSP + ARM processors include a wide range of device choices that deliver the highest performance at the lowest power levels and costs. TI DSP + ARM solutions range from single core ARM9 + C674x DSP to quad-core ARM Cortex-A15 + 8xC66x DSP cores. 66AK2x Multicore DSP + ARM Processors Companion Products for 66AKG0x/66AKG1x Review products that are frequently purchased or used in conjunction with this product. Reference Designs for 66AKG0x/66AKG1x TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Device Comparison 9 ADVANCE INFORMATION Digital Signal Processors DSPs bring computing performance, real-time processing, and power efficiency to diverse applications ranging from sensors to servers. Our product range spans high-performance real-time needs, to power-efficient processors with industry-leading lowest active power needs. Choose one of the following scalable solutions. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagram Figure 4-1 shows the ball locations for the 625 plastic ball grid array (NFBGA) package that are used in conjunction with Table 4-1 through Table 4-27 to locate signal names and ball grid numbers. ADVANCE INFORMATION Figure 4-1. ZBB NFBGA-N625 Package (Bottom View) 4.2 Pin Attributes Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. 10 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] C17 AUDOSC_IN AUDOSC_IN 0 I 0 1.8 V DVDD18 Analog A17 AUDOSC_OUT AUDOSC_OUT 0 O 0 1.8 V DVDD18 Analog N6 AVDDA_ARMPLL AVDDA_ARMPLL PWR W20 AVDDA_DDRPLL AVDDA_DDRPLL PWR N20 AVDDA_DSSPLL AVDDA_DSSPLL PWR G8 AVDDA_ICSSPLL AVDDA_ICSSPLL PWR M19 AVDDA_MAINPLL AVDDA_MAINPLL PWR G14 AVDDA_NSSPLL AVDDA_NSSPLL PWR G10 AVDDA_UARTPLL AVDDA_UARTPLL Y3 BOOTCOMPLETE BOOTCOMPLETE 0 OZ 0 3.3 V DVDD33 L21 CPTS_REFCLK_N CPTS_REFCLK_N 0 I 0 1.8 V DVDD18 LVDS K21 CPTS_REFCLK_P CPTS_REFCLK_P 0 I 0 1.8 V DVDD18 LVDS CVDD PWR J12, M5, N18, N8, T13 CVDD1 CVDD1 PWR R5 DCAN0_RX DCAN0_RX 0 I GPIO1_57 3 IOZ DCAN0_TX 0 OZ GPIO1_56 3 IOZ 0 DCAN0_TX DSIS [15] PWR J10, J14, J16, K11, CVDD K13, K15, K17, K9, L10, L12, L14, L16, L18, M11, M13, M15, M17, M9, N10, N12, N14, N16, P11, P13, P15, P17, P9, R10, R12, R14, R16, R18, R8, T11, T15, T17, T9, U16 P5 PULL UP/DOWN TYPE [14] ADVANCE INFORMATION BALL NUMBER [1] PD PD Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD 0 0 0 0 AC13 DDR3_CASn DDR3_CASn Y11 DDR3_CBDQM DDR3_CBDQM No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD12 DDR3_CBDQS_N DDR3_CBDQS_N No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE12 DDR3_CBDQS_P DDR3_CBDQS_P No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE13 DDR3_RASn DDR3_RASn 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD Y18 DDR3_RESETn DDR3_RESETn 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR LVCMOS Y9 DDR3_VREFSSTL DDR3_VREFSSTL 0 A 0 0.675 V n/a Analog Y13 DDR3_WEn DDR3_WEn 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 11 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] ADVANCE INFORMATION AC15 DDR3_A00 DDR3_A00 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD Y15 DDR3_A01 DDR3_A01 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AC16 DDR3_A02 DDR3_A02 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA15 DDR3_A03 DDR3_A03 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AB16 DDR3_A04 DDR3_A04 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AE17 DDR3_A05 DDR3_A05 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AC14 DDR3_A06 DDR3_A06 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AB15 DDR3_A07 DDR3_A07 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AC17 DDR3_A08 DDR3_A08 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AB17 DDR3_A09 DDR3_A09 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AB14 DDR3_A10 DDR3_A10 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA16 DDR3_A11 DDR3_A11 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA17 DDR3_A12 DDR3_A12 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA12 DDR3_A13 DDR3_A13 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD Y17 DDR3_A14 DDR3_A14 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD Y16 DDR3_A15 DDR3_A15 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA14 DDR3_BA0 DDR3_BA0 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AB13 DDR3_BA1 DDR3_BA1 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AD17 DDR3_BA2 DDR3_BA2 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD AA11 DDR3_CB00 DDR3_CB00 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB11 DDR3_CB01 DDR3_CB01 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC11 DDR3_CB02 DDR3_CB02 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC12 DDR3_CB03 DDR3_CB03 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD13 DDR3_CEn0 DDR3_CEn0 0 OZ OFF DRIVE 1 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD 12 Terminal Configuration and Functions DSIS [15] Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] AB18 DDR3_CKE0 DDR3_CKE0 0 OZ OFF AD15 DDR3_CLKOUT_N0 DDR3_CLKOUT_N0 0 OZ AD16 DDR3_CLKOUT_N1 DDR3_CLKOUT_N1 0 OZ AE15 DDR3_CLKOUT_P0 DDR3_CLKOUT_P0 0 AE16 DDR3_CLKOUT_P1 DDR3_CLKOUT_P1 AD2 DDR3_D00 Y4 BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] DRIVE 0 (OFF) POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] 0 1.35 V DVDD_DDR HSTL PU/PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD OZ OFF 0 1.35 V DVDD_DDR HSTL PU/PD 0 OZ OFF 0 1.35 V DVDD_DDR HSTL PU/PD DDR3_D00 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD DDR3_D01 DDR3_D01 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC3 DDR3_D02 DDR3_D02 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC2 DDR3_D03 DDR3_D03 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE3 DDR3_D04 DDR3_D04 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA4 DDR3_D05 DDR3_D05 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD3 DDR3_D06 DDR3_D06 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB3 DDR3_D07 DDR3_D07 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA6 DDR3_D08 DDR3_D08 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD Y7 DDR3_D09 DDR3_D09 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD Y6 DDR3_D10 DDR3_D10 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC5 DDR3_D11 DDR3_D11 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB6 DDR3_D12 DDR3_D12 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD Y5 DDR3_D13 DDR3_D13 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC4 DDR3_D14 DDR3_D14 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB5 DDR3_D15 DDR3_D15 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB7 DDR3_D16 DDR3_D16 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB8 DDR3_D17 DDR3_D17 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC7 DDR3_D18 DDR3_D18 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA7 DDR3_D19 DDR3_D19 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA8 DDR3_D20 DDR3_D20 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC6 DDR3_D21 DDR3_D21 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE7 DDR3_D22 DDR3_D22 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD7 DDR3_D23 DDR3_D23 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA10 DDR3_D24 DDR3_D24 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE10 DDR3_D25 DDR3_D25 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD10 DDR3_D26 DDR3_D26 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC10 DDR3_D27 DDR3_D27 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC9 DDR3_D28 DDR3_D28 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB10 DDR3_D29 DDR3_D29 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB9 DDR3_D30 DDR3_D30 No 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD DSIS [15] Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 ADVANCE INFORMATION BALL NUMBER [1] 13 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] ADVANCE INFORMATION Y8 DDR3_D31 DDR3_D31 0 IOZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AB4 DDR3_DQM0 DDR3_DQM0 0 OZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA5 DDR3_DQM1 DDR3_DQM1 0 OZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AC8 DDR3_DQM2 DDR3_DQM2 0 OZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA9 DDR3_DQM3 DDR3_DQM3 0 OZ OFF OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE2 DDR3_DQS0_N DDR3_DQS0_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD1 DDR3_DQS0_P DDR3_DQS0_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE4 DDR3_DQS1_N DDR3_DQS1_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD4 DDR3_DQS1_P DDR3_DQS1_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD6 DDR3_DQS2_N DDR3_DQS2_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE6 DDR3_DQS2_P DDR3_DQS2_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD AD9 DDR3_DQS3_N DDR3_DQS3_N 0 IOZ PU OFF 0 1.35 V DVDD_DDR HSTL PU/PD AE9 DDR3_DQS3_P DDR3_DQS3_P 0 IOZ PD OFF 0 1.35 V DVDD_DDR HSTL PU/PD AA13 DDR3_ODT0 DDR3_ODT0 0 OZ OFF DRIVE 0 (OFF) 0 1.35 V DVDD_DDR HSTL PU/PD W12 DDR3_RZQ0 DDR3_RZQ0 0 A 0 n/a n/a Analog V9 DDR3_RZQ1 DDR3_RZQ1 0 A 0 n/a n/a Analog AD24 DDR_CLK_N DDR_CLK_N 0 I 0 1.8 V DVDD18 LVDS AE24 DDR_CLK_P DDR_CLK_P 0 I 0 1.8 V DVDD18 V22 DSS_DATA0 DSS_DATA0 0 OZ 3 3.3 V DVDD33 GPMC_A1 1 OZ 0 GPIO0_53 3 IOZ 0 U21 W22 DSS_DATA1 DSS_DATA2 No PD PD LVDS Yes LVCMOS PU/PD 0 DSS_RFBI_DATA0 No 5 IOZ DSS_DATA1 No 0 OZ GPMC_A2 1 OZ 0 eQEP2_S 2 IOZ 0 GPIO0_52 3 IOZ 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 DSS_RFBI_DATA1 No 5 IOZ DSS_DATA2 No 0 OZ GPMC_A3 1 OZ 0 eQEP2_I 2 IOZ 0 GPIO0_51 3 IOZ 0 5 IOZ 0 Bootstrap I 0 DSS_RFBI_DATA2 MAINPLL_OD_SEL 14 No MUXMODE [5] No 0 OFF OFF Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) V23 U23 BALL NAME [2] DSS_DATA3 DSS_DATA4 SIGNAL NAME [3] DSS_DATA3 PN [4] No T21 U22 T22 DSS_DATA6 DSS_DATA7 DSS_DATA8 BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] 0 OZ 1 OZ 0 eQEP2_B 2 I 0 GPIO0_50 3 IOZ 0 0 DSS_RFBI_DATA3 No 5 IOZ DSS_DATA4 No 0 OZ GPMC_A5 1 OZ 0 eQEP2_A 2 I 0 GPIO0_49 3 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A6 1 OZ 0 eQEP1_S 2 IOZ 0 GPIO0_48 3 IOZ 0 No NODDR DSS_DATA5 TYPE [6] GPMC_A4 DSS_RFBI_DATA4 V24 MUXMODE [5] DSS_DATA5 No 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 DSS_RFBI_DATA5 No 5 IOZ DSS_DATA6 No 0 OZ GPMC_A7 1 OZ 0 eQEP1_I 2 IOZ 0 GPIO0_47 3 IOZ 0 EMU19 4 IOZ 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 DSS_RFBI_DATA6 No 5 IOZ DSS_DATA7 No 0 OZ GPMC_A8 1 OZ 0 eQEP1_B 2 I 0 GPIO0_46 3 IOZ 0 EMU18 4 IOZ 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 DSS_RFBI_DATA7 No 5 IOZ DSS_DATA8 No 0 OZ GPMC_A9 1 OZ 0 eQEP1_A 2 I 0 GPIO0_45 3 IOZ 0 EMU17 4 IOZ 0 5 IOZ 0 Bootstrap I 0 DSS_RFBI_DATA8 BOOTMODE15 No ADVANCE INFORMATION BALL NUMBER [1] 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 15 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] R21 BALL NAME [2] DSS_DATA9 SIGNAL NAME [3] DSS_DATA9 PN [4] ADVANCE INFORMATION DSS_DATA10 DSS_DATA11 0 0 GPIO0_44 3 IOZ 0 EMU16 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A11 1 OZ 0 eQEP0_I 2 IOZ 0 GPIO0_43 3 IOZ 0 EMU15 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A12 1 OZ 0 eQEP0_B 2 I 0 GPIO0_42 3 IOZ 0 EMU14 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A13 1 OZ 0 eQEP0_A 2 I 0 GPIO0_41 3 IOZ 0 EMU13 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A14 1 OZ 0 eHRPWM_TZn2 2 I 0 GPIO0_40 3 IOZ 0 EMU12 4 IOZ 0 5 IOZ 0 Bootstrap I 0 DSS_DATA11 DSS_RFBI_DATA11 No No BOOTMODE12 T24 DSS_DATA12 DSS_DATA12 DSS_RFBI_DATA12 No No BOOTMODE11 P21 DSS_DATA13 DSS_DATA13 DSS_RFBI_DATA13 BOOTMODE10 16 No No Yes LVCMOS DSIS [15] IOZ BOOTMODE13 DVDD33 PULL UP/DOWN TYPE [14] 2 No 3.3 V BUFFER TYPE [13] eQEP0_S No 3 HYS [12] OZ DSS_DATA10 OFF POWER [11] OZ No OFF BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] 1 DSS_RFBI_DATA10 V25 BALL RESET STATE [7] 0 BOOTMODE14 U24 TYPE [6] GPMC_A10 DSS_RFBI_DATA9 No MUXMODE [5] 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) U25 BALL NAME [2] DSS_DATA14 SIGNAL NAME [3] DSS_DATA14 PN [4] DSS_DATA15 DSS_DATA16 0 0 GPIO0_39 3 IOZ 0 EMU11 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A16 1 OZ 0 eHRPWM2_A 2 IOZ 0 GPIO0_38 3 IOZ 0 EMU10 4 IOZ 0 5 IOZ 0 Bootstrap I 0 OZ GPMC_A17 1 OZ 0 eHRPWM_TZn1 2 I 0 GPIO0_37 3 IOZ 0 EMU09 4 IOZ 0 5 OZ 0 Bootstrap I 0 OZ GPMC_A18 1 OZ 0 eHRPWM1_B 2 IOZ 0 GPIO0_36 3 IOZ 0 EMU08 4 IOZ 0 5 OZ 0 Bootstrap I 0 OZ GPMC_A19 1 OZ 0 eHRPWM1_A 2 IOZ 0 GPIO0_35 3 IOZ 0 EMU07 4 IOZ 0 5 I 0 Bootstrap I 0 DSS_DATA16 DSS_RFBI_CSn0 No No BOOTMODE07 R24 DSS_DATA17 DSS_DATA17 DSS_RFBI_CSn1 No No BOOTMODE06 N22 DSS_DATA18 DSS_DATA18 DSS_RFBI_HSYNC1 BOOTMODE05 No No Yes LVCMOS DSIS [15] IOZ BOOTMODE08 DVDD33 PULL UP/DOWN TYPE [14] 2 No 3.3 V BUFFER TYPE [13] eHRPWM2_B No 3 HYS [12] OZ DSS_DATA15 OFF POWER [11] OZ No OFF BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] 1 DSS_RFBI_DATA15 P23 BALL RESET STATE [7] 0 BOOTMODE09 R22 TYPE [6] GPMC_A15 DSS_RFBI_DATA14 No MUXMODE [5] 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS ADVANCE INFORMATION BALL NUMBER [1] 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 17 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] T25 BALL NAME [2] DSS_DATA19 SIGNAL NAME [3] DSS_DATA19 PN [4] ADVANCE INFORMATION P24 P25 N23 M25 DSS_DATA20 DSS_DATA21 DSS_DATA22 DSS_DATA23 DSS_DE 0 0 GPIO0_34 3 IOZ 0 EMU06 4 IOZ 0 5 I 0 Bootstrap I 0 OZ GPMC_A21 1 OZ 0 eHRPWM0_SYNCI 2 I 0 GPIO0_33 3 IOZ 0 EMU05 4 IOZ 0 BOOTMODE03 Bootstrap I 0 OZ GPMC_A22 1 OZ 0 eHRPWM_TZn0 2 I 0 GPIO0_32 3 IOZ 0 EMU04 4 IOZ 0 BOOTMODE02 Bootstrap I 0 OZ GPMC_A23 1 OZ 0 eHRPWM0_B 2 IOZ 0 GPIO0_31 3 IOZ 0 EMU03 4 IOZ 0 BOOTMODE01 Bootstrap I 0 OZ GPMC_A24 1 OZ 0 eHRPWM0_A 2 IOZ 0 GPIO0_30 3 IOZ 0 EMU02 4 IOZ 0 BOOTMODE00 Bootstrap I 0 OZ 1 OZ 0 2 OZ 0 3 IOZ 0 5 OZ 0 DSS_DATA22 DSS_DATA23 DSS_DE No No No PR1_EDIO_OUTVALID No GPIO0_57 DSS_RFBI_WEn No Yes LVCMOS DSIS [15] OZ No DVDD33 PULL UP/DOWN TYPE [14] 2 DSS_DATA21 3.3 V BUFFER TYPE [13] eHRPWM0_SYNCO No 3 HYS [12] OZ DSS_DATA20 OFF POWER [11] OZ No OFF BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] 1 GPMC_A0 18 BALL RESET STATE [7] 0 BOOTMODE04 N24 TYPE [6] GPMC_A20 DSS_RFBI_TEVSYNC1 No MUXMODE [5] 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 OFF OFF 3 3.3 V DVDD33 Yes LVCMOS 0 0 PD PD Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) L25 BALL NAME [2] DSS_FID SIGNAL NAME [3] PN [4] DSS_HSYNC DVDD33 Yes LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] OZ OZ 0 3 IOZ 0 0 DSS_RFBI_A0 No 5 OZ DSS_HSYNC No 0 OZ 1 OZ 0 2 I 0 3 IOZ 0 No 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 DSS_RFBI_HSYNC0 No 5 I DSS_PCLK No 0 OZ 1 OZ 0 2 OZ 0 3 IOZ 0 No GPIO0_56 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 DSS_RFBI_REn No 5 OZ DSS_VSYNC No 0 OZ GPMC_A25 1 OZ 0 PR1_eCAP0_eCAP_CAPIN_APWM_ No O 2 IOZ 0 GPIO0_54 3 IOZ 0 5 I 0 DSS_RFBI_TEVSYNC0 No DVDD18 DVDD18 PWR AA23, E23, F11, DVDD33 F15, F21, F7, G12, G16, G20, H11, H13, H15, H9, J20, P19, P7, R20, R6, T19, T23, T7, U20, V21 DVDD33 PWR G18, H17 DVDD33_USB 3.3 V BUFFER TYPE [13] 2 PR1_eCAP0_eCAP_SYNCOUT F17, F19, G6, H5, J6, K19, L20, L6, M7, U18, U6, V19, W6 3 HYS [12] 0 GPMC_A27 DSS_VSYNC PD POWER [11] No GPIO0_55 R25 PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] No PR1_eCAP0_eCAP_SYNCIN DSS_PCLK BALL RESET STATE [7] PR0_EDIO_OUTVALID GPMC_A26 N25 TYPE [6] DSS_FID GPIO0_58 P22 MUXMODE [5] DVDD33_USB PWR AD11, AD18, AD5, DVDD_DDR AE14, AE8, U10, U12, U14, U8, V11, V13, V15, V17, V7, W16, W18 DVDD_DDR PWR W10, W14, W8 DVDD_DDRDLL DVDD_DDRDLL A23 eHRPWM3_A PR0_EDIO_DATA3 ADVANCE INFORMATION BALL NUMBER [1] 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 PWR No 1 IOZ GPIO0_73 3 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 eHRPWM3_A 4 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 19 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] B22 C22 D23 BALL NAME [2] eHRPWM3_B eHRPWM3_SYNCI eHRPWM3_SYNCO SIGNAL NAME [3] PR0_EDIO_DATA2 PN [4] TYPE [6] ADVANCE INFORMATION 1 IOZ GPIO0_74 3 IOZ eHRPWM3_B 4 IOZ 1 IOZ GPIO0_75 3 IOZ eHRPWM3_SYNCI 4 I 1 IOZ GPIO0_76 3 IOZ eHRPWM3_SYNCO 4 OZ PR0_EDIO_DATA1 PR0_EDIO_DATA0 No MUXMODE [5] No No BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 IOZ PU OFF 0 3.3 V DVDD33 Yes LVCMOS PU/PD L22 EMU01 EMU01 0 IOZ PU OFF 0 3.3 V DVDD33 Yes LVCMOS PU/PD AC21 GPMC_AD0 GPMC_AD0 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_00 3 IOZ GPMC_AD1 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_01 3 IOZ GPMC_AD2 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_02 3 IOZ GPMC_AD3 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_03 3 IOZ GPMC_AD4 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_04 3 IOZ GPMC_AD5 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_05 3 IOZ GPMC_AD6 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_06 3 IOZ GPMC_AD7 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_07 3 IOZ GPMC_AD8 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_08 3 IOZ GPMC_AD9 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_09 3 IOZ GPMC_AD10 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_10 3 IOZ GPMC_AD11 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_11 3 IOZ GPMC_AD12 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_12 3 IOZ AD20 AE21 AE22 AC20 AD21 AE23 AB20 AA20 AD23 AA21 20 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5 GPMC_AD6 GPMC_AD7 GPMC_AD8 GPMC_AD9 GPMC_AD10 GPMC_AD11 GPMC_AD12 0 0 EMU00 AD22 0 0 EMU00 GPMC_AD1 0 0 M22 AE20 DSIS [15] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Terminal Configuration and Functions 0 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) AB21 AB22 AA22 AC23 AC24 AB24 AB23 AB25 W24 W23 Y25 AA25 AC22 Y24 AA24 Y22 BALL NAME [2] GPMC_AD13 GPMC_AD14 GPMC_AD15 GPMC_ADVn_ALE GPMC_BEn0_CLE GPMC_BEn1 GPMC_CLK GPMC_CSn0 GPMC_CSn1 GPMC_CSn2 GPMC_CSn3 GPMC_DIR GPMC_OEn_REn GPMC_WAIT0 GPMC_WAIT1 GPMC_WEn SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] GPMC_AD13 0 IOZ GPIO0_13 3 IOZ GPMC_AD14 0 IOZ GPIO0_14 3 IOZ GPMC_AD15 0 IOZ GPIO0_15 3 IOZ GPMC_ADVn_ALE 0 OZ GPIO0_17 3 IOZ GPMC_BEn0_CLE 0 OZ GPIO0_20 3 IOZ GPMC_BEn1 0 OZ GPIO0_21 3 IOZ GPMC_CLK 0 IOZ GPIO0_16 3 IOZ GPMC_CSn0 0 OZ GPIO0_26 3 IOZ GPMC_CSn1 0 OZ MLB_DAT 2 IOZ GPIO0_27 3 IOZ GPMC_CSn2 0 OZ TIMI1 2 I GPIO0_28 3 IOZ GPMC_CSn3 0 OZ TIMO1 2 OZ GPIO0_29 3 IOZ GPMC_DIR 0 OZ MLB_SIG 2 IOZ GPIO0_25 3 IOZ GPMC_OEn_REn 0 OZ GPIO0_18 3 IOZ GPMC_WAIT0 0 I GPIO0_22 3 IOZ GPMC_WAIT1 0 I MLB_CLK 2 I GPIO0_23 3 IOZ GPMC_WEn 0 OZ GPIO0_19 3 IOZ BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD DSIS [15] 0 0 0 0 0 0 0 ADVANCE INFORMATION BALL NUMBER [1] 0 0 0 0 0 0 0 0 0 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 0 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 21 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] W25 BALL NAME [2] GPMC_WPn SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] GPMC_WPn 0 OZ GPIO0_24 3 IOZ BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] PU PU 3 3.3 V DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] 0 0 ADVANCE INFORMATION U5 I2C0_SCL I2C0_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN W5 I2C0_SDA I2C0_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN V6 I2C1_SCL I2C1_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN W4 I2C1_SDA I2C1_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN V5 I2C2_SCL I2C2_SCL 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN V4 I2C2_SDA I2C2_SDA 0 IOD OFF OFF 0 3.3 V DVDD33 I2C OPEN DRAIN J8, L8 LDO_PCIE_CAP LDO_PCIE_CAP H19, J18 LDO_USB_CAP LDO_USB_CAP V2 LRESETn LRESETn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD V1 LRESETNMIENn LRESETNMIENn 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD U3 MDIO_CLK MDIO_CLK 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_98 3 IOZ MDIO_DATA 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_97 3 IOZ MII_COL 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_83 3 IOZ MII_CRS 0 I PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD RMII_CRS_DV 2 I GPIO0_84 3 IOZ MII_RXCLK 0 I RGMII_RXC 1 I GPIO0_72 3 IOZ MII_RXD0 0 I RGMII_RXD0 1 I 0 RMII_RXD0 2 I 0 GPIO0_80 3 IOZ MII_RXD1 0 I RGMII_RXD1 1 I 0 RMII_RXD1 2 I 0 GPIO0_79 3 IOZ 0 V3 B25 G22 A22 B24 C23 22 MDIO_DATA MII_COL MII_CRS MII_RXCLK MII_RXD0 MII_RXD1 CAP CAP 0 0 0 0 0 0 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) B23 F22 A24 F23 C25 G23 G24 G25 D25 H25 H24 BALL NAME [2] MII_RXD2 MII_RXD3 MII_RXDV MII_RXER MII_TXCLK MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_TXEN MII_TXER SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] 3 3.3 V DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] 0 I RGMII_RXD2 1 I GPIO0_78 3 IOZ MII_RXD3 0 I RGMII_RXD3 1 I GPIO0_77 3 IOZ MII_RXDV 0 I RGMII_RXCTL 1 I GPIO0_81 3 IOZ MII_RXER 0 I RMII_RXER 2 I GPIO0_82 3 IOZ MII_TXCLK 0 I RGMII_TXC 1 IOZ GPIO0_85 3 IOZ MII_TXD0 0 OZ RGMII_TXD0 1 OZ 0 RMII_TXD0 2 OZ 0 GPIO0_94 3 IOZ MII_TXD1 0 OZ RGMII_TXD1 1 OZ 0 RMII_TXD1 2 OZ 0 GPIO0_93 3 IOZ MII_TXD2 0 OZ RGMII_TXD2 1 OZ GPIO0_92 3 IOZ MII_TXD3 0 OZ RGMII_TXD3 1 OZ GPIO0_91 3 IOZ MII_TXEN 0 OZ RGMII_TXCTL 1 OZ 0 RMII_TXEN 2 OZ 0 GPIO0_95 3 IOZ MII_TXER 0 OZ 2 I 0 GPIO0_96 3 IOZ 0 eHRPWM_TZn3 4 I 0 No PD POWER [11] MII_RXD2 PR0_eCAP0_eCAP_SYNCIN PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 ADVANCE INFORMATION BALL NUMBER [1] 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 23 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] ADVANCE INFORMATION L23 MLBP_CLK_N MLBP_CLK_N 0 I 0 1.8 V DVDD18 MLB LVDS M23 MLBP_CLK_P MLBP_CLK_P 0 I 0 1.8 V DVDD18 MLB LVDS K22 MLBP_DAT_N MLBP_DAT_N 0 IO 0 1.8 V DVDD18 MLB LVDS K23 MLBP_DAT_P MLBP_DAT_P 0 IO 0 1.8 V DVDD18 MLB LVDS M24 MLBP_SIG_N MLBP_SIG_N 0 IO 0 1.8 V DVDD18 MLB LVDS L24 MLBP_SIG_P MLBP_SIG_P 0 IO 0 1.8 V DVDD18 J4 MMC1_CLK MMC1_CLK 0 IOZ GPIO0_67 3 IOZ MMC1_CMD 0 IOZ GPIO0_68 3 IOZ MMC1_POW 0 OZ GPIO0_71 3 IOZ MMC1_SDCD 0 I GPIO0_69 3 IOZ MMC1_SDWP 0 I GPIO0_70 3 IOZ MMC1_DAT0 0 IOZ GPIO0_66 3 IOZ MMC1_DAT1 0 IOZ GPIO0_65 3 IOZ MMC1_DAT2 0 IOZ GPIO0_64 3 IOZ MMC1_DAT3 0 IOZ GPIO0_63 3 IOZ MMC1_DAT4 0 IOZ GPIO0_62 3 IOZ MMC1_DAT5 0 IOZ GPIO0_61 3 IOZ MMC1_DAT6 0 IOZ GPIO0_60 3 IOZ MMC1_DAT7 0 IOZ GPIO0_59 3 IOZ J2 K2 J3 K3 H3 F5 J5 H4 E3 G4 F4 G5 MMC1_CMD MMC1_POW MMC1_SDCD MMC1_SDWP MMC1_DAT0 MMC1_DAT1 MMC1_DAT2 MMC1_DAT3 MMC1_DAT4 MMC1_DAT5 MMC1_DAT6 MMC1_DAT7 DSIS [15] MLB LVDS PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD PD PD 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 3 1.8 V DVDD18 Yes LVCMOS PU/PD PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W1 NMIn NMIn 0 I L1 OBSCLK_N OBSCLK_N 0 O 0 1.8 V DVDD18 K1 OBSCLK_P OBSCLK_P 0 O 0 1.8 V DVDD18 N5 OBSPLL_LOCK OBSPLL_LOCK 0 OZ 0 1.8 V DVDD18 24 PULL UP/DOWN TYPE [14] PD PD Terminal Configuration and Functions LVDS LVDS Yes LVCMOS PU/PD Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] F2 PCIE_CLK_N PCIE_CLK_N No 0 I 0 1.1 V DVDD18 SERDES/C ML G2 PCIE_CLK_P PCIE_CLK_P No 0 I 0 1.1 V DVDD18 SERDES/C ML H7 PCIE_REFRES PCIE_REFRES No 0 A 0 NA n/a D1 PCIE_RXN0 PCIE_RXN0 No 0 I 0 1.1 V DVDD18 SERDES/C ML E1 PCIE_RXP0 PCIE_RXP0 No 0 I 0 1.1 V DVDD18 SERDES/C ML H1 PCIE_TXN0 PCIE_TXN0 No 0 O 0 1.1 V DVDD18 SERDES/C ML G1 PCIE_TXP0 PCIE_TXP0 No 0 O 0 1.1 V DVDD18 SERDES/C ML AA3 PORn PORn 0 I 0 3.3 V DVDD33 Yes LVCMOS A10 PR0_MDIO_DATA PR0_MDIO_DATA 0 IOZ 3 3.3 V DVDD33 Yes LVCMOS GPIO1_04 3 IOZ MCASP0_AXR3 4 IOZ 0 OZ GPIO1_05 3 IOZ MCASP0_AXR4 4 IOZ 0 IOZ GPIO1_46 3 IOZ eCAP0_IN_APWM0_OUT 4 IOZ 0 OZ GPIO1_47 3 IOZ eCAP1_IN_APWM1_OUT 4 IOZ C10 E18 D18 D3 A2 E4 PR0_MDIO_MDCLK PR1_MDIO_DATA PR1_MDIO_MDCLK PR0_PRU0_GPO0 PR0_PRU0_GPO1 PR0_PRU0_GPO2 PR0_MDIO_MDCLK PR1_MDIO_DATA PR1_MDIO_MDCLK No No No No PU PU PULL UP/DOWN TYPE [14] PU/PD DSIS [15] ADVANCE INFORMATION BALL NUMBER [1] 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PR0_PRU0_GPO0 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI0 No 1 I 0 0 GPIO0_108 3 IOZ 0 MCASP2_AXR0 4 IOZ 0 PR0_PRU0_GPO1 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI1 No 1 I 0 0 GPIO0_109 3 IOZ 0 MCASP2_AXR1 4 IOZ 0 PR0_PRU0_GPO2 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI2 No 1 I 0 0 GPIO0_110 3 IOZ 0 MCASP2_AXR2 4 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 25 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] B1 A3 ADVANCE INFORMATION E5 B2 D4 E6 C2 C3 D5 26 BALL NAME [2] PR0_PRU0_GPO3 PR0_PRU0_GPO4 PR0_PRU0_GPO5 PR0_PRU0_GPO6 PR0_PRU0_GPO7 PR0_PRU0_GPO8 PR0_PRU0_GPO9 PR0_PRU0_GPO10 PR0_PRU0_GPO11 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR0_PRU0_GPO3 No 0 OZ PR0_PRU0_GPI3 No 1 I 0 0 GPIO0_111 3 IOZ 0 MCASP2_AXR3 4 IOZ 0 PR0_PRU0_GPO4 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI4 No 1 I 0 0 GPIO0_112 3 IOZ 0 MCASP2_AXR4 4 IOZ 0 PR0_PRU0_GPO5 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI5 No 1 I 0 0 GPIO0_113 3 IOZ 0 MCASP2_AXR5 4 IOZ 0 PR0_PRU0_GPO6 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI6 No 1 I 0 0 GPIO0_114 3 IOZ 0 MCASP2_ACLKR 4 IOZ 0 PR0_PRU0_GPO7 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI7 No 1 I 0 0 GPIO0_115 3 IOZ 0 MCASP2_AFSR 4 IOZ 0 PR0_PRU0_GPO8 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI8 No 1 I 0 0 GPIO0_116 3 IOZ 0 MCASP2_AHCLKR 4 IOZ 0 PR0_PRU0_GPO9 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI9 No 1 I 0 0 XREFCLK 2 I 0 GPIO0_117 3 IOZ 0 MCASP2_AMUTE 4 IOZ 0 PR0_PRU0_GPO10 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI10 No 1 I 0 0 GPIO0_118 3 IOZ 0 MCASP2_AFSX 4 IOZ 0 PR0_PRU0_GPO11 No 0 OZ PD PD PR0_PRU0_GPI11 No 1 I 0 GPIO0_119 3 IOZ 0 MCASP2_AHCLKX 4 IOZ 0 Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) B3 B4 A4 E7 D6 C4 C5 A5 BALL NAME [2] PR0_PRU0_GPO12 PR0_PRU0_GPO13 PR0_PRU0_GPO14 PR0_PRU0_GPO15 PR0_PRU0_GPO16 PR0_PRU0_GPO17 PR0_PRU0_GPO18 PR0_PRU0_GPO19 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR0_PRU0_GPO12 No 0 OZ PR0_PRU0_GPI12 No 1 I 0 0 GPIO0_120 3 IOZ 0 MCASP2_ACLKX 4 IOZ 0 PR0_PRU0_GPO13 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI13 No 1 I 0 0 GPIO0_121 3 IOZ 0 MCASP1_ACLKR 4 IOZ ADVANCE INFORMATION BALL NUMBER [1] 0 PR0_PRU0_GPO14 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI14 No 1 I 0 0 GPIO0_122 3 IOZ 0 MCASP1_AFSR 4 IOZ 0 PR0_PRU0_GPO15 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI15 No 1 I 0 0 GPIO0_123 3 IOZ 0 MCASP1_AHCLKR 4 IOZ 0 PR0_PRU0_GPO16 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI16 No 1 I 0 0 GPIO0_124 3 IOZ 0 MCASP1_ACLKX 4 IOZ 0 PR0_PRU0_GPO17 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI17 No 1 I 0 0 PR1_UART0_RXD No 2 I 0 GPIO0_125 3 IOZ 0 MCASP1_AFSX 4 IOZ 0 PR0_PRU0_GPO18 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI18 No 1 I 0 0 PR0_EDC_LATCH0_IN No 2 I 0 GPIO0_126 3 IOZ 0 MCASP1_AHCLKX 4 IOZ 0 PR0_PRU0_GPO19 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU0_GPI19 No 1 I 0 0 PR0_EDC_SYNC0_OUT No 2 OZ 0 GPIO0_127 3 IOZ 0 MCASP1_AMUTE 4 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 27 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] B5 B6 ADVANCE INFORMATION D7 A6 C6 E8 A7 D8 F9 28 BALL NAME [2] PR0_PRU1_GPO0 PR0_PRU1_GPO1 PR0_PRU1_GPO2 PR0_PRU1_GPO3 PR0_PRU1_GPO4 PR0_PRU1_GPO5 PR0_PRU1_GPO6 PR0_PRU1_GPO7 PR0_PRU1_GPO8 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR0_PRU1_GPO0 No 0 OZ PR0_PRU1_GPI0 No 1 I 0 0 GPIO0_128 3 IOZ 0 MCASP1_AXR0 4 IOZ 0 PR0_PRU1_GPO1 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI1 No 1 I 0 0 GPIO0_129 3 IOZ 0 MCASP1_AXR1 4 IOZ 0 PR0_PRU1_GPO2 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI2 No 1 I 0 0 GPIO0_130 3 IOZ 0 MCASP1_AXR2 4 IOZ 0 PR0_PRU1_GPO3 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI3 No 1 I 0 0 GPIO0_131 3 IOZ 0 MCASP1_AXR3 4 IOZ 0 PR0_PRU1_GPO4 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI4 No 1 I 0 0 GPIO0_132 3 IOZ 0 MCASP1_AXR4 4 IOZ 0 PR0_PRU1_GPO5 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI5 No 1 I 0 0 GPIO0_133 3 IOZ 0 MCASP1_AXR5 4 IOZ 0 PR0_PRU1_GPO6 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI6 No 1 I 0 0 GPIO0_134 3 IOZ 0 MCASP1_AXR6 4 IOZ 0 PR0_PRU1_GPO7 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI7 No 1 I 0 0 GPIO0_135 3 IOZ 0 MCASP1_AXR7 4 IOZ 0 PR0_PRU1_GPO8 No 0 OZ PD PD PR0_PRU1_GPI8 No 1 I 0 GPIO0_136 3 IOZ 0 MCASP1_AXR8 4 IOZ 0 Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) B7 C7 E9 A8 B8 D9 C8 C9 B9 BALL NAME [2] PR0_PRU1_GPO9 PR0_PRU1_GPO10 PR0_PRU1_GPO11 PR0_PRU1_GPO12 PR0_PRU1_GPO13 PR0_PRU1_GPO14 PR0_PRU1_GPO15 PR0_PRU1_GPO16 PR0_PRU1_GPO17 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR0_PRU1_GPO9 No 0 OZ PR0_PRU1_GPI9 No 1 I 0 0 GPIO0_137 3 IOZ 0 MCASP1_AXR9 4 IOZ 0 PR0_PRU1_GPO10 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI10 No 1 I 0 0 GPIO0_138 3 IOZ 0 MCASP0_AMUTE 4 IOZ ADVANCE INFORMATION BALL NUMBER [1] 0 PR0_PRU1_GPO11 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI11 No 1 I 0 0 GPIO0_139 3 IOZ 0 MCASP0_ACLKR 4 IOZ 0 PR0_PRU1_GPO12 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI12 No 1 I 0 0 GPIO0_140 3 IOZ 0 MCASP0_AFSR 4 IOZ 0 PR0_PRU1_GPO13 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI13 No 1 I 0 0 GPIO0_141 3 IOZ 0 MCASP0_AHCLKR 4 IOZ 0 PR0_PRU1_GPO14 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI14 No 1 I 0 0 GPIO0_142 3 IOZ 0 MCASP0_ACLKX 4 IOZ 0 PR0_PRU1_GPO15 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI15 No 1 I 0 0 GPIO0_143 3 IOZ 0 MCASP0_AFSX 4 IOZ 0 PR0_PRU1_GPO16 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI16 No 1 I 0 0 GPIO1_00 3 IOZ 0 MCASP0_AHCLKX 4 IOZ 0 PR0_PRU1_GPO17 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI17 No 1 I 0 0 PR1_UART0_TXD No 2 OZ 0 GPIO1_01 3 IOZ 0 MCASP0_AXR0 4 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 29 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] A9 B10 ADVANCE INFORMATION E10 D10 F10 C11 D11 E11 30 BALL NAME [2] PR0_PRU1_GPO18 PR0_PRU1_GPO19 PR1_PRU0_GPO0 PR1_PRU0_GPO1 PR1_PRU0_GPO2 PR1_PRU0_GPO3 PR1_PRU0_GPO4 PR1_PRU0_GPO5 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR0_PRU1_GPO18 No 0 OZ PR0_PRU1_GPI18 No 1 I 0 0 PR0_EDC_LATCH1_IN No 2 I 0 GPIO1_02 3 IOZ 0 MCASP0_AXR1 4 IOZ 0 PR0_PRU1_GPO19 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_PRU1_GPI19 No 1 I 0 0 PR0_EDC_SYNC1_OUT No 2 OZ 0 GPIO1_03 3 IOZ 0 MCASP0_AXR2 4 IOZ 0 PR1_PRU0_GPO0 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI0 No 1 I 0 0 GPIO1_06 3 IOZ 0 MCASP0_AXR5 4 IOZ 0 PR1_PRU0_GPO1 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI1 No 1 I 0 0 GPIO1_07 3 IOZ 0 MCASP0_AXR6 4 IOZ 0 PR1_PRU0_GPO2 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI2 No 1 I 0 0 GPIO1_08 3 IOZ 0 MCASP0_AXR7 4 IOZ 0 PR1_PRU0_GPO3 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI3 No 1 I 0 0 GPIO1_09 3 IOZ 0 MCASP0_AXR8 4 IOZ 0 PR1_PRU0_GPO4 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI4 No 1 I 0 0 MMC0_POW 2 OZ 0 GPIO1_10 3 IOZ 0 MCASP0_AXR9 4 IOZ 0 PR1_PRU0_GPO5 No 0 OZ PD PD PR1_PRU0_GPI5 No 1 I 0 MMC0_SDWP 2 I 0 GPIO1_11 3 IOZ 0 MCASP0_AXR10 4 IOZ 0 Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) F12 E12 C12 B11 B12 A12 A11 A13 BALL NAME [2] PR1_PRU0_GPO6 PR1_PRU0_GPO7 PR1_PRU0_GPO8 PR1_PRU0_GPO9 PR1_PRU0_GPO10 PR1_PRU0_GPO11 PR1_PRU0_GPO12 PR1_PRU0_GPO13 SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] PR1_PRU0_GPO6 No 0 OZ PR1_PRU0_GPI6 No 1 I 0 0 MMC0_SDCD 2 I 0 GPIO1_12 3 IOZ 0 MCASP0_AXR11 4 IOZ 0 PR1_PRU0_GPO7 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI7 No 1 I 0 0 MMC0_DAT7 2 IOZ 0 GPIO1_13 3 IOZ 0 MCASP0_AXR12 4 IOZ ADVANCE INFORMATION BALL NUMBER [1] 0 PR1_PRU0_GPO8 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI8 No 1 I 0 0 MMC0_DAT6 2 IOZ 0 GPIO1_14 3 IOZ 0 MCASP0_AXR13 4 IOZ 0 PR1_PRU0_GPO9 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI9 No 1 I 0 0 MMC0_DAT5 2 IOZ 0 GPIO1_15 3 IOZ 0 MCASP0_AXR14 4 IOZ 0 PR1_PRU0_GPO10 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI10 No 1 I 0 0 MMC0_DAT4 2 IOZ 0 GPIO1_16 3 IOZ 0 MCASP0_AXR15 4 IOZ 0 PR1_PRU0_GPO11 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI11 No 1 I 0 0 MMC0_DAT3 2 IOZ 0 GPIO1_17 3 IOZ 0 PR1_PRU0_GPO12 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI12 No 1 I 0 0 MMC0_DAT2 2 IOZ 0 GPIO1_18 3 IOZ 0 PR1_PRU0_GPO13 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU0_GPI13 No 1 I 0 0 MMC0_DAT1 2 IOZ 0 GPIO1_19 3 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 31 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] B13 F13 ADVANCE INFORMATION C13 E13 D12 D13 A14 BALL NAME [2] PR1_PRU0_GPO14 PR1_PRU0_GPO15 PR1_PRU0_GPO16 PR1_PRU0_GPO17 PR1_PRU0_GPO18 PR1_PRU0_GPO19 PR1_PRU1_GPO0 SIGNAL NAME [3] PN [4] PR1_PRU1_GPO1 PR1_PRU1_GPO2 PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] No 0 OZ No 1 I 0 MMC0_DAT0 2 IOZ 0 GPIO1_20 3 IOZ 0 0 PR1_PRU0_GPO15 No 0 OZ PR1_PRU0_GPI15 No 1 I 0 MMC0_CLK 2 IOZ 0 GPIO1_21 3 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PR1_PRU0_GPO16 No 0 OZ PR1_PRU0_GPI16 No 1 I 0 MMC0_CMD 2 IOZ 0 GPIO1_22 3 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PR1_PRU0_GPO17 No 0 OZ PR1_PRU0_GPI17 No 1 I 0 GPIO1_23 3 IOZ 0 eHRPWM_TZn4 4 I 0 eHRPWM_SOCA 5 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PR1_PRU0_GPO18 No 0 OZ PR1_PRU0_GPI18 No 1 I 0 PR1_EDC_LATCH0_IN No 2 I 0 GPIO1_24 3 IOZ 0 eHRPWM4_A 4 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PR1_PRU0_GPO19 No 0 OZ PR1_PRU0_GPI19 No 1 I 0 PR1_EDC_SYNC0_OUT No 2 OZ 0 GPIO1_25 3 IOZ 0 eHRPWM4_B 4 IOZ PR1_PRU1_GPO0 No 0 OZ PR1_PRU1_GPI0 No 1 I 3 IOZ PR1_PRU1_GPO1 No 0 OZ PR1_PRU1_GPI1 No 1 I 3 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PR1_PRU1_GPO2 No 0 OZ PR1_PRU1_GPI2 No 1 I 0 3 IOZ 0 GPIO1_28 32 BALL RESET STATE [7] PR1_PRU0_GPI14 GPIO1_27 C14 TYPE [6] PR1_PRU0_GPO14 GPIO1_26 B14 MUXMODE [5] PD PD Terminal Configuration and Functions 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) E14 BALL NAME [2] PR1_PRU1_GPO3 SIGNAL NAME [3] PN [4] PR1_PRU1_GPO4 No 0 OZ PR1_PRU1_GPI3 No 1 I 3 IOZ PR1_PRU1_GPO4 No 0 OZ PR1_PRU1_GPI4 No 1 I 3 IOZ GPIO1_30 A15 PR1_PRU1_GPO5 PR1_PRU1_GPO5 No 0 OZ PR1_PRU1_GPI5 No 1 I 3 IOZ GPIO1_31 F14 PR1_PRU1_GPO6 PR1_PRU1_GPO6 No 0 OZ PR1_PRU1_GPI6 No 1 I 3 IOZ GPIO1_32 B15 PR1_PRU1_GPO7 PR1_PRU1_GPO7 No 0 OZ PR1_PRU1_GPI7 No 1 I 3 IOZ GPIO1_33 C15 PR1_PRU1_GPO8 PR1_PRU1_GPO8 No 0 OZ PR1_PRU1_GPI8 No 1 I 3 IOZ GPIO1_34 D15 A16 E15 B16 PR1_PRU1_GPO9 PR1_PRU1_GPO10 PR1_PRU1_GPO11 PR1_PRU1_GPO12 TYPE [6] PR1_PRU1_GPO3 GPIO1_29 D14 MUXMODE [5] BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 ADVANCE INFORMATION BALL NUMBER [1] 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PR1_PRU1_GPO9 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI9 No 1 I 0 0 MCBSP_DR 2 I 0 GPIO1_35 3 IOZ 0 PR1_PRU1_GPO10 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI10 No 1 I 0 0 MCBSP_DX 2 OZ 0 GPIO1_36 3 IOZ 0 PR1_PRU1_GPO11 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI11 No 1 I 0 0 MCBSP_FSX 2 IOZ 0 GPIO1_37 3 IOZ 0 PR1_PRU1_GPO12 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI12 No 1 I 0 0 MCBSP_CLKX 2 IOZ 0 GPIO1_38 3 IOZ 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 33 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] C16 D17 ADVANCE INFORMATION C18 BALL NAME [2] PR1_PRU1_GPO13 PR1_PRU1_GPO14 PR1_PRU1_GPO15 SIGNAL NAME [3] PN [4] PR1_PRU1_GPO16 E17 E16 K25 J25 H23 34 PR1_PRU1_GPO17 PR1_PRU1_GPO18 PR1_PRU1_GPO19 QSPI_CLK QSPI_CSn0 QSPI_CSn1 BALL RESET STATE [7] PD BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD 3 3.3 V POWER [11] DVDD33 HYS [12] Yes BUFFER TYPE [13] LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] No 0 OZ PR1_PRU1_GPI13 No 1 I 0 MCBSP_FSR 2 IOZ 0 GPIO1_39 3 IOZ 0 0 PR1_PRU1_GPO14 No 0 OZ PR1_PRU1_GPI14 No 1 I 0 MCBSP_CLKR 2 IOZ 0 GPIO1_40 3 IOZ PR1_PRU1_GPO15 No 0 OZ PR1_PRU1_GPI15 No 1 I 3 IOZ PR1_PRU1_GPO16 No 0 OZ PR1_PRU1_GPI16 No 1 I 3 IOZ GPIO1_42 F16 TYPE [6] PR1_PRU1_GPO13 GPIO1_41 D16 MUXMODE [5] PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PR1_PRU1_GPO17 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI17 No 1 I 0 0 GPIO1_43 3 IOZ 0 eHRPWM_TZn5 4 I 0 eHRPWM_SOCB 5 OZ 0 PR1_PRU1_GPO18 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI18 No 1 I 0 0 PR1_EDC_LATCH1_IN No 2 I 0 GPIO1_44 3 IOZ 0 eHRPWM5_A 4 IOZ 0 PR1_PRU1_GPO19 No 0 OZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR1_PRU1_GPI19 No 1 I 0 0 PR1_EDC_SYNC1_OUT No 2 OZ 0 GPIO1_45 3 IOZ 0 eHRPWM5_B 4 IOZ QSPI_CLK 0 OZ GPIO1_58 3 IOZ QSPI_CSn0 0 OZ GPIO1_64 3 IOZ QSPI_CSn1 0 OZ CLKOUT 1 OZ 0 GPIO1_65 3 IOZ 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 0 Terminal Configuration and Functions 0 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) H22 BALL NAME [2] QSPI_CSn2 SIGNAL NAME [3] PN [4] J22 J21 J24 K24 QSPI_D0 QSPI_D1 QSPI_D2 QSPI_D3 QSPI_RCLK DVDD33 Yes LVCMOS PULL UP/DOWN TYPE [14] PU/PD DSIS [15] 0 2 I 0 3 IOZ 0 4 I QSPI_CSn3 0 OZ DCAN1_RX 1 I 1 2 OZ 1 GPIO1_67 3 IOZ 1 USB1_EXT_TRIGGER 4 I QSPI_D0 0 IOZ GPIO1_60 3 IOZ QSPI_D1 0 IOZ GPIO1_61 3 IOZ QSPI_D2 0 IOZ GPIO1_62 3 IOZ QSPI_D3 0 IOZ GPIO1_63 3 IOZ QSPI_RCLK 0 I GPIO1_59 3 IOZ No 3.3 V BUFFER TYPE [13] OZ PR1_UART0_RTSN 3 HYS [12] OZ No PU POWER [11] 1 No PU BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] 0 USB0_EXT_TRIGGER J23 BALL RESET STATE [7] DCAN1_TX GPIO1_66 QSPI_CSn3 TYPE [6] QSPI_CSn2 PR1_UART0_CTSN H21 MUXMODE [5] 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD PU/PD 0 0 0 0 0 0 0 0 0 0 RESETFULLn RESETFULLn 0 I PU W3 RESETn RESETn 0 I PU 0 3.3 V DVDD33 Yes LVCMOS Y2 RESETSTATn RESETSTATn 0 O DRIVE 0 (OFF) DRIVE 0 (OFF) 0 3.3 V DVDD33 Yes LVCMOS D24 RMII_REFCLK RMII_REFCLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 2 OZ No 1 1 PD W2 PR0_eCAP0_eCAP_SYNCOUT 0 0 0 M2 SPI0_CLK SPI0_CLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 N4 SPI0_SIMO SPI0_SIMO 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 M1 SPI0_SOMI SPI0_SOMI 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 N2 SPI1_CLK SPI1_CLK 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 P2 SPI1_SIMO SPI1_SIMO 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 N1 SPI1_SOMI SPI1_SOMI 0 IOZ PD PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 R2 SPI2_CLK SPI2_CLK 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 GPIO0_103 3 IOZ SPI2_SIMO 0 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_105 3 IOZ R3 SPI2_SIMO ADVANCE INFORMATION BALL NUMBER [1] 0 0 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 35 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] R4 E24 BALL NAME [2] SPI2_SOMI SPI3_CLK SIGNAL NAME [3] SPI3_SIMO ADVANCE INFORMATION SPI3_SOMI TYPE [6] 0 IOZ GPIO0_104 3 IOZ SPI3_CLK 1 IOZ 2 OZ GPIO0_88 3 IOZ SPI3_SIMO 1 IOZ 2 OZ GPIO0_90 3 IOZ SPI3_SOMI 1 IOZ 2 I GPIO0_89 3 IOZ PR0_UART0_RTSN F25 MUXMODE [5] SPI2_SOMI PR0_UART0_TXD F24 PN [4] PR0_UART0_CTSN No No No BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD DSIS [15] 0 0 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 M3 SPI0_SCSn0 SPI0_SCSn0 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 1 M4 SPI0_SCSn1 SPI0_SCSn1 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 GPIO0_99 3 IOZ 0 P1 SPI1_SCSn0 SPI1_SCSn0 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 1 N3 SPI1_SCSn1 SPI1_SCSn1 0 IOZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 GPIO0_100 3 IOZ SPI2_SCSn0 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_101 3 IOZ SPI2_SCSn1 0 IOZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO0_102 3 IOZ SPI3_SCSn0 1 IOZ PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD PR0_eCAP0_eCAP_CAPIN_APWM_ No O 2 IOZ GPIO0_86 3 IOZ SPI3_SCSn1 1 IOZ 2 I GPIO0_87 3 IOZ P3 P4 C24 E25 SPI2_SCSn0 SPI2_SCSn1 SPI3_SCSn0 SPI3_SCSn1 PR0_UART0_RXD No M21 SYSCLKOUT SYSCLKOUT 0 OZ R1 SYSCLKSEL SYSCLKSEL 0 AC25 SYSCLK_N SYSCLK_N 0 AD25 SYSCLK_P SYSCLK_P AC19 SYSOSC_IN AE19 0 0 0 0 1 1 1 PD PD 3 3.3 V DVDD33 Yes LVCMOS PU/PD 1 1 1 0 3.3 V DVDD33 Yes LVCMOS I 0 3.3 V DVDD33 Yes LVCMOS I 0 1.8 V DVDD18 LVDS 0 I 0 1.8 V DVDD18 LVDS SYSOSC_IN 0 I 0 1.8 V DVDD18 Analog SYSOSC_OUT SYSOSC_OUT 0 O 0 1.8 V DVDD18 L3 TCK TCK 0 I PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD L5 TDI TDI 0 I PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD K5 TDO TDO 0 OZ PU 0 3.3 V DVDD33 LVCMOS PU/PD 36 0 PD PD OFF Terminal Configuration and Functions PU/PD Analog Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] K4 TMS TMS 0 I PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD L4 TRSTn TRSTn 0 I PD 0 3.3 V DVDD33 Yes LVCMOS PU/PD T2 UART0_CTSn UART0_CTSn 0 I PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD TIMI0 1 I GPIO0_106 3 IOZ UART0_RTSn 0 OZ TIMO0 1 OZ GPIO0_107 3 IOZ U1 UART0_RTSn PU DSIS [15] 0 0 0 PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 0 T4 UART0_RXD UART0_RXD 0 I PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD T1 UART0_TXD UART0_TXD 0 OZ PU PU 0 3.3 V DVDD33 Yes LVCMOS PU/PD U2 UART1_CTSn UART1_CTSn 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO1_50 3 IOZ UART1_RTSn 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO1_51 3 IOZ UART1_RXD 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO1_48 3 IOZ UART1_TXD 0 OZ PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD GPIO1_49 3 IOZ UART2_CTSn 0 I PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 1 IOZ 0 UART0_DTRn 2 OZ 0 GPIO1_54 3 IOZ 0 CPTS_TS_SYNC 4 OZ UART2_RTSn 0 OZ 1 IOZ 0 UART0_RIN 2 I 0 GPIO1_55 3 IOZ 0 CPTS_TS_COMP 4 OZ UART2_RXD 0 I 1 IOZ 0 UART0_DCDn 2 I 0 GPIO1_52 3 IOZ 0 CPTS_HW1_TSPUSH 4 I 0 U4 T3 T5 D22 UART1_RTSn UART1_RXD UART1_TXD UART2_CTSn PR1_EDIO_DATA1 C21 UART2_RTSn PR1_EDIO_DATA0 E21 UART2_RXD PR1_EDIO_DATA3 No No No ADVANCE INFORMATION BALL NUMBER [1] 1 0 0 0 0 0 0 0 0 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 0 PU PU 3 3.3 V DVDD33 Yes LVCMOS PU/PD 0 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 37 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] D21 BALL NAME [2] UART2_TXD SIGNAL NAME [3] PN [4] UART2_TXD MUXMODE [5] TYPE [6] BALL RESET STATE [7] 0 2 I 0 GPIO1_53 3 IOZ 0 CPTS_HW2_TSPUSH 4 I ADVANCE INFORMATION No 0 IO A18 USB0_DP USB0_DP No 0 IO E19 USB0_DRVVBUS USB0_DRVVBUS No 0 OZ A19 USB0_ID USB0_ID No 0 C19 USB0_TXRTUNE_RKELVIN USB0_TXRTUNE_RKELVIN No B19 USB0_VBUS USB0_VBUS No D19 USB0_XO USB0_XO No A20 USB1_DM B20 Yes LVCMOS 0 0 0 3.3 V DVDD33_USB 0 3.3 V DVDD33_USB 0 3.3 V DVDD33_USB A 0 3.3 V DVDD33_USB USB0_PHY 0 A 0 n/a USB0_PHY 0 A 0 5.25 V n/a USB0_PHY 0 I 0 1.8 V USB0 USB0_PHY USB1_DM 0 IO 0 3.3 V DVDD33_USB USB1_PHY USB1_DP USB1_DP 0 IO 0 3.3 V DVDD33_USB B21 USB1_DRVVBUS USB1_DRVVBUS 0 OZ 0 3.3 V DVDD33_USB E20 USB1_ID USB1_ID 0 A 0 3.3 V DVDD33_USB USB1_PHY D20 USB1_TXRTUNE_RKELVIN USB1_TXRTUNE_RKELVIN 0 A 0 n/a USB1_PHY A21 USB1_VBUS USB1_VBUS 0 A 0 5.25 V n/a USB1_PHY C20 USB1_XO USB1_XO 0 I 0 1.8 V DVDD18 USB1_PHY K7 VDDAHV VDDAHV PWR Y21 VPP VPP PWR W21 VPP2 VPP2 PWR 38 PU/PD DSIS [15] UART0_DSRn USB0_DM DVDD33 PULL UP/DOWN TYPE [14] IOZ USB0_DM 3.3 V BUFFER TYPE [13] OZ B18 3 HYS [12] 1 No PU POWER [11] 0 PR1_EDIO_DATA2 PU BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] PD PD PD PD Terminal Configuration and Functions USB0_PHY USB0_PHY Yes LVCMOS PU/PD USB1_PHY Yes LVCMOS PU/PD Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-1. Pin Attributes (continued) BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] A1, A25, AD14, VSS AD8, AE1, AE11, AE18, AE25, AE5, C1, E2, E22, F1, F20, F3, F6, F8, G11, G13, G15, G17, G19, G21, G7, G9, H10, H12, H14, H16, H18, H20, H6, H8, J1, J11, J13, J15, J17, J19, J7, J9, K10, K12, K14, K16, K18, K20, K6, K8, L11, L13, L15, L17, L19, L7, L9, M10, M12, M14, M16, M18, M20, M6, M8, N11, N13, N15, N17, N19, N21, N7, N9, P10, P12, P14, P16, P18, P20, P6, P8, R11, R13, R15, R17, R19, R23, R7, R9, T10, T12, T14, T16, T18, T20, T6, T8, U11, U13, U15, U17, U19, U7, U9, V10, V12, V14, V16, V18, V20, V8, W11, W13, W15, W17, W7, W9, Y10, Y23 VSS GND B17 VSS_OSC_AUDIO VSS_OSC_AUDIO GND AD19 VSS_OSC_SYS VSS_OSC_SYS GND BALL RESET STATE [7] BALL BALL I/O RESET RESET VOLTAGE REL. REL. VALUE MUXMODE STATE [8] [10] [9] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] ADVANCE INFORMATION BALL NUMBER [1] Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 39 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com The following list describes the table column headers: 1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom. 2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0). 3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0). NOTE Table 4-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions. ADVANCE INFORMATION 4. PN: This column shows if the functionality is applicable for 66AK2G01 device. Note that the ball characteristics table presents a functionality of super set. If the cell is empty it means that the signal is available in all devices. – Yes – Functionality is presented in 66AK2G01 – No – Functionality not presented in 66AK2G01 An empty box means Yes. 5. MUXMODE: Multiplexing mode number: (a) MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode. NOTE The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column. (b) MUXMODE 1 through 5 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used. (c) Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These are not programable MUXMODE. (d) An empty box means Not Applicable. 6. TYPE: Signal type and direction: – I = Input – O = Output – IO = Input or Output – IOD = Open drain terminal - Input or Output – IOZ = Input, Output or Three-state terminal – OZ = Output or Three-state terminal – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor. 7. BALL RESET STATE: The state of the terminal at power-on reset: – DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated). – DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable. 8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal. – DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated). – DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated). 40 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 DRIVE CLK (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated). OFF: High-impedance PD: High-impedance with an active pulldown resistor PU: High-impedance with an active pullup resistor An empty box means Not Applicable. For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see chapter Device Configuration of the device TRM. 9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal. An empty box means Not Applicable. 10. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply). An empty box means Not Applicable. 11. POWER: The voltage supply that powers the terminal IO buffers. An empty box means Not Applicable. 12. HYS: Indicates if the input buffer has hysteresis: – Yes: With hysteresis – No: Without hysteresis An empty box means No. For more information, see the hysteresis values in Section 5.7, Electrical Characteristics. 13. BUFFER TYPE: This column describes the associated output buffer type An empty box means Not Applicable. For drive strength of the associated output buffer, refer to Section 5.7, Electrical Characteristics. 14. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. – PU: Internal pullup – PD: Internal pulldown – PU/PD: Internal pullup and pulldown – An empty box means No pull. 15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the input signal port of the peripheral. – 1: Logic 1 driven on the input signal port of the peripheral. – An empty box means Not Applicable. NOTE Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (HiZ mode is not an input signal). NOTE When a pad is set into a multiplexing mode that is not defined by pin multiplexing, behavior of that pad is undefined, which must be avoided. 4.3 Signal Descriptions Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 41 ADVANCE INFORMATION – – – – – 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com The following list describes the column headers: 1. SIGNAL NAME: The name of the signal passing through the pin. NOTE In Table 4-1 and Table 4-28 are not described the subsystem multiplexing signals. ADVANCE INFORMATION 2. DESCRIPTION: Description of the signal 3. PIN TYPE: Signal direction and type: – I = Input – O = Output – IO = Input or Output – IOD = Open drain terminal - Input or Output – IOZ = Input, Output or Three-state terminal – OZ = Output or Three-state terminal – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor 4. ZBB BALL: Associated balls bottom For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. 4.3.1 DSS Table 4-2. DSS Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] V22 DSS_DATA0 DSS Data output OZ DSS_DATA1 DSS Data output OZ U21 DSS_DATA2 DSS Data output OZ W22 DSS_DATA3 DSS Data output OZ V23 DSS_DATA4 DSS Data output OZ U23 DSS_DATA5 DSS Data output OZ V24 DSS_DATA6 DSS Data output OZ T21 DSS_DATA7 DSS Data output OZ U22 DSS_DATA8 DSS Data output OZ T22 DSS_DATA9 DSS Data output OZ R21 DSS_DATA10 DSS Data output OZ U24 DSS_DATA11 DSS Data output OZ V25 DSS_DATA12 DSS Data output OZ T24 DSS_DATA13 DSS Data output OZ P21 DSS_DATA14 DSS Data output OZ U25 DSS_DATA15 DSS Data output OZ R22 DSS_DATA16 DSS Data output OZ P23 DSS_DATA17 DSS Data output OZ R24 DSS_DATA18 DSS Data output OZ N22 DSS_DATA19 DSS Data output OZ T25 DSS_DATA20 DSS Data output OZ N24 DSS_DATA21 DSS Data output OZ P24 DSS_DATA22 DSS Data output OZ P25 42 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-2. DSS Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] DSS_DATA23 DSS Data output OZ N23 DSS_DE DSS Data Enable output OZ M25 DSS_FID DSS Field ID output. This signal is not used for embedded sync modes OZ L25 DSS_HSYNC DSS Horizontal Sync output. This signal is not used for embedded sync modes OZ P22 DSS_PCLK DSS Clock output OZ N25 DSS_VSYNC DSS Vertical Sync output. This signal is not used for embedded sync modes OZ R25 DSS_RFBI_A0 RFBI A0 Indicate the status of the data: command or data (Polarity is programmable) OZ L25 DSS_RFBI_CSn0 RFBI LCD chip select 0 (Polarity is programmable) OZ P23 DSS_RFBI_CSn1 RFBI LCD chip select 1 (Polarity is programmable) OZ R24 DSS_RFBI_DATA0 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ V22 DSS_RFBI_DATA1 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ U21 DSS_RFBI_DATA2 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ W22 DSS_RFBI_DATA3 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ V23 DSS_RFBI_DATA4 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ U23 DSS_RFBI_DATA5 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ V24 DSS_RFBI_DATA6 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ T21 DSS_RFBI_DATA7 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ U22 DSS_RFBI_DATA8 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ T22 DSS_RFBI_DATA9 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ R21 DSS_RFBI_DATA10 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ U24 DSS_RFBI_DATA11 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ V25 DSS_RFBI_DATA12 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ T24 DSS_RFBI_DATA13 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ P21 DSS_RFBI_DATA14 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ U25 DSS_RFBI_DATA15 RFBI Data Read/Write to LCD panel Clock reference: Asynchronous IOZ R22 DSS_RFBI_HSYNC0 RFBI Horizontal synchronization input 0 HSYNC pulse signals Clock reference: Asynchronous I P22 DSS_RFBI_HSYNC1 RFBI Horizontal synchronization input 1 HSYNC pulse signals Clock reference: Asynchronous I N22 DSS_RFBI_REn RFBI Read Enable (Polarity is programmable) Indicate when a read is on going from the embedded emory in the LCD panel clock reference. OZ N25 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION DSS RFBI Mode 43 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-2. DSS Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] DSS_RFBI_TEVSYNC0 RFBI Vertical synchronization input 0 TE (Tearing Effect) pulse signal or the LCD panel VSYNC (Vertical Synchronization) Clock reference: Asynchronous I R25 DSS_RFBI_TEVSYNC1 RFBI Vertical synchronization input 1 TE (Tearing Effect) pulse signal or the LCD panel VSYNC (Vertical Synchronization) Clock reference: Asynchronous I T25 DSS_RFBI_WEn RFBI LCD write enable (Polarity is programmable) OZ M25 4.3.2 DDR EMIF Table 4-3. DDR External Memory Interface Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION DDR3_A00 EMIF Address Bit 00 output OZ AC15 DDR3_A01 EMIF Address Bit 01 output OZ Y15 DDR3_A02 EMIF Address Bit 02 output OZ AC16 DDR3_A03 EMIF Address Bit 03 output OZ AA15 DDR3_A04 EMIF Address Bit 04 output OZ AB16 DDR3_A05 EMIF Address Bit 05 output OZ AE17 DDR3_A06 EMIF Address Bit 06 output OZ AC14 DDR3_A07 EMIF Address Bit 07 output OZ AB15 DDR3_A08 EMIF Address Bit 08 output OZ AC17 DDR3_A09 EMIF Address Bit 09 output OZ AB17 DDR3_A10 EMIF Address Bit 10 output OZ AB14 DDR3_A11 EMIF Address Bit 11 output OZ AA16 DDR3_A12 EMIF Address Bit 12 output OZ AA17 DDR3_A13 EMIF Address Bit 13 output OZ AA12 DDR3_A14 EMIF Address Bit 14 output OZ Y17 DDR3_A15 EMIF Address Bit 15 output OZ Y16 DDR3_BA0 EMIF Bank Address 0 output OZ AA14 DDR3_BA1 EMIF Bank Address 1 output OZ AB13 DDR3_BA2 EMIF Bank Address 2 output OZ AD17 DDR3_CASn EMIF Column Address Strobe output OZ AC13 DDR3_CB00 EMIF ECC Check Bit 00 input/output IOZ AA11 DDR3_CB01 EMIF ECC Check Bit 01 input/output IOZ AB11 DDR3_CB02 EMIF ECC Check Bit 02 input/output IOZ AC11 DDR3_CB03 EMIF ECC Check Bit 03 input/output IOZ AC12 DDR3_CBDQM EMIF ECC Check Bit Data Mask IOZ Y11 DDR3_CBDQS_N EMIF ECC Check Bit Data Strobe input/output (negative) IOZ AD12 DDR3_CBDQS_P EMIF ECC Check Bit Data Strobe input/output (positive) IOZ AE12 DDR3_CEn0 EMIF Chip Enable 0 output (Active Low) OZ AD13 DDR3_CKE0 EMIF Clock Enable 0 output OZ AB18 DDR3_CLKOUT_N0 EMIF Differential Clock 0 output (negative) OZ AD15 DDR3_CLKOUT_P0 EMIF Differential Clock 0 output (positive) OZ AE15 DDR3_CLKOUT_N1 EMIF Differential Clock 1 output (negative) OZ AD16 DDR3_CLKOUT_P1 EMIF Differential Clock 1 output (positive) OZ AE16 DDR3_D00 EMIF Data Bit 00 input/output IOZ AD2 DDR3_D01 EMIF Data Bit 01 input/output IOZ Y4 44 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] DDR3_D02 EMIF Data Bit 02 input/output IOZ AC3 DDR3_D03 EMIF Data Bit 03 input/output IOZ AC2 DDR3_D04 EMIF Data Bit 04 input/output IOZ AE3 DDR3_D05 EMIF Data Bit 05 input/output IOZ AA4 DDR3_D06 EMIF Data Bit 06 input/output IOZ AD3 DDR3_D07 EMIF Data Bit 07 input/output IOZ AB3 DDR3_D08 EMIF Data Bit 08 input/output IOZ AA6 DDR3_D09 EMIF Data Bit 09 input/output IOZ Y7 DDR3_D10 EMIF Data Bit 10 input/output IOZ Y6 DDR3_D11 EMIF Data Bit 11 input/output IOZ AC5 DDR3_D12 EMIF Data Bit 12 input/output IOZ AB6 DDR3_D13 EMIF Data Bit 13 input/output IOZ Y5 DDR3_D14 EMIF Data Bit 14 input/output IOZ AC4 DDR3_D15 EMIF Data Bit 15 input/output IOZ AB5 DDR3_D16 EMIF Data Bit 16 input/output IOZ AB7 DDR3_D17 EMIF Data Bit 17 input/output IOZ AB8 DDR3_D18 EMIF Data Bit 18 input/output IOZ AC7 DDR3_D19 EMIF Data Bit 19 input/output IOZ AA7 DDR3_D20 EMIF Data Bit 20 input/output IOZ AA8 DDR3_D21 EMIF Data Bit 21 input/output IOZ AC6 DDR3_D22 EMIF Data Bit 22 input/output IOZ AE7 DDR3_D23 EMIF Data Bit 23 input/output IOZ AD7 DDR3_D24 EMIF Data Bit 24 input/output IOZ AA10 DDR3_D25 EMIF Data Bit 25 input/output IOZ AE10 DDR3_D26 EMIF Data Bit 26 input/output IOZ AD10 DDR3_D27 EMIF Data Bit 27 input/output IOZ AC10 DDR3_D28 EMIF Data Bit 28 input/output IOZ AC9 DDR3_D29 EMIF Data Bit 29 input/output IOZ AB10 DDR3_D30 EMIF Data Bit 30 input/output IOZ AB9 DDR3_D31 EMIF Data Bit 31 input/output IOZ Y8 DDR3_DQM0 EMIF Data Mask 0 output for byte 0 of the 32-bit data bus OZ AB4 DDR3_DQM1 EMIF Data Mask 1 output for byte 1 of the 32-bit data bus OZ AA5 DDR3_DQM2 EMIF Data Mask 2 output for byte 2 of the 32-bit data bus OZ AC8 DDR3_DQM3 EMIF Data Mask 3 output for byte 3 of the 32-bit data bus OZ AA9 DDR3_DQS0_N EMIF Differential Data strobe 0 negative input/output for byte 0 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AE2 DDR3_DQS0_P EMIF Differential Data strobe 0 positive input/output for byte 0 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AD1 DDR3_DQS1_N EMIF Differential Data strobe 1 negative input/output for byte 1 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AE4 DDR3_DQS1_P EMIF Differential Data strobe 1 positive input/output for byte 1 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AD4 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION Table 4-3. DDR External Memory Interface Signal Descriptions (continued) 45 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-3. DDR External Memory Interface Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION DDR3_DQS2_N EMIF Differential Data strobe 2 negative input/output for byte 2 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AD6 DDR3_DQS2_P EMIF Differential Data strobe 2 positive input/output for byte 2 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AE6 DDR3_DQS3_N EMIF Differential Data strobe 3 negative input/output for byte 3 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AD9 DDR3_DQS3_P EMIF Differential Data strobe 3 positive input/output for byte 3 of the 32-bit data bus. This signal is a output to the DDR3L memory when writing and a input when reading. IOZ AE9 DDR3_ODT0 EMIF On-Die Termination output for Chip Select 0 OZ AA13 DDR3_RASn EMIF Row Address Strobe output OZ AE13 DDR3_RESETn EMIF Reset output (DDR3L-SDRAM only) OZ Y18 DDR3_RZQ0 EMIF calibration resistor. An external 240Ω ±1% resistor must be connected between this pin and VSS. A W12 DDR3_RZQ1 EMIF calibration resistor. An external 240Ω ±1% resistor must be connected between this pin and VSS. A V9 DDR3_WEn EMIF Write Enable output OZ Y13 DDR_CLK_N EMIF DPLL Differential Reference Clock Input (Negative) I AD24 DDR_CLK_P EMIF DPLL Differential Reference Clock Input (Positive) I AE24 For more information, see section DDR Extrenal Memory Interface (EMIF) in chapter Memory Subsystem of the device TRM. 4.3.3 GPMC Table 4-4. GPMC Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] GPMC_A0 GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories. OZ M25 GPMC_A1 GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode OZ V22 GPMC_A2 GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode OZ U21 GPMC_A3 GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode OZ W22 GPMC_A4 GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode OZ V23 GPMC_A5 GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode OZ U23 GPMC_A6 GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode OZ V24 GPMC_A7 GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode OZ T21 GPMC_A8 GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode OZ U22 GPMC_A9 GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode OZ T22 GPMC_A10 GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode OZ R21 46 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] GPMC_A11 GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ U24 GPMC_A12 GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ V25 GPMC_A13 GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ T24 GPMC_A14 GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ P21 GPMC_A15 GPMC address 15 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ U25 GPMC_A16 GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ R22 GPMC_A17 GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ P23 GPMC_A18 GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ R24 GPMC_A19 GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ N22 GPMC_A20 GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ T25 GPMC_A21 GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ N24 GPMC_A22 GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ P24 GPMC_A23 GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ P25 GPMC_A24 GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ N23 GPMC_A25 GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ R25 GPMC_A26 GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode OZ P22 GPMC_A27 GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode OZ N25 GPMC_AD0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IOZ AC21 GPMC_AD1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IOZ AE20 GPMC_AD2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IOZ AD22 GPMC_AD3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IOZ AD20 GPMC_AD4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode IOZ AE21 GPMC_AD5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode IOZ AE22 GPMC_AD6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode IOZ AC20 GPMC_AD7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode IOZ AD21 GPMC_AD8 GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode IOZ AE23 GPMC_AD9 GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode IOZ AB20 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION Table 4-4. GPMC Signal Descriptions (continued) 47 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-4. GPMC Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION GPMC_AD10 GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode IOZ AA20 GPMC_AD11 GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode IOZ AD23 GPMC_AD12 GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode IOZ AA21 GPMC_AD13 GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode IOZ AB21 GPMC_AD14 GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode IOZ AB22 GPMC_AD15 GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode IOZ AA22 GPMC_ADVn_ALE GPMC address valid active low or address latch enable OZ AC23 GPMC_BEn1 GPMC upper-byte enable (Active Low) OZ AB24 GPMC_BEn0_CLE GPMC lower-byte enable (Active Low) OZ AC24 GPMC_CLK(1) GPMC Clock output IOZ AB23 GPMC_CSn0 GPMC Chip Select 0 (Active Low) OZ AB25 GPMC_CSn1 GPMC Chip Select 1 (Active Low) OZ W24 GPMC_CSn2 GPMC Chip Select 2 (Active Low) OZ W23 GPMC_CSn3 GPMC Chip Select 3 (Active Low) OZ Y25 GPMC_DIR GPMC direction OZ AA25 GPMC_OEn_REn GPMC output enable (Active Low) or read enable OZ AC22 GPMC_WAIT0 GPMC external indication of wait 0 I Y24 GPMC_WAIT1 GPMC external indication of wait 1 I AA24 GPMC_WEn GPMC write enable (Active Low) OZ Y22 GPMC_WPn GPMC flash write protect (Active Low) OZ W25 (1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock input. For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory Subsystem of the device TRM. 4.3.4 Timers Table 4-5. Timer Signal Descriptions SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] TIMI0 Timer Input for TIMERS [4:0] I T2 TIMI1 Timer Input for TIMERS [4:0] I W23 TIMO0 Timer Output for TIMERS [4:0] OZ U1 TIMO1 Timer Output for TIMERS [4:0] OZ Y25 For more information, see section Timers in chapter Peripherals of the device TRM. 4.3.5 I2C Table 4-6. I2C Signal Descriptions SIGNAL NAME [1] I2C0_SCL 48 Terminal Configuration and Functions DESCRIPTION [2] I2C0 Clock I/O PIN TYPE [3] ZBB BALL [4] IOD U5 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-6. I2C Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] W5 I2C0_SDA I2C0 Data I/O IOD I2C1_SCL I2C1 Clock I/O IOD V6 I2C1_SDA I2C1 Data I/O IOD W4 I2C2_SCL I2C2 Clock I/O IOD V5 I2C2_SDA I2C2 Data I/O IOD V4 For more information, see section Inter-IC module (I2C) in chapter Peripherals of the device TRM. 4.3.6 UART Table 4-7. UART Signal Descriptions DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] UART0_CTSn UART0 Clear to Send (Active Low) I T2 UART0_DCDn UART0 Data Carrier Detect (Active Low) I E21 UART0_DSRn UART0 Data Set Ready (Active Low) UART0_DTRn UART0 Data Terminal Ready (Active Low) UART0_RIN UART0 Ring Indicator Input UART0_RTSn UART0 Request to Send (Active Low) UART0_RXD UART0 Receive Data Input UART0_TXD UART0 Transmit Data Output UART1_CTSn UART1 Clear to Send (Active Low) UART1_RTSn UART1 Request to Send (Active Low) UART1_RXD UART1 Receive Data Input UART1_TXD UART1 Transmit Data Output UART2_CTSn UART2 Clear to Send (Active Low) UART2_RTSn UART2 Request to Send (Active Low) UART2_RXD UART2 Receive Data Input for UART Mode UART2_TXD UART2 Transmit Data Output I D21 OZ D22 I C21 OZ U1 I T4 OZ T1 I U2 OZ U4 I T3 OZ T5 I D22 OZ C21 I E21 OZ D21 For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the device TRM. 4.3.7 SPI Table 4-8. SPI Signal Descriptions SIGNAL NAME [1] SPI0_CLK (1) DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] SPI Clock I/O IOZ M2 SPI0_SCSn0 SPI Chip Select I/O (Active Low) IOZ M3 SPI0_SCSn1 SPI Chip Select I/O (Active Low) IOZ M4 SPI0_SIMO SPI Data Output IOZ N4 SPI0_SOMI SPI Data Input IOZ M1 SPI1_CLK (1) SPI Clock I/O IOZ N2 SPI1_SCSn0 SPI Chip Select I/O (Active Low) IOZ P1 SPI1_SCSn1 SPI Chip Select I/O (Active Low) IOZ N3 SPI1_SIMO SPI Data Output IOZ P2 SPI1_SOMI SPI Data Input IOZ N1 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 49 ADVANCE INFORMATION SIGNAL NAME [1] 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-8. SPI Signal Descriptions (continued) SIGNAL NAME [1] SPI2_CLK DESCRIPTION [2] (1) PIN TYPE [3] ZBB BALL [4] SPI Clock I/O IOZ R2 SPI2_SCSn0 SPI Chip Select I/O (Active Low) IOZ P3 SPI2_SCSn1 SPI Chip Select I/O (Active Low) IOZ P4 SPI2_SIMO SPI Data Output IOZ R3 SPI2_SOMI SPI Data Input IOZ R4 SPI Clock I/O IOZ E24 SPI3_SCSn0 SPI Chip Select I/O (Active Low) IOZ C24 SPI3_SCSn1 SPI Chip Select I/O (Active Low) IOZ E25 SPI3_SIMO SPI Data Output IOZ F24 SPI3_SOMI SPI Data Input IOZ F25 SPI3_CLK (1) (1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock input. ADVANCE INFORMATION For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the device TRM. 4.3.8 QSPI Table 4-9. QSPI Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] QSPI_CLK QSPI Serial Clock Output OZ K25 QSPI_CSn0 QSPI Chip Select 0 (Active Low). This pin is used for QSPI boot modes. OZ J25 QSPI_CSn1 QSPI Chip Select 1 (Active Low) OZ H23 QSPI_CSn2 QSPI Chip Select 2 (Active Low) OZ H22 QSPI_CSn3 QSPI Chip Select 3 (Active Low) OZ H21 QSPI_D0 QSPI Data 0. This pin is output data for all commands and writes. For dual read and quad read modes, it becomes input data pin during read phase. IOZ J23 QSPI_D1 QSPI Data 1. Input read data in all modes. IOZ J22 QSPI_D2 QSPI Data 2. This pin is used only in quad read mode as input data pin during read phase. IOZ J21 QSPI_D3 QSPI Data 3. This pin is used only in quad read mode as input data pin during read phase. IOZ J24 QSPI_RCLK QSPI Return Clock Input. Must be connected from QSPI_SCLK on PCB. Refer to PCB Guidelines for QSPI. I K24 For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the device TRM. 4.3.9 McASP Table 4-10. McASP Signal Descriptions SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] MCASP0_ACLKR(1) McASP0 Receive Bit Clock I/O IOZ E9 MCASP0_ACLKX(1) McASP0 Transmit Bit Clock I/O IOZ D9 MCASP0_AFSR McASP0 Receive Frame Sync I/O IOZ A8 MCASP0_AFSX McASP0 Transmit Frame Sync I/O IOZ C8 50 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-10. McASP Signal Descriptions (continued) PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] MCASP0_AHCLKR McASP0 Receive High-Frequency Master Clock I/O IOZ B8 MCASP0_AHCLKX McASP0 Transmit High-Frequency Master Clock Output OZ C9 MCASP0_AMUTE McASP0 Mute IOZ C7 MCASP0_AXR0 McASP0 Transmit and Receive Data I/O IOZ B9 MCASP0_AXR1 McASP0 Transmit and Receive Data I/O IOZ A9 MCASP0_AXR2 McASP0 Transmit and Receive Data I/O IOZ B10 MCASP0_AXR3 McASP0 Transmit and Receive Data I/O IOZ A10 MCASP0_AXR4 McASP0 Transmit and Receive Data I/O IOZ C10 MCASP0_AXR5 McASP0 Transmit and Receive Data I/O IOZ E10 MCASP0_AXR6 McASP0 Transmit and Receive Data I/O IOZ D10 MCASP0_AXR7 McASP0 Transmit and Receive Data I/O IOZ F10 MCASP0_AXR8 McASP0 Transmit and Receive Data I/O IOZ C11 MCASP0_AXR9 McASP0 Transmit and Receive Data I/O IOZ D11 MCASP0_AXR10 McASP0 Transmit and Receive Data I/O IOZ E11 MCASP0_AXR11 McASP0 Transmit and Receive Data I/O IOZ F12 MCASP0_AXR12 McASP0 Transmit and Receive Data I/O IOZ E12 MCASP0_AXR13 McASP0 Transmit and Receive Data I/O IOZ C12 MCASP0_AXR14 McASP0 Transmit and Receive Data I/O IOZ B11 MCASP0_AXR15 McASP0 Transmit and Receive Data I/O IOZ B12 MCASP1_ACLKR(1) McASP1 Receive Bit Clock I/O IOZ B4 D6 MCASP1_ACLKX (1) McASP1 Transmit Bit Clock I/O IOZ MCASP1_AFSR McASP1 Receive Frame Sync I/O IOZ A4 MCASP1_AFSX McASP1 Transmit Frame Sync I/O IOZ C4 MCASP1_AHCLKR McASP1 Receive High-Frequency Master Clock I/O IOZ E7 MCASP1_AHCLKX McASP1 Transmit High-Frequency Master Clock Output OZ C5 MCASP1_AMUTE McASP1 Mute IOZ A5 MCASP1_AXR0 McASP1 Transmit and Receive Data I/O IOZ B5 MCASP1_AXR1 McASP1 Transmit and Receive Data I/O IOZ B6 MCASP1_AXR2 McASP1 Transmit and Receive Data I/O IOZ D7 MCASP1_AXR3 McASP1 Transmit and Receive Data I/O IOZ A6 MCASP1_AXR4 McASP1 Transmit and Receive Data I/O IOZ C6 MCASP1_AXR5 McASP1 Transmit and Receive Data I/O IOZ E8 MCASP1_AXR6 McASP1 Transmit and Receive Data I/O IOZ A7 MCASP1_AXR7 McASP1 Transmit and Receive Data I/O IOZ D8 MCASP1_AXR8 McASP1 Transmit and Receive Data I/O IOZ F9 MCASP1_AXR9 McASP1 Transmit and Receive Data I/O IOZ B7 McASP2 Receive Bit Clock I/O IOZ B2 MCASP2_ACLKR(1) MCASP2_ACLKX (1) McASP2 Transmit Bit Clock I/O IOZ B3 MCASP2_AFSR McASP2 Receive Frame Sync I/O IOZ D4 MCASP2_AFSX McASP2 Transmit Frame Sync I/O IOZ C3 MCASP2_AHCLKR McASP2 Receive High-Frequency Master Clock I/O IOZ E6 MCASP2_AHCLKX McASP2 Transmit High-Frequency Master Clock Output OZ D5 MCASP2_AMUTE McASP2 Mute IOZ C2 MCASP2_AXR0 McASP2 Transmit and Receive Data I/O IOZ D3 MCASP2_AXR1 McASP2 Transmit and Receive Data I/O IOZ A2 MCASP2_AXR2 McASP2 Transmit and Receive Data I/O IOZ E4 MCASP2_AXR3 McASP2 Transmit and Receive Data I/O IOZ B1 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION SIGNAL NAME [1] 51 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-10. McASP Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] MCASP2_AXR4 McASP2 Transmit and Receive Data I/O IOZ A3 MCASP2_AXR5 McASP2 Transmit and Receive Data I/O IOZ E5 (1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock input. For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the device TRM. ADVANCE INFORMATION 52 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 4.3.10 USB SIGNAL NAME [1] USB0_DM(1) DESCRIPTION [2] USB0 USB2.0 differential signal pair (negative) (1) PIN TYPE [3] ZBB BALL [4] IO B18 A18 USB0_DP USB0 USB2.0 differential signal pair (positive) IO USB0_DRVVBUS(1) USB0 Drive VBUS signal OZ E19 USB0_EXT_TRIGGER(1) USB0 USB2.0 External trigger Input I H22 USB0_ID(1) USB0 USB2.0 operational mode determination input A A19 USB0_TXRTUNE_RKELVIN(1) USB0 USB2.0 Transmitter Kelvin Connection to Resistor Tune Pin (200Ω ±1%) A C19 USB0_VBUS(1) 5-V USB0 VBUS comparator input A B19 USB0_XO USB0 USB2.0 Crystal Oscillator XO Pin or Board Clock Reference Input I D19 USB1_DM USB1 USB2.0 differential signal pair (negative) IO A20 USB1_DP USB1 USB2.0 differential signal pair (positive) IO B20 USB1_DRVVBUS USB1 Drive VBUS signal OZ B21 USB1_EXT_TRIGGER USB1 USB2.0 External trigger Input I H21 USB1_ID USB1 USB2.0 operational mode determination input A E20 USB1_TXRTUNE_RKELVIN USB1 USB2.0 Transmitter Kelvin Connection to Resistor Tune Pin (200Ω ±1%) A D20 USB1_VBUS 5-V USB1 VBUS comparator input A A21 USB1_XO USB1 USB2.0 Crystal Oscillator XO Pin or Board Clock Reference Input I C20 (1) (1) The USB0 port is NOT supported in the 66AK2G01 device. For more details on the device differentiation, refer to Table 3-1, Device Comparison. For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the device TRM. 4.3.11 PCIESS Table 4-12. PCIESS Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] I F2 PCIE_CLK_N PCIe Clock Input (negative) PCIE_CLK_P PCIe Clock Input (positive) I G2 PCIE_REFRES PCIe SerDes Reference Resistor input (3kΩ ±1%) A H7 PCIE_RXN0 PCIe Receive Data Lane 0 (negative) I D1 PCIE_RXP0 PCIe Receive Data Lane 0 (positive) I E1 PCIE_TXN0 PCIe Transmit Data Lane 0 (negative) O H1 PCIE_TXP0 PCIe Transmit Data Lane 0 (positive) O G1 For more information, see section Peripheral Component Interconnect Express Subsystem (PCIe SS) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 53 ADVANCE INFORMATION Table 4-11. USB Signal Descriptions 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 4.3.12 DCAN Table 4-13. DCAN Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] R5 DCAN0_RX DCAN0 receive data pin I DCAN0_TX DCAN0 transmit data pin OZ P5 DCAN1_RX DCAN1 receive data pin I H21 DCAN1_TX DCAN1 transmit data pin OZ H22 For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals of the device TRM. 4.3.13 EMAC Table 4-14. EMAC Signal Descriptions ADVANCE INFORMATION SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] CPTS_HW1_TSPUSH CPTS Hardware Time Stamp Push Input 1 I E21 CPTS_HW2_TSPUSH CPTS Hardware Time Stamp Push Input 2 I D21 CPTS_TS_COMP CPTS Time Stamp Counter Compare Output OZ C21 CPTS_TS_SYNC CPTS Time Stamp Counter Bit Output OZ D22 MDIO_CLK MDIO Clock OZ U3 MDIO_DATA MDIO Data IOZ V3 MII_COL MII Collision Detect (Sense) Input I B25 MII_CRS MII Carrier Sense Input I G22 MII_RXCLK MII Receive Clock I A22 MII_RXD0 MII Receive Data 0 I B24 MII_RXD1 MII Receive Data 1 I C23 MII_RXD2 MII Receive Data 2 I B23 MII_RXD3 MII Receive Data 3 I F22 MII_RXDV MII Receive Data Valid Input I A24 MII_RXER MII Receive Data Error Input I F23 MII_TXCLK MII Transmit Clock I C25 MII_TXD0 MII Transmit Data 0 OZ G23 MII_TXD1 MII Transmit Data 1 OZ G24 MII_TXD2 MII Transmit Data 2 OZ G25 MII_TXD3 MII Transmit Data 3 OZ D25 MII_TXEN MII Transmit Data Enable Output OZ H25 MII_TXER MII Transmit Data Error Output OZ H24 RGMII_RXC RGMII Receive Clock I A22 RGMII_RXCTL RGMII Receive Control I A24 RGMII_RXD0 RGMII Receive Data I B24 RGMII_RXD1 RGMII Receive Data I C23 RGMII_RXD2 RGMII Receive Data I B23 RGMII_RXD3 RGMII Receive Data I F22 RGMII_TXC RGMII Transmit Clock IOZ C25 RGMII_TXCTL RGMII Transmit Enable OZ H25 RGMII_TXD0 RGMII Transmit Data OZ G23 RGMII_TXD1 RGMII Transmit Data OZ G24 54 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-14. EMAC Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] G25 RGMII_TXD2 RGMII Transmit Data OZ RGMII_TXD3 RGMII Transmit Data OZ D25 RMII_CRS_DV RMII Carrier Sense Input I G22 RMII_REFCLK(1) 50-MHz RMII clock. Typically sourced from the CLKOUT pin I D24 RMII_RXD0 RMII Receive Data I B24 RMII_RXD1 RMII Receive Data I C23 RMII_RXER RMII Receive Data Error Input I F23 RMII_TXD0 RMII Transmit Data OZ G23 RMII_TXD1 RMII Transmit Data OZ G24 RMII_TXEN RMII Transmit Data Enable Output OZ H25 For more information, see section Networking Subsystem (NSS), Gigabit Ethernet MAC (EMAC) Subsystem in chapter Peripherals of the device TRM. 4.3.14 MLB Table 4-15. MLB Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] MLBP_CLK_N Media Local Bus Subsystem (MLB) clock input differential pair (negative) I L23 MLBP_CLK_P Media Local Bus Subsystem (MLB) clock input differential pair (positive) I M23 MLBP_DAT_N Media Local Bus Subsystem (MLB) data input and output differential pair (negative) IO K22 MLBP_DAT_P Media Local Bus Subsystem (MLB) data input and output differential pair (positive) IO K23 MLBP_SIG_N Media Local Bus Subsystem (MLB) signal input and output differential pair (negative) IO M24 MLBP_SIG_P Media Local Bus Subsystem (MLB) signal input and output differential pair (positive) IO L24 MLB_CLK Media Local Bus Subsystem (MLB) clock input I AA24 MLB_DAT Media Local Bus Subsystem (MLB) data input and output IOZ W24 MLB_SIG Media Local Bus Subsystem (MLB) signal input and output IOZ AA25 For more information, see section Media Local Bus (MLB) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 55 ADVANCE INFORMATION (1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as close as possible to device pin) to improve signal integrity of the clock input. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 4.3.15 McBSP Table 4-16. McBSP Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] D17 MCBSP_CLKR McBSP received serial clock IOZ MCBSP_CLKX McBSP transmitted serial clock IOZ B16 MCBSP_DR McBSP received serial data I D15 MCBSP_DX McBSP transmitted serial data OZ A16 MCBSP_FSR McBSP received frame synchronization IOZ C16 MCBSP_FSX McBSP transmitted frame synchronization IOZ E15 For more information, see section Multi-channel Buffered Serial Port (McBSP) in chapter Peripherals of the device TRM. 4.3.16 MMC/SD ADVANCE INFORMATION Table 4-17. MMC/SD Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] MMC0_CLK(1) MMC0 clock IOZ F13 MMC0_CMD MMC0 command IOZ C13 MMC0_DAT0 MMC0 data bit 0 IOZ B13 MMC0_DAT1 MMC0 data bit 1 IOZ A13 MMC0_DAT2 MMC0 data bit 2 IOZ A11 MMC0_DAT3 MMC0 data bit 3 IOZ A12 MMC0_DAT4 MMC0 data bit 4 IOZ B12 MMC0_DAT5 MMC0 data bit 5 IOZ B11 MMC0_DAT6 MMC0 data bit 6 IOZ C12 MMC0_DAT7 MMC0 data bit 7 IOZ E12 MMC0_POW MMC/SD cards on/off power supply control OZ D11 MMC0_SDCD MMC0 Card Detect I F12 MMC0_SDWP MMC0 Write Protect I E11 MMC1_CLK(1) MMC1 clock IOZ J4 MMC1_CMD MMC1 command IOZ J2 MMC1_DAT0 MMC1 data bit 0 IOZ H3 MMC1_DAT1 MMC1 data bit 1 IOZ F5 MMC1_DAT2 MMC1 data bit 2 IOZ J5 MMC1_DAT3 MMC1 data bit 3 IOZ H4 MMC1_DAT4 MMC1 data bit 4 IOZ E3 MMC1_DAT5 MMC1 data bit 5 IOZ G4 MMC1_DAT6 MMC1 data bit 6 IOZ F4 MMC1_DAT7 MMC1 data bit 7 IOZ G5 MMC1_POW MMC/SD cards on/off power supply control OZ K2 MMC1_SDCD MMC1 Card Detect I J3 MMC1_SDWP MMC1 Write Protect I K3 (1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is required (as closeas possible to device pin) to improve signal integrity of the clock input. For more information, see section Multimedia Card High Speed Interface (MMCHS) in chapter Peripherals of the device TRM. 56 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 4.3.17 GPIO SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] AC21 GPIO0_00 General-Purpose Input/Output IOZ GPIO0_01 General-Purpose Input/Output IOZ AE20 GPIO0_02 General-Purpose Input/Output IOZ AD22 GPIO0_03 General-Purpose Input/Output IOZ AD20 GPIO0_04 General-Purpose Input/Output IOZ AE21 GPIO0_05 General-Purpose Input/Output IOZ AE22 GPIO0_06 General-Purpose Input/Output IOZ AC20 GPIO0_07 General-Purpose Input/Output IOZ AD21 GPIO0_08 General-Purpose Input/Output IOZ AE23 GPIO0_09 General-Purpose Input/Output IOZ AB20 GPIO0_10 General-Purpose Input/Output IOZ AA20 GPIO0_11 General-Purpose Input/Output IOZ AD23 GPIO0_12 General-Purpose Input/Output IOZ AA21 GPIO0_13 General-Purpose Input/Output IOZ AB21 GPIO0_14 General-Purpose Input/Output IOZ AB22 GPIO0_15 General-Purpose Input/Output IOZ AA22 GPIO0_16 General-Purpose Input/Output IOZ AB23 GPIO0_17 General-Purpose Input/Output IOZ AC23 GPIO0_18 General-Purpose Input/Output IOZ AC22 GPIO0_19 General-Purpose Input/Output IOZ Y22 GPIO0_100 General-Purpose Input/Output IOZ N3 GPIO0_101 General-Purpose Input/Output IOZ P3 GPIO0_102 General-Purpose Input/Output IOZ P4 GPIO0_103 General-Purpose Input/Output IOZ R2 GPIO0_104 General-Purpose Input/Output IOZ R4 GPIO0_105 General-Purpose Input/Output IOZ R3 GPIO0_106 General-Purpose Input/Output IOZ T2 GPIO0_107 General-Purpose Input/Output IOZ U1 GPIO0_108 General-Purpose Input/Output IOZ D3 GPIO0_109 General-Purpose Input/Output IOZ A2 GPIO0_110 General-Purpose Input/Output IOZ E4 GPIO0_111 General-Purpose Input/Output IOZ B1 GPIO0_112 General-Purpose Input/Output IOZ A3 GPIO0_113 General-Purpose Input/Output IOZ E5 GPIO0_114 General-Purpose Input/Output IOZ B2 GPIO0_115 General-Purpose Input/Output IOZ D4 GPIO0_116 General-Purpose Input/Output IOZ E6 GPIO0_117 General-Purpose Input/Output IOZ C2 GPIO0_118 General-Purpose Input/Output IOZ C3 GPIO0_119 General-Purpose Input/Output IOZ D5 GPIO0_120 General-Purpose Input/Output IOZ B3 GPIO0_121 General-Purpose Input/Output IOZ B4 GPIO0_122 General-Purpose Input/Output IOZ A4 GPIO0_123 General-Purpose Input/Output IOZ E7 GPIO0_124 General-Purpose Input/Output IOZ D6 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION Table 4-18. GPIO Signal Descriptions 57 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-18. GPIO Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION GPIO0_125 General-Purpose Input/Output IOZ C4 GPIO0_126 General-Purpose Input/Output IOZ C5 GPIO0_127 General-Purpose Input/Output IOZ A5 GPIO0_128 General-Purpose Input/Output IOZ B5 GPIO0_129 General-Purpose Input/Output IOZ B6 GPIO0_130 General-Purpose Input/Output IOZ D7 GPIO0_131 General-Purpose Input/Output IOZ A6 GPIO0_132 General-Purpose Input/Output IOZ C6 GPIO0_133 General-Purpose Input/Output IOZ E8 GPIO0_134 General-Purpose Input/Output IOZ A7 GPIO0_135 General-Purpose Input/Output IOZ D8 GPIO0_136 General-Purpose Input/Output IOZ F9 GPIO0_137 General-Purpose Input/Output IOZ B7 GPIO0_138 General-Purpose Input/Output IOZ C7 GPIO0_139 General-Purpose Input/Output IOZ E9 GPIO0_140 General-Purpose Input/Output IOZ A8 GPIO0_141 General-Purpose Input/Output IOZ B8 GPIO0_142 General-Purpose Input/Output IOZ D9 GPIO0_143 General-Purpose Input/Output IOZ C8 GPIO0_20 General-Purpose Input/Output IOZ AC24 GPIO0_21 General-Purpose Input/Output IOZ AB24 GPIO0_22 General-Purpose Input/Output IOZ Y24 GPIO0_23 General-Purpose Input/Output IOZ AA24 GPIO0_24 General-Purpose Input/Output IOZ W25 GPIO0_25 General-Purpose Input/Output IOZ AA25 GPIO0_26 General-Purpose Input/Output IOZ AB25 GPIO0_27 General-Purpose Input/Output IOZ W24 GPIO0_28 General-Purpose Input/Output IOZ W23 GPIO0_29 General-Purpose Input/Output IOZ Y25 GPIO0_30 General-Purpose Input/Output IOZ N23 GPIO0_31 General-Purpose Input/Output IOZ P25 GPIO0_32 General-Purpose Input/Output IOZ P24 GPIO0_33 General-Purpose Input/Output IOZ N24 GPIO0_34 General-Purpose Input/Output IOZ T25 GPIO0_35 General-Purpose Input/Output IOZ N22 GPIO0_36 General-Purpose Input/Output IOZ R24 GPIO0_37 General-Purpose Input/Output IOZ P23 GPIO0_38 General-Purpose Input/Output IOZ R22 GPIO0_39 General-Purpose Input/Output IOZ U25 GPIO0_40 General-Purpose Input/Output IOZ P21 GPIO0_41 General-Purpose Input/Output IOZ T24 GPIO0_42 General-Purpose Input/Output IOZ V25 GPIO0_43 General-Purpose Input/Output IOZ U24 GPIO0_44 General-Purpose Input/Output IOZ R21 GPIO0_45 General-Purpose Input/Output IOZ T22 GPIO0_46 General-Purpose Input/Output IOZ U22 GPIO0_47 General-Purpose Input/Output IOZ T21 58 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-18. GPIO Signal Descriptions (continued) DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] GPIO0_48 General-Purpose Input/Output IOZ V24 GPIO0_49 General-Purpose Input/Output IOZ U23 GPIO0_50 General-Purpose Input/Output IOZ V23 GPIO0_51 General-Purpose Input/Output IOZ W22 GPIO0_52 General-Purpose Input/Output IOZ U21 GPIO0_53 General-Purpose Input/Output IOZ V22 GPIO0_54 General-Purpose Input/Output IOZ R25 GPIO0_55 General-Purpose Input/Output IOZ P22 GPIO0_56 General-Purpose Input/Output IOZ N25 GPIO0_57 General-Purpose Input/Output IOZ M25 GPIO0_58 General-Purpose Input/Output IOZ L25 GPIO0_59 General-Purpose Input/Output IOZ G5 GPIO0_60 General-Purpose Input/Output IOZ F4 GPIO0_61 General-Purpose Input/Output IOZ G4 GPIO0_62 General-Purpose Input/Output IOZ E3 GPIO0_63 General-Purpose Input/Output IOZ H4 GPIO0_64 General-Purpose Input/Output IOZ J5 GPIO0_65 General-Purpose Input/Output IOZ F5 GPIO0_66 General-Purpose Input/Output IOZ H3 GPIO0_67 General-Purpose Input/Output IOZ J4 GPIO0_68 General-Purpose Input/Output IOZ J2 GPIO0_69 General-Purpose Input/Output IOZ J3 GPIO0_70 General-Purpose Input/Output IOZ K3 GPIO0_71 General-Purpose Input/Output IOZ K2 GPIO0_72 General-Purpose Input/Output IOZ A22 GPIO0_73 General-Purpose Input/Output IOZ A23 GPIO0_74 General-Purpose Input/Output IOZ B22 GPIO0_75 General-Purpose Input/Output IOZ C22 GPIO0_76 General-Purpose Input/Output IOZ D23 GPIO0_77 General-Purpose Input/Output IOZ F22 GPIO0_78 General-Purpose Input/Output IOZ B23 GPIO0_79 General-Purpose Input/Output IOZ C23 GPIO0_80 General-Purpose Input/Output IOZ B24 GPIO0_81 General-Purpose Input/Output IOZ A24 GPIO0_82 General-Purpose Input/Output IOZ F23 GPIO0_83 General-Purpose Input/Output IOZ B25 GPIO0_84 General-Purpose Input/Output IOZ G22 GPIO0_85 General-Purpose Input/Output IOZ C25 GPIO0_86 General-Purpose Input/Output IOZ C24 GPIO0_87 General-Purpose Input/Output IOZ E25 GPIO0_88 General-Purpose Input/Output IOZ E24 GPIO0_89 General-Purpose Input/Output IOZ F25 GPIO0_90 General-Purpose Input/Output IOZ F24 GPIO0_91 General-Purpose Input/Output IOZ D25 GPIO0_92 General-Purpose Input/Output IOZ G25 GPIO0_93 General-Purpose Input/Output IOZ G24 GPIO0_94 General-Purpose Input/Output IOZ G23 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION SIGNAL NAME [1] 59 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-18. GPIO Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION GPIO0_95 General-Purpose Input/Output IOZ H25 GPIO0_96 General-Purpose Input/Output IOZ H24 GPIO0_97 General-Purpose Input/Output IOZ V3 GPIO0_98 General-Purpose Input/Output IOZ U3 GPIO0_99 General-Purpose Input/Output IOZ M4 GPIO1_00 General-Purpose Input/Output IOZ C9 GPIO1_01 General-Purpose Input/Output IOZ B9 GPIO1_02 General-Purpose Input/Output IOZ A9 GPIO1_03 General-Purpose Input/Output IOZ B10 GPIO1_04 General-Purpose Input/Output IOZ A10 GPIO1_05 General-Purpose Input/Output IOZ C10 GPIO1_06 General-Purpose Input/Output IOZ E10 GPIO1_07 General-Purpose Input/Output IOZ D10 GPIO1_08 General-Purpose Input/Output IOZ F10 GPIO1_09 General-Purpose Input/Output IOZ C11 GPIO1_10 General-Purpose Input/Output IOZ D11 GPIO1_11 General-Purpose Input/Output IOZ E11 GPIO1_12 General-Purpose Input/Output IOZ F12 GPIO1_13 General-Purpose Input/Output IOZ E12 GPIO1_14 General-Purpose Input/Output IOZ C12 GPIO1_15 General-Purpose Input/Output IOZ B11 GPIO1_16 General-Purpose Input/Output IOZ B12 GPIO1_17 General-Purpose Input/Output IOZ A12 GPIO1_18 General-Purpose Input/Output IOZ A11 GPIO1_19 General-Purpose Input/Output IOZ A13 GPIO1_20 General-Purpose Input/Output IOZ B13 GPIO1_21 General-Purpose Input/Output IOZ F13 GPIO1_22 General-Purpose Input/Output IOZ C13 GPIO1_23 General-Purpose Input/Output IOZ E13 GPIO1_24 General-Purpose Input/Output IOZ D12 GPIO1_25 General-Purpose Input/Output IOZ D13 GPIO1_26 General-Purpose Input/Output IOZ A14 GPIO1_27 General-Purpose Input/Output IOZ B14 GPIO1_28 General-Purpose Input/Output IOZ C14 GPIO1_29 General-Purpose Input/Output IOZ E14 GPIO1_30 General-Purpose Input/Output IOZ D14 GPIO1_31 General-Purpose Input/Output IOZ A15 GPIO1_32 General-Purpose Input/Output IOZ F14 GPIO1_33 General-Purpose Input/Output IOZ B15 GPIO1_34 General-Purpose Input/Output IOZ C15 GPIO1_35 General-Purpose Input/Output IOZ D15 GPIO1_36 General-Purpose Input/Output IOZ A16 GPIO1_37 General-Purpose Input/Output IOZ E15 GPIO1_38 General-Purpose Input/Output IOZ B16 GPIO1_39 General-Purpose Input/Output IOZ C16 GPIO1_40 General-Purpose Input/Output IOZ D17 GPIO1_41 General-Purpose Input/Output IOZ C18 60 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] D16 GPIO1_42 General-Purpose Input/Output IOZ GPIO1_43 General-Purpose Input/Output IOZ F16 GPIO1_44 General-Purpose Input/Output IOZ E17 GPIO1_45 General-Purpose Input/Output IOZ E16 GPIO1_46 General-Purpose Input/Output IOZ E18 GPIO1_47 General-Purpose Input/Output IOZ D18 GPIO1_48 General-Purpose Input/Output IOZ T3 GPIO1_49 General-Purpose Input/Output IOZ T5 GPIO1_50 General-Purpose Input/Output IOZ U2 GPIO1_51 General-Purpose Input/Output IOZ U4 GPIO1_52 General-Purpose Input/Output IOZ E21 GPIO1_53 General-Purpose Input/Output IOZ D21 GPIO1_54 General-Purpose Input/Output IOZ D22 GPIO1_55 General-Purpose Input/Output IOZ C21 GPIO1_56 General-Purpose Input/Output IOZ P5 GPIO1_57 General-Purpose Input/Output IOZ R5 GPIO1_58 General-Purpose Input/Output IOZ K25 GPIO1_59 General-Purpose Input/Output IOZ K24 GPIO1_60 General-Purpose Input/Output IOZ J23 GPIO1_61 General-Purpose Input/Output IOZ J22 GPIO1_62 General-Purpose Input/Output IOZ J21 GPIO1_63 General-Purpose Input/Output IOZ J24 GPIO1_64 General-Purpose Input/Output IOZ J25 GPIO1_65 General-Purpose Input/Output IOZ H23 GPIO1_66 General-Purpose Input/Output IOZ H22 GPIO1_67 General-Purpose Input/Output IOZ H21 For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 61 ADVANCE INFORMATION Table 4-18. GPIO Signal Descriptions (continued) 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 4.3.18 ePWM Table 4-19. ePWM Signal Descriptions SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] ADVANCE INFORMATION eCAP0_IN_APWM0_OUT eCAP0 Capture Input and PWM Output IOZ E18 eCAP1_IN_APWM1_OUT eCAP1 Capture Input and PWM Output IOZ D18 eHRPWM0_A eHRPWM0 Output A IOZ N23 eHRPWM0_B eHRPWM0 Output B IOZ P25 eHRPWM0_SYNCI eHRPWM0 Sync Input I N24 eHRPWM0_SYNCO eHRPWM0 Sync Output OZ T25 eHRPWM1_A eHRPWM1 Output A IOZ N22 eHRPWM1_B eHRPWM1 Output B IOZ R24 eHRPWM2_A eHRPWM2 Output A IOZ R22 eHRPWM2_B eHRPWM2 Output B IOZ U25 eHRPWM3_A eHRPWM3 Output A IOZ A23 eHRPWM3_B eHRPWM3 Output B IOZ B22 eHRPWM3_SYNCI eHRPWM3 Sync Input I C22 eHRPWM3_SYNCO eHRPWM3 Sync Output OZ D23 eHRPWM4_A eHRPWM4 Output A IOZ D12 eHRPWM4_B eHRPWM4 Output B IOZ D13 eHRPWM5_A eHRPWM5 Output A IOZ E17 eHRPWM5_B eHRPWM5 Output B IOZ E16 eHRPWM_SOCA ePWM ADC Output A OZ E13 eHRPWM_SOCB ePWM ADC Output B OZ F16 eHRPWM_TZn0 eHRPWM0 Trip Zone Input (Active Low) I P24 eHRPWM_TZn1 eHRPWM1 Trip Zone Input (Active Low) I P23 eHRPWM_TZn2 eHRPWM2 Trip Zone Input (Active Low) I P21 eHRPWM_TZn3 eHRPWM3 Trip Zone Input (Active Low) I H24 eHRPWM_TZn4 eHRPWM4 Trip Zone Input (Active Low) I E13 eHRPWM_TZn5 eHRPWM5 Trip Zone Input (Active Low) I F16 eQEP0_A eQEP0 Quadrature Input A I T24 eQEP0_B eQEP0 Quadrature Input B I V25 eQEP0_I eQEP0 Index Input / Output IOZ U24 eQEP0_S eQEP0 Strobe Input / Output IOZ R21 eQEP1_A eQEP1 Quadrature Input A I T22 eQEP1_B eQEP1 Quadrature Input B I U22 eQEP1_I eQEP1 Index Input / Output IOZ T21 eQEP1_S eQEP1 Strobe Input / Output IOZ V24 eQEP2_A eQEP2 Quadrature Input A I U23 eQEP2_B eQEP2 Quadrature Input B I V23 eQEP2_I eQEP2 Index Input / Output IOZ W22 eQEP2_S eQEP2 Strobe Input / Output IOZ U21 62 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 For more information, see section Enhanced PWM (ePWM) Module in chapter Peripherals of the device TRM. 4.3.19 PRU-ICSS SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] IOZ C24 I H24 OZ D24 PR0_eCAP0_eCAP_CAPIN_APWM_O Capture Input and PWM Output PR0_eCAP0_eCAP_SYNCIN Capture Sync Input PR0_eCAP0_eCAP_SYNCOUT Capture Sync Output PR0_EDC_LATCH0_IN Latch Input 0 I C5 PR0_EDC_LATCH1_IN Latch Input 1 I A9 PR0_EDC_SYNC0_OUT SYNC 0 Output OZ A5 PR0_EDC_SYNC1_OUT SYNC 1 Output OZ B10 PR0_EDIO_DATA0 Digital Input IOZ D23 PR0_EDIO_DATA1 Digital Input IOZ C22 PR0_EDIO_DATA2 Digital Input IOZ B22 PR0_EDIO_DATA3 Digital Input IOZ A23 PR0_EDIO_OUTVALID Digital Out Valid Signal OZ L25 PR0_MDIO_DATA MDIO Data IOZ A10 PR0_MDIO_MDCLK MDIO Clock OZ C10 PR0_PRU0_GPI0 PRU0 General-Purpose Input I D3 PR0_PRU0_GPI1 PRU0 General-Purpose Input I A2 PR0_PRU0_GPI2 PRU0 General-Purpose Input I E4 PR0_PRU0_GPI3 PRU0 General-Purpose Input I B1 PR0_PRU0_GPI4 PRU0 General-Purpose Input I A3 PR0_PRU0_GPI5 PRU0 General-Purpose Input I E5 PR0_PRU0_GPI6 PRU0 General-Purpose Input I B2 PR0_PRU0_GPI7 PRU0 General-Purpose Input I D4 PR0_PRU0_GPI8 PRU0 General-Purpose Input I E6 PR0_PRU0_GPI9 PRU0 General-Purpose Input I C2 PR0_PRU0_GPI10 PRU0 General-Purpose Input I C3 PR0_PRU0_GPI11 PRU0 General-Purpose Input I D5 PR0_PRU0_GPI12 PRU0 General-Purpose Input I B3 PR0_PRU0_GPI13 PRU0 General-Purpose Input I B4 PR0_PRU0_GPI14 PRU0 General-Purpose Input I A4 PR0_PRU0_GPI15 PRU0 General-Purpose Input I E7 PR0_PRU0_GPI16 PRU0 General-Purpose Input I D6 PR0_PRU0_GPI17 PRU0 General-Purpose Input I C4 PR0_PRU0_GPI18 PRU0 General-Purpose Input I C5 PR0_PRU0_GPI19 PRU0 General-Purpose Input I A5 PR0_PRU0_GPO0 PRU0 General-Purpose Output OZ D3 PR0_PRU0_GPO1 PRU0 General-Purpose Output OZ A2 PR0_PRU0_GPO2 PRU0 General-Purpose Output OZ E4 PR0_PRU0_GPO3 PRU0 General-Purpose Output OZ B1 PR0_PRU0_GPO4 PRU0 General-Purpose Output OZ A3 PR0_PRU0_GPO5 PRU0 General-Purpose Output OZ E5 PR0_PRU0_GPO6 PRU0 General-Purpose Output OZ B2 PR0_PRU0_GPO7 PRU0 General-Purpose Output OZ D4 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions ADVANCE INFORMATION Table 4-20. PRU-ICSS Signal Descriptions 63 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-20. PRU-ICSS Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] ADVANCE INFORMATION PR0_PRU0_GPO8 PRU0 General-Purpose Output OZ E6 PR0_PRU0_GPO9 PRU0 General-Purpose Output OZ C2 PR0_PRU0_GPO10 PRU0 General-Purpose Output OZ C3 PR0_PRU0_GPO11 PRU0 General-Purpose Output OZ D5 PR0_PRU0_GPO12 PRU0 General-Purpose Output OZ B3 PR0_PRU0_GPO13 PRU0 General-Purpose Output OZ B4 PR0_PRU0_GPO14 PRU0 General-Purpose Output OZ A4 PR0_PRU0_GPO15 PRU0 General-Purpose Output OZ E7 PR0_PRU0_GPO16 PRU0 General-Purpose Output OZ D6 PR0_PRU0_GPO17 PRU0 General-Purpose Output OZ C4 PR0_PRU0_GPO18 PRU0 General-Purpose Output OZ C5 PR0_PRU0_GPO19 PRU0 General-Purpose Output OZ A5 PR0_PRU1_GPI0 PRU1 General-Purpose Input I B5 PR0_PRU1_GPI1 PRU1 General-Purpose Input I B6 PR0_PRU1_GPI2 PRU1 General-Purpose Input I D7 PR0_PRU1_GPI3 PRU1 General-Purpose Input I A6 PR0_PRU1_GPI4 PRU1 General-Purpose Input I C6 PR0_PRU1_GPI5 PRU1 General-Purpose Input I E8 PR0_PRU1_GPI6 PRU1 General-Purpose Input I A7 PR0_PRU1_GPI7 PRU1 General-Purpose Input I D8 PR0_PRU1_GPI8 PRU1 General-Purpose Input I F9 PR0_PRU1_GPI9 PRU1 General-Purpose Input I B7 PR0_PRU1_GPI10 PRU1 General-Purpose Input I C7 PR0_PRU1_GPI11 PRU1 General-Purpose Input I E9 PR0_PRU1_GPI12 PRU1 General-Purpose Input I A8 PR0_PRU1_GPI13 PRU1 General-Purpose Input I B8 PR0_PRU1_GPI14 PRU1 General-Purpose Input I D9 PR0_PRU1_GPI15 PRU1 General-Purpose Input I C8 PR0_PRU1_GPI16 PRU1 General-Purpose Input I C9 PR0_PRU1_GPI17 PRU1 General-Purpose Input I B9 PR0_PRU1_GPI18 PRU1 General-Purpose Input I A9 PR0_PRU1_GPI19 PRU1 General-Purpose Input I B10 PR0_PRU1_GPO0 PRU1 General-Purpose Output OZ B5 PR0_PRU1_GPO1 PRU1 General-Purpose Output OZ B6 PR0_PRU1_GPO2 PRU1 General-Purpose Output OZ D7 PR0_PRU1_GPO3 PRU1 General-Purpose Output OZ A6 PR0_PRU1_GPO4 PRU1 General-Purpose Output OZ C6 PR0_PRU1_GPO5 PRU1 General-Purpose Output OZ E8 PR0_PRU1_GPO6 PRU1 General-Purpose Output OZ A7 PR0_PRU1_GPO7 PRU1 General-Purpose Output OZ D8 PR0_PRU1_GPO8 PRU1 General-Purpose Output OZ F9 PR0_PRU1_GPO9 PRU1 General-Purpose Output OZ B7 PR0_PRU1_GPO10 PRU1 General-Purpose Output OZ C7 PR0_PRU1_GPO11 PRU1 General-Purpose Output OZ E9 PR0_PRU1_GPO12 PRU1 General-Purpose Output OZ A8 PR0_PRU1_GPO13 PRU1 General-Purpose Output OZ B8 PR0_PRU1_GPO14 PRU1 General-Purpose Output OZ D9 64 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] PR0_PRU1_GPO15 PRU1 General-Purpose Output OZ C8 PR0_PRU1_GPO16 PRU1 General-Purpose Output OZ C9 PR0_PRU1_GPO17 PRU1 General-Purpose Output OZ B9 PR0_PRU1_GPO18 PRU1 General-Purpose Output OZ A9 PR0_PRU1_GPO19 PRU1 General-Purpose Output OZ B10 PR0_UART0_CTSN UART Clear-To-Send I F25 PR0_UART0_RTSN UART Ready-To-Send OZ F24 PR0_UART0_RXD UART Receive Data I E25 PR0_UART0_TXD UART Transmit Data OZ E24 PR1_eCAP0_eCAP_CAPIN_APWM_O Capture Input and PWM Output IOZ R25 PR1_eCAP0_eCAP_SYNCIN Capture Sync Input PR1_eCAP0_eCAP_SYNCOUT Cpature Sync Output PR1_EDC_LATCH0_IN Latch Input 0 PR1_EDC_LATCH1_IN Latch Input 1 PR1_EDC_SYNC0_OUT SYNC 0 Output PR1_EDC_SYNC1_OUT SYNC 1 Output OZ E16 PR1_EDIO_DATA0 Digital Input IOZ C21 PR1_EDIO_DATA1 Digital Input IOZ D22 PR1_EDIO_DATA2 Digital Input IOZ D21 PR1_EDIO_DATA3 Digital Input IOZ E21 PR1_EDIO_OUTVALID Digital Out Valid Signal OZ M25 PR1_MDIO_DATA MDIO Data IOZ E18 PR1_MDIO_MDCLK MDIO Clock OZ D18 PR1_PRU0_GPI0 PRU0 General-Purpose Input I E10 PR1_PRU0_GPI1 PRU0 General-Purpose Input I D10 PR1_PRU0_GPI2 PRU0 General-Purpose Input I F10 PR1_PRU0_GPI3 PRU0 General-Purpose Input I C11 PR1_PRU0_GPI4 PRU0 General-Purpose Input I D11 PR1_PRU0_GPI5 PRU0 General-Purpose Input I E11 PR1_PRU0_GPI6 PRU0 General-Purpose Input I F12 PR1_PRU0_GPI7 PRU0 General-Purpose Input I E12 PR1_PRU0_GPI8 PRU0 General-Purpose Input I C12 PR1_PRU0_GPI9 PRU0 General-Purpose Input I B11 PR1_PRU0_GPI10 PRU0 General-Purpose Input I B12 PR1_PRU0_GPI11 PRU0 General-Purpose Input I A12 PR1_PRU0_GPI12 PRU0 General-Purpose Input I A11 PR1_PRU0_GPI13 PRU0 General-Purpose Input I A13 PR1_PRU0_GPI14 PRU0 General-Purpose Input I B13 PR1_PRU0_GPI15 PRU0 General-Purpose Input I F13 PR1_PRU0_GPI16 PRU0 General-Purpose Input I C13 PR1_PRU0_GPI17 PRU0 General-Purpose Input I E13 PR1_PRU0_GPI18 PRU0 General-Purpose Input I D12 PR1_PRU0_GPI19 PRU0 General-Purpose Input I D13 PR1_PRU0_GPO0 PRU0 General-Purpose Output OZ E10 PR1_PRU0_GPO1 PRU0 General-Purpose Output OZ D10 PR1_PRU0_GPO2 PRU0 General-Purpose Output OZ F10 PR1_PRU0_GPO3 PRU0 General-Purpose Output OZ C11 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 I P22 OZ N25 I D12 I E17 OZ D13 Terminal Configuration and Functions ADVANCE INFORMATION Table 4-20. PRU-ICSS Signal Descriptions (continued) 65 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-20. PRU-ICSS Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] ADVANCE INFORMATION PR1_PRU0_GPO4 PRU0 General-Purpose Output OZ D11 PR1_PRU0_GPO5 PRU0 General-Purpose Output OZ E11 PR1_PRU0_GPO6 PRU0 General-Purpose Output OZ F12 PR1_PRU0_GPO7 PRU0 General-Purpose Output OZ E12 PR1_PRU0_GPO8 PRU0 General-Purpose Output OZ C12 PR1_PRU0_GPO9 PRU0 General-Purpose Output OZ B11 PR1_PRU0_GPO10 PRU0 General-Purpose Output OZ B12 PR1_PRU0_GPO11 PRU0 General-Purpose Output OZ A12 PR1_PRU0_GPO12 PRU0 General-Purpose Output OZ A11 PR1_PRU0_GPO13 PRU0 General-Purpose Output OZ A13 PR1_PRU0_GPO14 PRU0 General-Purpose Output OZ B13 PR1_PRU0_GPO15 PRU0 General-Purpose Output OZ F13 PR1_PRU0_GPO16 PRU0 General-Purpose Output OZ C13 PR1_PRU0_GPO17 PRU0 General-Purpose Output OZ E13 PR1_PRU0_GPO18 PRU0 General-Purpose Output OZ D12 PR1_PRU0_GPO19 PRU0 General-Purpose Output OZ D13 PR1_PRU1_GPI0 PRU1 General-Purpose Input I A14 PR1_PRU1_GPI1 PRU1 General-Purpose Input I B14 PR1_PRU1_GPI2 PRU1 General-Purpose Input I C14 PR1_PRU1_GPI3 PRU1 General-Purpose Input I E14 PR1_PRU1_GPI4 PRU1 General-Purpose Input I D14 PR1_PRU1_GPI5 PRU1 General-Purpose Input I A15 PR1_PRU1_GPI6 PRU1 General-Purpose Input I F14 PR1_PRU1_GPI7 PRU1 General-Purpose Input I B15 PR1_PRU1_GPI8 PRU1 General-Purpose Input I C15 PR1_PRU1_GPI9 PRU1 General-Purpose Input I D15 PR1_PRU1_GPI10 PRU1 General-Purpose Input I A16 PR1_PRU1_GPI11 PRU1 General-Purpose Input I E15 PR1_PRU1_GPI12 PRU1 General-Purpose Input I B16 PR1_PRU1_GPI13 PRU1 General-Purpose Input I C16 PR1_PRU1_GPI14 PRU1 General-Purpose Input I D17 PR1_PRU1_GPI15 PRU1 General-Purpose Input I C18 PR1_PRU1_GPI16 PRU1 General-Purpose Input I D16 PR1_PRU1_GPI17 PRU1 General-Purpose Input I F16 PR1_PRU1_GPI18 PRU1 General-Purpose Input I E17 PR1_PRU1_GPI19 PRU1 General-Purpose Input I E16 PR1_PRU1_GPO0 PRU1 General-Purpose Output OZ A14 PR1_PRU1_GPO1 PRU1 General-Purpose Output OZ B14 PR1_PRU1_GPO2 PRU1 General-Purpose Output OZ C14 PR1_PRU1_GPO3 PRU1 General-Purpose Output OZ E14 PR1_PRU1_GPO4 PRU1 General-Purpose Output OZ D14 PR1_PRU1_GPO5 PRU1 General-Purpose Output OZ A15 PR1_PRU1_GPO6 PRU1 General-Purpose Output OZ F14 PR1_PRU1_GPO7 PRU1 General-Purpose Output OZ B15 PR1_PRU1_GPO8 PRU1 General-Purpose Output OZ C15 PR1_PRU1_GPO9 PRU1 General-Purpose Output OZ D15 PR1_PRU1_GPO10 PRU1 General-Purpose Output OZ A16 66 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] E15 PR1_PRU1_GPO11 PRU1 General-Purpose Output OZ PR1_PRU1_GPO12 PRU1 General-Purpose Output OZ B16 PR1_PRU1_GPO13 PRU1 General-Purpose Output OZ C16 PR1_PRU1_GPO14 PRU1 General-Purpose Output OZ D17 PR1_PRU1_GPO15 PRU1 General-Purpose Output OZ C18 PR1_PRU1_GPO16 PRU1 General-Purpose Output OZ D16 PR1_PRU1_GPO17 PRU1 General-Purpose Output OZ F16 PR1_PRU1_GPO18 PRU1 General-Purpose Output OZ E17 PR1_PRU1_GPO19 PRU1 General-Purpose Output OZ E16 PR1_UART0_CTSN UART Clear-To-Send I H22 PR1_UART0_RTSN UART Ready-To-Send OZ H21 PR1_UART0_RXD UART Receive Data I C4 PR1_UART0_TXD UART Transmit Data OZ B9 ADVANCE INFORMATION Table 4-20. PRU-ICSS Signal Descriptions (continued) NOTE PRU-ICSS has internal-multiplexing capability of pin functions. See Programmable RealTime Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM. Besides, EGPIO (enhanced GPIO) module can be configured to export additional functions to EGPIO pins in place of simple GPIO. See section PRU-ICSS PRU Cores in chapter Processors and Accelerators of the device TRM. 4.3.20 Emulation and Debug Subsystem Table 4-21. Debug Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] M22 EMU00 Emulator pin 0 IOZ EMU01 Emulator pin 1 IOZ L22 EMU02 Emulator pin 2 IOZ N23 EMU03 Emulator pin 3 IOZ P25 EMU04 Emulator pin 4 IOZ P24 EMU05 Emulator pin 5 IOZ N24 EMU06 Emulator pin 6 IOZ T25 EMU07 Emulator pin 7 IOZ N22 EMU08 Emulator pin 8 IOZ R24 EMU09 Emulator pin 9 IOZ P23 EMU10 Emulator pin 10 IOZ R22 EMU11 Emulator pin 11 IOZ U25 EMU12 Emulator pin 12 IOZ P21 EMU13 Emulator pin 13 IOZ T24 EMU14 Emulator pin 14 IOZ V25 EMU15 Emulator pin 15 IOZ U24 EMU16 Emulator pin 16 IOZ R21 EMU17 Emulator pin 17 IOZ T22 EMU18 Emulator pin 18 IOZ U22 EMU19 Emulator pin 19 IOZ T21 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 67 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-21. Debug Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [3] DESCRIPTION [2] ZBB BALL [4] OBSCLK_N Reserved. Never connect to a load. O L1 OBSCLK_P Reserved. Never connect to a load. O K1 OBSPLL_LOCK Device PLLs lock indicator OZ N5 TCK JTAG test clock input I L3 TDI JTAG test data input I L5 TDO JTAG test port data output OZ K5 TMS JTAG test port mode select input. An external pullup resistor must be used on this ball. I K4 TRSTn JTAG test reset I L4 PIN TYPE [3] ZBB BALL [4] For more information, see chapter On-chip Debug of the device TRM. 4.3.21 System and Miscellaneous 4.3.21.1 Boot Mode Configuration ADVANCE INFORMATION Table 4-22. Sysboot Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] BOOTCOMPLETE ARM and DSP boot complete indicator OZ Y3 BOOTMODE00 Bootmode pin 00 I N23 BOOTMODE01 Bootmode pin 01 I P25 BOOTMODE02 Bootmode pin 02 I P24 BOOTMODE03 Bootmode pin 03 I N24 BOOTMODE04 Bootmode pin 04 I T25 BOOTMODE05 Bootmode pin 05 I N22 BOOTMODE06 Bootmode pin 06 I R24 BOOTMODE07 Bootmode pin 07 I P23 BOOTMODE08 Bootmode pin 08 I R22 BOOTMODE09 Bootmode pin 09 I U25 BOOTMODE10 Bootmode pin 10 I P21 BOOTMODE11 Bootmode pin 11 I T24 BOOTMODE12 Bootmode pin 12 I V25 BOOTMODE13 Bootmode pin 13 I U24 BOOTMODE14 Bootmode pin 14 I R21 BOOTMODE15 Bootmode pin 15 I T22 MAINPLL_OD_SEL Main PLL Output devide I W22 NODDR Bootmode pin for no-DDR usecase I U23 For more information, see chapter Initialization of the device TRM. 68 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 4.3.21.2 Reset Table 4-23. Reset Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] V2 LRESETn Local Reset to DSP (Active Low) I LRESETNMIENn Enable for l_reset_n and NMIn (Active Low) I V1 PORn Power-on Reset (Active Low). This pin must be asserted low until all device supplies are valid (see Section 5.9.1, Power Supply Sequencing). I AA3 RESETFULLn Cold Reset (Active Low) I W2 RESETn Device Reset Input (Active Low) I W3 RESETSTATn Reset Status Indicator (Active Low) O Y2 For more information, see section Reset Management in chapter Device Configuration of the device TRM. 4.3.21.3 Oscillator Reference Clocks and Clock Generator SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ZBB BALL [4] AUDOSC_IN Optional audio input crystal interface pin connected to secondary internal oscillator dedicated for Audio Applications. This clock feeds McASPs and McBSP. I C17 AUDOSC_OUT Optional audio output crystal interface pin connected to secondary internal oscillator dedicated for Audio Applications. This clock feeds McASPs and McBSP. O A17 CLKOUT Device Reference Clock Output OZ H23 CPTS_REFCLK_N Differential CPTS Reference Clock Input. Negative I L21 CPTS_REFCLK_P Differential CPTS Reference Clock Input. Positive I K21 SYSCLKOUT SYSCLK1 coming from the DPLL Controller for test and debug. It is divided by 6. OZ M21 SYSCLK_N Differential System Clock Input for SYS_OSCCLK. Negative I AC25 SYSCLK_P Differential System Clock Input for SYS_OSCCLK. Positive I AD25 SYSOSC_IN System Oscillator OSC0 Crystal Input and LVCMOS clock Input. Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used. I AC19 SYSOSC_OUT System Oscillator OSC0 Crystal Output O AE19 XREFCLK External Reference Clock. For Audio and other Peripherals. I C2 PIN TYPE [3] ZBB BALL [4] I R1 ADVANCE INFORMATION Table 4-24. Clock Signal Descriptions 4.3.21.4 Miscellaneous Table 4-25. Miscellaneous Signal Descriptions SIGNAL NAME [1] SYSCLKSEL DESCRIPTION [2] System Clock Selection Control (Internal Oscillator versus External Clock) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 69 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 4.3.21.5 Interrupt Controllers (INTC) Table 4-26. INTC Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] NMIn Nonmaskable interrupt (Active Low) PIN TYPE [3] ZBB BALL [4] I W1 PIN TYPE [3] ZBB BALL [4] For more information, see chapter Interrupts of the device TRM. 4.3.21.6 Power Supplies Table 4-27. Power Supply Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] ADVANCE INFORMATION AVDDA_ARMPLL ARM_PLL analog power supply voltage PWR N6 AVDDA_DDRPLL DDR_PLL analog power supply voltage PWR W20 AVDDA_DSSPLL DSS_PLL analog power supply voltage PWR N20 AVDDA_ICSSPLL ICSS_PLL analog power supply voltage PWR G8 AVDDA_MAINPLL MAIN_PLL analog power supply voltage PWR M19 AVDDA_NSSPLL NSS_PLL analog power supply voltage PWR G14 AVDDA_UARTPLL UART_PLL analog power supply voltage PWR G10 CVDD Core power supply voltage PWR J10, J14, J16, K11, K13, K15, K17, K9, L10, L12, L14, L16, L18, M11, M13, M15, M17, M9, N10, N12, N14, N16, P11, P13, P15, P17, P9, R10, R12, R14, R16, R18, R8, T11, T15, T17, T9, U16 CVDD1 Core fixed power supply voltage PWR M5, J12, N18, N8, T13 DVDD18 1.8-V I/Os power supply voltage PWR F17, F19, G6, H5, J6, K19, L20, L6, M7, U18, U6, V19, W6 DVDD33 3.3-V I/Os power supply voltage PWR AA23, E23, F11, F15, F21, F7, G12, G16, G20, H11, H13, H15, H9, J20, P19, P7, R20, R6, T19, T23, T7, U20, V21 DVDD33_USB USB 3.3-V IO supply voltage PWR G18, H17 DVDD_DDR DDR EMIF I/Os power supply voltage PWR AD11, AD18, AD5, AE14, AE8, U10, U12, U14, U8, V11, V13, V15, V17, V7, W16, W18 DDR3_VREFSSTL DDR EMIF Reference Power Supply PWR Y9 DVDD_DDRDLL DDR EMIF PHY DLL power supply voltage PWR W10, W14, W8 LDO_PCIE_CAP(1) SERDES LDO output CAP J8, L8 LDO_USB_CAP(1) USB LDO output CAP H19, J18 VDDAHV PCIESS SERDES I/O power supply voltage PWR K7 VPP Reserved, leave unconnected PWR Y21 VPP2 Reserved, leave unconnected PWR W21 VSS_OSC_AUDIO AUDOSC Ground GND B17 VSS_OSC_SYS SYSOSC Ground GND AD19 70 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-27. Power Supply Signal Descriptions (continued) VSS DESCRIPTION [2] Ground PIN TYPE [3] GND ZBB BALL [4] A1, A25, AD14, AD8, AE1, AE11, AE18, AE25, AE5, C1, E2, E22, F1, F20, F3, F6, F8, G11, G13, G15, G17, G19, G21, G7, G9, H10, H12, H14, H16, H18, H20, H6, H8, J1, J11, J13, J15, J17, J19, J7, J9, K10, K12, K14, K16, K18, K20, K6, K8, L11, L13, L15, L17, L19, L7, L9, M10, M12, M14, M16, M18, M20, M6, M8, N11, N13, N15, N17, N19, N21, N7, N9, P10, P12, P14, P16, P18, P20, P6, P8, R11, R13, R15, R17, R19, R23, R7, R9, T10, T12, T14, T16, T18, T20, T6, T8, U11, U13, U15, U17, U19, U7, U9, V10, V12, V14, V16, V18, V20, V8, W11, W13, W15, W17, W7, W9, Y10, Y23 (1) This pin must always be connected through a 1-µF capacitor to VSS. For more information, see section Power Management in chapter Device Configuration of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 71 ADVANCE INFORMATION SIGNAL NAME [1] 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 4.4 www.ti.com Pin Multiplexing Table 4-28 describes the device pin multiplexing (no characteristics are provided in this table). NOTE Table 4-28, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions. NOTE When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided. ADVANCE INFORMATION For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Table 4-28. Pin Multiplexing MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 72 1 R1 SYSCLKSEL Y15 DDR3_A01 AB4 DDR3_DQM0 L1 OBSCLK_N Y6 DDR3_D10 AE15 DDR3_CLKOUT_P0 AA3 PORn AA17 DDR3_A12 AE7 DDR3_D22 A19 USB0_ID AB16 DDR3_A04 C19 USB0_TXRTUNE_RKE LVIN AE9 DDR3_DQS3_P W2 RESETFULLn A21 USB1_VBUS AE4 DDR3_DQS1_N V9 DDR3_RZQ1 AD16 DDR3_CLKOUT_N1 AE19 SYSOSC_OUT L24 MLBP_SIG_P AC11 DDR3_CB02 2 Terminal Configuration and Functions 3 4 5 Bootstrap Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS REGISTER NAME BALL NUMBER 0 1 K1 OBSCLK_P L22 EMU01 A20 USB1_DM AD1 DDR3_DQS0_P AE3 DDR3_D04 H7 PCIE_REFRES K22 MLBP_DAT_N AA8 DDR3_D20 AC14 DDR3_A06 AB8 DDR3_D17 AC17 DDR3_A08 AC6 DDR3_D21 W3 RESETn AD6 DDR3_DQS2_N AA9 DDR3_DQM3 AB10 DDR3_D29 AA12 DDR3_A13 Y16 DDR3_A15 AA4 DDR3_D05 AA16 DDR3_A11 AA5 DDR3_DQM1 C17 AUDOSC_IN AB15 DDR3_A07 D20 USB1_TXRTUNE_RKE LVIN Y5 DDR3_D13 F2 PCIE_CLK_N L23 MLBP_CLK_N AD13 DDR3_CEn0 AB9 DDR3_D30 D19 USB0_XO AC25 SYSCLK_N AE16 DDR3_CLKOUT_P1 L21 CPTS_REFCLK_N W12 DDR3_RZQ0 AE24 DDR_CLK_P AB5 DDR3_D15 AC15 DDR3_A00 AE10 DDR3_D25 2 3 4 5 Bootstrap ADVANCE INFORMATION ADDRESS OFFSET Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 73 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 ADVANCE INFORMATION 74 1 AA15 DDR3_A03 M24 MLBP_SIG_N E1 PCIE_RXP0 AD17 DDR3_BA2 AC3 DDR3_D02 K5 TDO AC7 DDR3_D18 AD9 DDR3_DQS3_N Y8 DDR3_D31 L3 TCK K23 MLBP_DAT_P Y11 DDR3_CBDQM AB14 DDR3_A10 Y13 DDR3_WEn A18 USB0_DP AD24 DDR_CLK_N Y17 DDR3_A14 AC8 DDR3_DQM2 AC12 DDR3_CB03 AA6 DDR3_D08 AD7 DDR3_D23 B19 USB0_VBUS AA11 DDR3_CB00 AC10 DDR3_D27 AE17 DDR3_A05 AE12 DDR3_CBDQS_P AA14 DDR3_BA0 G2 PCIE_CLK_P AC4 DDR3_D14 Y9 DDR3_VREFSSTL H1 PCIE_TXN0 AB18 DDR3_CKE0 AB6 DDR3_D12 E20 USB1_ID L4 TRSTn AC19 SYSOSC_IN AD3 DDR3_D06 B20 USB1_DP AE6 DDR3_DQS2_P 2 Terminal Configuration and Functions 3 4 5 Bootstrap Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS REGISTER NAME BALL NUMBER 0 1 AB7 DDR3_D16 M22 EMU00 D1 PCIE_RXN0 M23 MLBP_CLK_P AB3 DDR3_D07 AD2 DDR3_D00 A17 AUDOSC_OUT B18 USB0_DM AB13 DDR3_BA1 K4 TMS AB17 DDR3_A09 Y7 DDR3_D09 AD15 DDR3_CLKOUT_N0 Y18 DDR3_RESETn AC13 DDR3_CASn AC2 DDR3_D03 G1 PCIE_TXP0 AD12 DDR3_CBDQS_N AD10 DDR3_D26 AE13 DDR3_RASn AE2 DDR3_DQS0_N AA13 DDR3_ODT0 C20 USB1_XO L5 TDI AA10 DDR3_D24 K21 CPTS_REFCLK_P AA7 DDR3_D19 AC5 DDR3_D11 Y4 DDR3_D01 AC16 DDR3_A02 AB11 DDR3_CB01 AD25 SYSCLK_P AC9 DDR3_D28 AD4 DDR3_DQS1_P U5 I2C0_SCL W5 I2C0_SDA V6 I2C1_SCL W4 I2C1_SDA V5 I2C2_SCL 2 3 4 5 Bootstrap ADVANCE INFORMATION ADDRESS OFFSET Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 75 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 V4 I2C2_SDA 1 2 3 4 5 Bootstrap ADVANCE INFORMATION 0x1000 PADCONFIG_0 AC21 GPMC_AD0 GPIO0_00 0x1004 PADCONFIG_1 AE20 GPMC_AD1 GPIO0_01 0x1008 PADCONFIG_2 AD22 GPMC_AD2 GPIO0_02 0x100C PADCONFIG_3 AD20 GPMC_AD3 GPIO0_03 0x1010 PADCONFIG_4 AE21 GPMC_AD4 GPIO0_04 0x1014 PADCONFIG_5 AE22 GPMC_AD5 GPIO0_05 0x1018 PADCONFIG_6 AC20 GPMC_AD6 GPIO0_06 0x101C PADCONFIG_7 AD21 GPMC_AD7 GPIO0_07 0x1020 PADCONFIG_8 AE23 GPMC_AD8 GPIO0_08 0x1024 PADCONFIG_9 AB20 GPMC_AD9 GPIO0_09 0x1028 PADCONFIG_10 AA20 GPMC_AD10 GPIO0_10 0x102C PADCONFIG_11 AD23 GPMC_AD11 GPIO0_11 0x1030 PADCONFIG_12 AA21 GPMC_AD12 GPIO0_12 0x1034 PADCONFIG_13 AB21 GPMC_AD13 GPIO0_13 0x1038 PADCONFIG_14 AB22 GPMC_AD14 GPIO0_14 0x103C PADCONFIG_15 AA22 GPMC_AD15 GPIO0_15 0x1040 PADCONFIG_16 AB23 GPMC_CLK GPIO0_16 0x1044 PADCONFIG_17 AC23 GPMC_ADVn_ALE GPIO0_17 0x1048 PADCONFIG_18 AC22 GPMC_OEn_REn GPIO0_18 0x104C PADCONFIG_19 Y22 GPMC_WEn GPIO0_19 0x1050 PADCONFIG_20 AC24 GPMC_BEn0_CLE GPIO0_20 0x1054 PADCONFIG_21 AB24 GPMC_BEn1 GPIO0_21 0x1058 PADCONFIG_22 Y24 GPMC_WAIT0 0x105C PADCONFIG_23 AA24 GPMC_WAIT1 0x1060 PADCONFIG_24 W25 GPMC_WPn 0x1064 PADCONFIG_25 AA25 GPMC_DIR 0x1068 PADCONFIG_26 AB25 GPMC_CSn0 0x106C PADCONFIG_27 W24 GPMC_CSn1 MLB_DAT GPIO0_27 0x1070 PADCONFIG_28 W23 GPMC_CSn2 TIMI1 GPIO0_28 0x1074 PADCONFIG_29 Y25 GPMC_CSn3 TIMO1 GPIO0_29 0x1078 PADCONFIG_30 N23 DSS_DATA23 GPMC_A24 eHRPWM0_A GPIO0_30 EMU02 BOOTMODE00 0x107C PADCONFIG_31 P25 DSS_DATA22 GPMC_A23 eHRPWM0_B GPIO0_31 EMU03 BOOTMODE01 0x1080 PADCONFIG_32 P24 DSS_DATA21 GPMC_A22 eHRPWM_TZn0 GPIO0_32 EMU04 BOOTMODE02 0x1084 PADCONFIG_33 N24 DSS_DATA20 GPMC_A21 eHRPWM0_SYNCI GPIO0_33 EMU05 BOOTMODE03 0x1088 PADCONFIG_34 T25 DSS_DATA19 GPMC_A20 eHRPWM0_SYNCO GPIO0_34 EMU06 DSS_RFBI_TEVSYNC BOOTMODE04 1 0x108C PADCONFIG_35 N22 DSS_DATA18 GPMC_A19 eHRPWM1_A GPIO0_35 EMU07 DSS_RFBI_HSYNC1 BOOTMODE05 0x1090 PADCONFIG_36 R24 DSS_DATA17 GPMC_A18 eHRPWM1_B GPIO0_36 EMU08 DSS_RFBI_CSn1 BOOTMODE06 76 GPIO0_22 MLB_CLK GPIO0_23 GPIO0_24 MLB_SIG GPIO0_25 GPIO0_26 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS REGISTER NAME BALL NUMBER 0 1 2 3 4 5 Bootstrap 0x1094 PADCONFIG_37 P23 DSS_DATA16 GPMC_A17 eHRPWM_TZn1 GPIO0_37 EMU09 DSS_RFBI_CSn0 BOOTMODE07 0x1098 PADCONFIG_38 R22 DSS_DATA15 GPMC_A16 eHRPWM2_A GPIO0_38 EMU10 DSS_RFBI_DATA15 BOOTMODE08 0x109C PADCONFIG_39 U25 DSS_DATA14 GPMC_A15 eHRPWM2_B GPIO0_39 EMU11 DSS_RFBI_DATA14 BOOTMODE09 0x10A0 PADCONFIG_40 P21 DSS_DATA13 GPMC_A14 eHRPWM_TZn2 GPIO0_40 EMU12 DSS_RFBI_DATA13 BOOTMODE10 0x10A4 PADCONFIG_41 T24 DSS_DATA12 GPMC_A13 eQEP0_A GPIO0_41 EMU13 DSS_RFBI_DATA12 BOOTMODE11 0x10A8 PADCONFIG_42 V25 DSS_DATA11 GPMC_A12 eQEP0_B GPIO0_42 EMU14 DSS_RFBI_DATA11 BOOTMODE12 0x10AC PADCONFIG_43 U24 DSS_DATA10 GPMC_A11 eQEP0_I GPIO0_43 EMU15 DSS_RFBI_DATA10 BOOTMODE13 0x10B0 PADCONFIG_44 R21 DSS_DATA9 GPMC_A10 eQEP0_S GPIO0_44 EMU16 DSS_RFBI_DATA9 BOOTMODE14 0x10B4 PADCONFIG_45 T22 DSS_DATA8 GPMC_A9 eQEP1_A GPIO0_45 EMU17 DSS_RFBI_DATA8 BOOTMODE15 0x10B8 PADCONFIG_46 U22 DSS_DATA7 GPMC_A8 eQEP1_B GPIO0_46 EMU18 DSS_RFBI_DATA7 0x10BC PADCONFIG_47 T21 DSS_DATA6 GPMC_A7 eQEP1_I GPIO0_47 EMU19 DSS_RFBI_DATA6 0x10C0 PADCONFIG_48 V24 DSS_DATA5 GPMC_A6 eQEP1_S GPIO0_48 DSS_RFBI_DATA5 0x10C4 PADCONFIG_49 U23 DSS_DATA4 GPMC_A5 eQEP2_A GPIO0_49 DSS_RFBI_DATA4 0x10C8 PADCONFIG_50 V23 DSS_DATA3 GPMC_A4 eQEP2_B GPIO0_50 DSS_RFBI_DATA3 0x10CC PADCONFIG_51 W22 DSS_DATA2 GPMC_A3 eQEP2_I GPIO0_51 DSS_RFBI_DATA2 0x10D0 PADCONFIG_52 U21 DSS_DATA1 GPMC_A2 eQEP2_S GPIO0_52 DSS_RFBI_DATA1 0x10D4 PADCONFIG_53 V22 DSS_DATA0 GPMC_A1 GPIO0_53 DSS_RFBI_DATA0 0x10D8 PADCONFIG_54 R25 DSS_VSYNC GPMC_A25 PR1_eCAP0_eCAP_C GPIO0_54 APIN_APWM_O DSS_RFBI_TEVSYNC 0 0x10DC PADCONFIG_55 P22 DSS_HSYNC GPMC_A26 PR1_eCAP0_eCAP_S GPIO0_55 YNCIN DSS_RFBI_HSYNC0 0x10E0 PADCONFIG_56 N25 DSS_PCLK GPMC_A27 PR1_eCAP0_eCAP_S GPIO0_56 YNCOUT DSS_RFBI_REn 0x10E4 PADCONFIG_57 M25 DSS_DE GPMC_A0 PR1_EDIO_OUTVALID GPIO0_57 DSS_RFBI_WEn 0x10E8 PADCONFIG_58 L25 DSS_FID PR0_EDIO_OUTVALID GPIO0_58 DSS_RFBI_A0 0x10EC PADCONFIG_59 G5 MMC1_DAT7 GPIO0_59 0x10F0 PADCONFIG_60 F4 MMC1_DAT6 GPIO0_60 0x10F4 PADCONFIG_61 G4 MMC1_DAT5 GPIO0_61 0x10F8 PADCONFIG_62 E3 MMC1_DAT4 GPIO0_62 0x10FC PADCONFIG_63 H4 MMC1_DAT3 GPIO0_63 0x1100 PADCONFIG_64 J5 MMC1_DAT2 GPIO0_64 0x1104 PADCONFIG_65 F5 MMC1_DAT1 GPIO0_65 0x1108 PADCONFIG_66 H3 MMC1_DAT0 GPIO0_66 0x110C PADCONFIG_67 J4 MMC1_CLK GPIO0_67 0x1110 PADCONFIG_68 J2 MMC1_CMD GPIO0_68 0x1114 PADCONFIG_69 J3 MMC1_SDCD GPIO0_69 0x1118 PADCONFIG_70 K3 MMC1_SDWP GPIO0_70 0x111C PADCONFIG_71 K2 MMC1_POW 0x1120 PADCONFIG_72 A22 MII_RXCLK 0x1124 PADCONFIG_73 A23 ADVANCE INFORMATION ADDRESS OFFSET NODDR MAINPLL_OD_SEL GPIO0_71 RGMII_RXC GPIO0_72 PR0_EDIO_DATA3 GPIO0_73 eHRPWM3_A Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 77 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 1 2 3 4 ADVANCE INFORMATION 0x1128 PADCONFIG_74 B22 PR0_EDIO_DATA2 GPIO0_74 eHRPWM3_B 0x112C PADCONFIG_75 C22 PR0_EDIO_DATA1 GPIO0_75 eHRPWM3_SYNCI 0x1130 PADCONFIG_76 D23 PR0_EDIO_DATA0 GPIO0_76 eHRPWM3_SYNCO 0x1134 PADCONFIG_77 F22 MII_RXD3 RGMII_RXD3 GPIO0_77 0x1138 PADCONFIG_78 B23 MII_RXD2 RGMII_RXD2 0x113C PADCONFIG_79 C23 MII_RXD1 RGMII_RXD1 RMII_RXD1 GPIO0_79 0x1140 PADCONFIG_80 B24 MII_RXD0 RGMII_RXD0 RMII_RXD0 GPIO0_80 0x1144 PADCONFIG_81 A24 MII_RXDV RGMII_RXCTL 0x1148 PADCONFIG_82 F23 MII_RXER 0x114C PADCONFIG_83 B25 MII_COL 0x1150 PADCONFIG_84 G22 MII_CRS 0x1154 PADCONFIG_85 C25 MII_TXCLK 0x1158 PADCONFIG_86 C24 SPI3_SCSn0 PR0_eCAP0_eCAP_C GPIO0_86 APIN_APWM_O 0x115C PADCONFIG_87 E25 SPI3_SCSn1 PR0_UART0_RXD GPIO0_87 0x1160 PADCONFIG_88 E24 SPI3_CLK PR0_UART0_TXD GPIO0_88 0x1164 PADCONFIG_89 F25 SPI3_SOMI PR0_UART0_CTSN GPIO0_89 0x1168 PADCONFIG_90 F24 SPI3_SIMO PR0_UART0_RTSN GPIO0_90 0x116C PADCONFIG_91 D25 MII_TXD3 RGMII_TXD3 0x1170 PADCONFIG_92 G25 MII_TXD2 RGMII_TXD2 0x1174 PADCONFIG_93 G24 MII_TXD1 RGMII_TXD1 RMII_TXD1 GPIO0_93 0x1178 PADCONFIG_94 G23 MII_TXD0 RGMII_TXD0 RMII_TXD0 GPIO0_94 0x117C PADCONFIG_95 H25 MII_TXEN RGMII_TXCTL RMII_TXEN GPIO0_95 0x1180 PADCONFIG_96 H24 MII_TXER PR0_eCAP0_eCAP_S GPIO0_96 YNCIN 0x1184 PADCONFIG_97 D24 RMII_REFCLK PR0_eCAP0_eCAP_S YNCOUT 0x1188 PADCONFIG_98 V3 MDIO_DATA GPIO0_97 0x118C PADCONFIG_99 U3 MDIO_CLK GPIO0_98 0x1190 PADCONFIG_100 M3 SPI0_SCSn0 0x1194 PADCONFIG_101 M4 SPI0_SCSn1 0x1198 PADCONFIG_102 M2 SPI0_CLK 0x119C PADCONFIG_103 M1 SPI0_SOMI 0x11A0 PADCONFIG_104 N4 SPI0_SIMO 0x11A4 PADCONFIG_105 P1 SPI1_SCSn0 0x11A8 PADCONFIG_106 N3 SPI1_SCSn1 0x11AC PADCONFIG_107 N2 SPI1_CLK 0x11B0 PADCONFIG_108 N1 SPI1_SOMI 0x11B4 PADCONFIG_109 P2 SPI1_SIMO 0x11B8 PADCONFIG_110 P3 SPI2_SCSn0 78 5 Bootstrap GPIO0_78 GPIO0_81 RMII_RXER GPIO0_82 GPIO0_83 RMII_CRS_DV RGMII_TXC GPIO0_84 GPIO0_85 GPIO0_91 GPIO0_92 eHRPWM_TZn3 GPIO0_99 GPIO0_100 GPIO0_101 Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS REGISTER NAME BALL NUMBER 0 1 2 3 4 0x11BC PADCONFIG_111 P4 SPI2_SCSn1 GPIO0_102 0x11C0 PADCONFIG_112 R2 SPI2_CLK GPIO0_103 0x11C4 PADCONFIG_113 R4 SPI2_SOMI GPIO0_104 0x11C8 PADCONFIG_114 R3 SPI2_SIMO GPIO0_105 0x11CC PADCONFIG_115 T4 UART0_RXD 0x11D0 PADCONFIG_116 T1 UART0_TXD 0x11D4 PADCONFIG_117 T2 UART0_CTSn TIMI0 GPIO0_106 0x11D8 PADCONFIG_118 U1 UART0_RTSn TIMO0 GPIO0_107 0x11DC PADCONFIG_119 T3 UART1_RXD GPIO1_48 0x11E0 PADCONFIG_120 T5 UART1_TXD GPIO1_49 0x11E4 PADCONFIG_121 U2 UART1_CTSn GPIO1_50 0x11E8 PADCONFIG_122 U4 UART1_RTSn 0x11EC PADCONFIG_123 E21 UART2_RXD PR1_EDIO_DATA3 UART0_DCDn GPIO1_52 CPTS_HW1_TSPUSH 0x11F0 PADCONFIG_124 D21 UART2_TXD PR1_EDIO_DATA2 UART0_DSRn GPIO1_53 CPTS_HW2_TSPUSH 0x11F4 PADCONFIG_125 D22 UART2_CTSn PR1_EDIO_DATA1 UART0_DTRn GPIO1_54 CPTS_TS_SYNC 0x11F8 PADCONFIG_126 C21 UART2_RTSn PR1_EDIO_DATA0 UART0_RIN GPIO1_55 CPTS_TS_COMP 0x11FC PADCONFIG_127 P5 DCAN0_TX GPIO1_56 0x1200 PADCONFIG_128 R5 DCAN0_RX GPIO1_57 0x1204 PADCONFIG_129 K25 QSPI_CLK GPIO1_58 0x1208 PADCONFIG_130 K24 QSPI_RCLK GPIO1_59 0x120C PADCONFIG_131 J23 QSPI_D0 GPIO1_60 0x1210 PADCONFIG_132 J22 QSPI_D1 GPIO1_61 0x1214 PADCONFIG_133 J21 QSPI_D2 GPIO1_62 0x1218 PADCONFIG_134 J24 QSPI_D3 GPIO1_63 0x121C PADCONFIG_135 J25 QSPI_CSn0 0x1220 PADCONFIG_136 H23 QSPI_CSn1 CLKOUT 0x1224 PADCONFIG_137 H22 QSPI_CSn2 DCAN1_TX PR1_UART0_CTSN GPIO1_66 USB0_EXT_TRIGGER 0x1228 PADCONFIG_138 H21 QSPI_CSn3 DCAN1_RX PR1_UART0_RTSN GPIO1_67 USB1_EXT_TRIGGER 0x122C PADCONFIG_139 D3 PR0_PRU0_GPO0 PR0_PRU0_GPI0 GPIO0_108 MCASP2_AXR0 0x1230 PADCONFIG_140 A2 PR0_PRU0_GPO1 PR0_PRU0_GPI1 GPIO0_109 MCASP2_AXR1 0x1234 PADCONFIG_141 E4 PR0_PRU0_GPO2 PR0_PRU0_GPI2 GPIO0_110 MCASP2_AXR2 0x1238 PADCONFIG_142 B1 PR0_PRU0_GPO3 PR0_PRU0_GPI3 GPIO0_111 MCASP2_AXR3 0x123C PADCONFIG_143 A3 PR0_PRU0_GPO4 PR0_PRU0_GPI4 GPIO0_112 MCASP2_AXR4 0x1240 PADCONFIG_144 E5 PR0_PRU0_GPO5 PR0_PRU0_GPI5 GPIO0_113 MCASP2_AXR5 0x1244 PADCONFIG_145 B2 PR0_PRU0_GPO6 PR0_PRU0_GPI6 GPIO0_114 MCASP2_ACLKR 0x1248 PADCONFIG_146 D4 PR0_PRU0_GPO7 PR0_PRU0_GPI7 GPIO0_115 MCASP2_AFSR 0x124C PADCONFIG_147 E6 PR0_PRU0_GPO8 PR0_PRU0_GPI8 GPIO0_116 MCASP2_AHCLKR 0x1250 PADCONFIG_148 C2 PR0_PRU0_GPO9 PR0_PRU0_GPI9 GPIO0_117 MCASP2_AMUTE 0x1254 PADCONFIG_149 C3 PR0_PRU0_GPO10 PR0_PRU0_GPI10 GPIO0_118 MCASP2_AFSX 5 Bootstrap ADVANCE INFORMATION ADDRESS OFFSET GPIO1_51 GPIO1_64 GPIO1_65 XREFCLK Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 79 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 1 2 3 4 ADVANCE INFORMATION 0x1258 PADCONFIG_150 D5 PR0_PRU0_GPO11 PR0_PRU0_GPI11 GPIO0_119 MCASP2_AHCLKX 0x125C PADCONFIG_151 B3 PR0_PRU0_GPO12 PR0_PRU0_GPI12 GPIO0_120 MCASP2_ACLKX 0x1260 PADCONFIG_152 B4 PR0_PRU0_GPO13 PR0_PRU0_GPI13 GPIO0_121 MCASP1_ACLKR 0x1264 PADCONFIG_153 A4 PR0_PRU0_GPO14 PR0_PRU0_GPI14 GPIO0_122 MCASP1_AFSR 0x1268 PADCONFIG_154 E7 PR0_PRU0_GPO15 PR0_PRU0_GPI15 GPIO0_123 MCASP1_AHCLKR 0x126C PADCONFIG_155 D6 PR0_PRU0_GPO16 PR0_PRU0_GPI16 GPIO0_124 MCASP1_ACLKX 0x1270 PADCONFIG_156 C4 PR0_PRU0_GPO17 PR0_PRU0_GPI17 PR1_UART0_RXD GPIO0_125 MCASP1_AFSX 0x1274 PADCONFIG_157 C5 PR0_PRU0_GPO18 PR0_PRU0_GPI18 PR0_EDC_LATCH0_IN GPIO0_126 MCASP1_AHCLKX 0x1278 PADCONFIG_158 A5 PR0_PRU0_GPO19 PR0_PRU0_GPI19 PR0_EDC_SYNC0_OU GPIO0_127 T MCASP1_AMUTE 0x127C PADCONFIG_159 B5 PR0_PRU1_GPO0 PR0_PRU1_GPI0 GPIO0_128 MCASP1_AXR0 0x1280 PADCONFIG_160 B6 PR0_PRU1_GPO1 PR0_PRU1_GPI1 GPIO0_129 MCASP1_AXR1 0x1284 PADCONFIG_161 D7 PR0_PRU1_GPO2 PR0_PRU1_GPI2 GPIO0_130 MCASP1_AXR2 0x1288 PADCONFIG_162 A6 PR0_PRU1_GPO3 PR0_PRU1_GPI3 GPIO0_131 MCASP1_AXR3 0x128C PADCONFIG_163 C6 PR0_PRU1_GPO4 PR0_PRU1_GPI4 GPIO0_132 MCASP1_AXR4 0x1290 PADCONFIG_164 E8 PR0_PRU1_GPO5 PR0_PRU1_GPI5 GPIO0_133 MCASP1_AXR5 0x1294 PADCONFIG_165 A7 PR0_PRU1_GPO6 PR0_PRU1_GPI6 GPIO0_134 MCASP1_AXR6 0x1298 PADCONFIG_166 D8 PR0_PRU1_GPO7 PR0_PRU1_GPI7 GPIO0_135 MCASP1_AXR7 0x129C PADCONFIG_167 F9 PR0_PRU1_GPO8 PR0_PRU1_GPI8 GPIO0_136 MCASP1_AXR8 0x12A0 PADCONFIG_168 B7 PR0_PRU1_GPO9 PR0_PRU1_GPI9 GPIO0_137 MCASP1_AXR9 0x12A4 PADCONFIG_169 C7 PR0_PRU1_GPO10 PR0_PRU1_GPI10 GPIO0_138 MCASP0_AMUTE 0x12A8 PADCONFIG_170 E9 PR0_PRU1_GPO11 PR0_PRU1_GPI11 GPIO0_139 MCASP0_ACLKR 0x12AC PADCONFIG_171 A8 PR0_PRU1_GPO12 PR0_PRU1_GPI12 GPIO0_140 MCASP0_AFSR 0x12B0 PADCONFIG_172 B8 PR0_PRU1_GPO13 PR0_PRU1_GPI13 GPIO0_141 MCASP0_AHCLKR 0x12B4 PADCONFIG_173 D9 PR0_PRU1_GPO14 PR0_PRU1_GPI14 GPIO0_142 MCASP0_ACLKX 0x12B8 PADCONFIG_174 C8 PR0_PRU1_GPO15 PR0_PRU1_GPI15 GPIO0_143 MCASP0_AFSX 0x12BC PADCONFIG_175 C9 PR0_PRU1_GPO16 PR0_PRU1_GPI16 GPIO1_00 MCASP0_AHCLKX 0x12C0 PADCONFIG_176 B9 PR0_PRU1_GPO17 PR0_PRU1_GPI17 PR1_UART0_TXD GPIO1_01 MCASP0_AXR0 0x12C4 PADCONFIG_177 A9 PR0_PRU1_GPO18 PR0_PRU1_GPI18 PR0_EDC_LATCH1_IN GPIO1_02 MCASP0_AXR1 0x12C8 PADCONFIG_178 B10 PR0_PRU1_GPO19 PR0_PRU1_GPI19 PR0_EDC_SYNC1_OU GPIO1_03 T MCASP0_AXR2 0x12CC PADCONFIG_179 A10 PR0_MDIO_DATA GPIO1_04 MCASP0_AXR3 0x12D0 PADCONFIG_180 C10 PR0_MDIO_MDCLK GPIO1_05 MCASP0_AXR4 0x12D4 PADCONFIG_181 E10 PR1_PRU0_GPO0 PR1_PRU0_GPI0 GPIO1_06 MCASP0_AXR5 0x12D8 PADCONFIG_182 D10 PR1_PRU0_GPO1 PR1_PRU0_GPI1 GPIO1_07 MCASP0_AXR6 0x12DC PADCONFIG_183 F10 PR1_PRU0_GPO2 PR1_PRU0_GPI2 GPIO1_08 MCASP0_AXR7 0x12E0 PADCONFIG_184 C11 PR1_PRU0_GPO3 PR1_PRU0_GPI3 GPIO1_09 MCASP0_AXR8 0x12E4 PADCONFIG_185 D11 PR1_PRU0_GPO4 PR1_PRU0_GPI4 MMC0_POW GPIO1_10 MCASP0_AXR9 0x12E8 PADCONFIG_186 E11 PR1_PRU0_GPO5 PR1_PRU0_GPI5 MMC0_SDWP GPIO1_11 MCASP0_AXR10 80 Terminal Configuration and Functions 5 Bootstrap Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS REGISTER NAME BALL NUMBER 0 1 2 3 4 0x12EC PADCONFIG_187 F12 PR1_PRU0_GPO6 PR1_PRU0_GPI6 MMC0_SDCD GPIO1_12 MCASP0_AXR11 0x12F0 PADCONFIG_188 E12 PR1_PRU0_GPO7 PR1_PRU0_GPI7 MMC0_DAT7 GPIO1_13 MCASP0_AXR12 0x12F4 PADCONFIG_189 C12 PR1_PRU0_GPO8 PR1_PRU0_GPI8 MMC0_DAT6 GPIO1_14 MCASP0_AXR13 0x12F8 PADCONFIG_190 B11 PR1_PRU0_GPO9 PR1_PRU0_GPI9 MMC0_DAT5 GPIO1_15 MCASP0_AXR14 0x12FC PADCONFIG_191 B12 PR1_PRU0_GPO10 PR1_PRU0_GPI10 MMC0_DAT4 GPIO1_16 MCASP0_AXR15 0x1300 PADCONFIG_192 A12 PR1_PRU0_GPO11 PR1_PRU0_GPI11 MMC0_DAT3 GPIO1_17 0x1304 PADCONFIG_193 A11 PR1_PRU0_GPO12 PR1_PRU0_GPI12 MMC0_DAT2 GPIO1_18 0x1308 PADCONFIG_194 A13 PR1_PRU0_GPO13 PR1_PRU0_GPI13 MMC0_DAT1 GPIO1_19 0x130C PADCONFIG_195 B13 PR1_PRU0_GPO14 PR1_PRU0_GPI14 MMC0_DAT0 GPIO1_20 0x1310 PADCONFIG_196 F13 PR1_PRU0_GPO15 PR1_PRU0_GPI15 MMC0_CLK GPIO1_21 0x1314 PADCONFIG_197 C13 PR1_PRU0_GPO16 PR1_PRU0_GPI16 MMC0_CMD GPIO1_22 0x1318 PADCONFIG_198 E13 PR1_PRU0_GPO17 PR1_PRU0_GPI17 GPIO1_23 0x131C PADCONFIG_199 D12 PR1_PRU0_GPO18 PR1_PRU0_GPI18 PR1_EDC_LATCH0_IN GPIO1_24 eHRPWM4_A 0x1320 PADCONFIG_200 D13 PR1_PRU0_GPO19 PR1_PRU0_GPI19 PR1_EDC_SYNC0_OU GPIO1_25 T eHRPWM4_B 0x1324 PADCONFIG_201 A14 PR1_PRU1_GPO0 PR1_PRU1_GPI0 GPIO1_26 0x1328 PADCONFIG_202 B14 PR1_PRU1_GPO1 PR1_PRU1_GPI1 GPIO1_27 0x132C PADCONFIG_203 C14 PR1_PRU1_GPO2 PR1_PRU1_GPI2 GPIO1_28 0x1330 PADCONFIG_204 E14 PR1_PRU1_GPO3 PR1_PRU1_GPI3 GPIO1_29 0x1334 PADCONFIG_205 D14 PR1_PRU1_GPO4 PR1_PRU1_GPI4 GPIO1_30 0x1338 PADCONFIG_206 A15 PR1_PRU1_GPO5 PR1_PRU1_GPI5 GPIO1_31 0x133C PADCONFIG_207 F14 PR1_PRU1_GPO6 PR1_PRU1_GPI6 GPIO1_32 0x1340 PADCONFIG_208 B15 PR1_PRU1_GPO7 PR1_PRU1_GPI7 GPIO1_33 0x1344 PADCONFIG_209 C15 PR1_PRU1_GPO8 PR1_PRU1_GPI8 0x1348 PADCONFIG_210 D15 PR1_PRU1_GPO9 PR1_PRU1_GPI9 MCBSP_DR GPIO1_35 0x134C PADCONFIG_211 A16 PR1_PRU1_GPO10 PR1_PRU1_GPI10 MCBSP_DX GPIO1_36 0x1350 PADCONFIG_212 E15 PR1_PRU1_GPO11 PR1_PRU1_GPI11 MCBSP_FSX GPIO1_37 0x1354 PADCONFIG_213 B16 PR1_PRU1_GPO12 PR1_PRU1_GPI12 MCBSP_CLKX GPIO1_38 0x1358 PADCONFIG_214 C16 PR1_PRU1_GPO13 PR1_PRU1_GPI13 MCBSP_FSR GPIO1_39 0x135C PADCONFIG_215 D17 PR1_PRU1_GPO14 PR1_PRU1_GPI14 MCBSP_CLKR GPIO1_40 0x1360 PADCONFIG_216 C18 PR1_PRU1_GPO15 PR1_PRU1_GPI15 GPIO1_41 0x1364 PADCONFIG_217 D16 PR1_PRU1_GPO16 PR1_PRU1_GPI16 GPIO1_42 0x1368 PADCONFIG_218 F16 PR1_PRU1_GPO17 PR1_PRU1_GPI17 GPIO1_43 0x136C PADCONFIG_219 E17 PR1_PRU1_GPO18 PR1_PRU1_GPI18 PR1_EDC_LATCH1_IN GPIO1_44 eHRPWM5_A 0x1370 PADCONFIG_220 E16 PR1_PRU1_GPO19 PR1_PRU1_GPI19 PR1_EDC_SYNC1_OU GPIO1_45 T eHRPWM5_B 0x1374 PADCONFIG_221 E18 PR1_MDIO_DATA GPIO1_46 eCAP0_IN_APWM0_O UT 0x1378 PADCONFIG_222 D18 PR1_MDIO_MDCLK GPIO1_47 eCAP1_IN_APWM1_O UT eHRPWM_TZn4 5 Bootstrap ADVANCE INFORMATION ADDRESS OFFSET eHRPWM_SOCA GPIO1_34 eHRPWM_TZn5 eHRPWM_SOCB Terminal Configuration and Functions Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 81 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 4-28. Pin Multiplexing (continued) MUXMODE AND BOOTSTRAP SETTINGS ADDRESS OFFSET REGISTER NAME BALL NUMBER 0 1 ADVANCE INFORMATION 0x1394 PADCONFIG_229 W1 NMIn 0x1398 PADCONFIG_230 V2 LRESETn 0x139C PADCONFIG_231 V1 LRESETNMIENn 0x13AC PADCONFIG_235 Y2 RESETSTATn 0x13B0 PADCONFIG_236 Y3 BOOTCOMPLETE 0x13B4 PADCONFIG_237 M21 SYSCLKOUT 0x13B8 PADCONFIG_238 N5 OBSPLL_LOCK 0x1408 PADCONFIG_258 E19 USB0_DRVVBUS 0x140C PADCONFIG_259 B21 USB1_DRVVBUS 82 2 Terminal Configuration and Functions 3 4 5 Bootstrap Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 4.5 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Connections for Unused Pins This section describes the Unused/Reserved balls connection requirements. NOTE All power balls must be supplied with the voltages specified in Section 5.4, Recommended Operating Conditions, unless otherwise specified in Section 4.3, Signal Descriptions. Table 4-29. Unused Balls Specific Connection Requirements Balls Connection Requirements AC19 / L4 / AD1 / AD4 / AE6 / AE9 / AE12 / M2 / N4 / M1 / N2 / P2 / N1 / T4 / T1 / D24 / C17 / L5 / AC25 / AD24 / L21 / L23 Each of these balls must be connected to GND through a separate external pull resistor if unused L3 / W1 / W3 / K4 / AE2 / AE4 / AD6 / AD9 / AD12 / U5 / W5 / V6 / W4 / V5 / V4 / AD25 / AE24 / K21 / M23 / M3 / P1 These balls must be connected to the corresponding power supply through a separate external pull resistor if unused ADVANCE INFORMATION NOTE The following balls are reserved: AA19 (RSV1) / AB19 (RSV2) / Y20 (RSV3) / W19 (RSV4) / D2 (RSV5) / G3 (RSV7) / F18 (RSV8) / H2 (RSV9) / AA18 (RSV10) / Y19 (RSV11) / Y14 (RSV12) / L1 / K1/ AC18 / AB12 / Y12 These balls must be left unconnected. NOTE The following balls are reserved: L2 (RSV6) These balls must be connected to GND through a separate external pull resistor. NOTE The following balls are reserved: Y1 (RSV13) / AA1 (RSV14) / AB1 (RSV15) / AA2 (RSV16) / AB2 (RSV17) / AC1 (RSV18) These balls must be connected to DVDD18 through a separate external pull resistor. NOTE All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled. Unused signal balls should only be connected to a pad on the PCB. No trace or via should be connected to the pad for an unused signal. If trace or a via is connected to an unused signal pad, an external pulling resistor is required. Failure to included an external resistor could result in a high current state which could damaged the IO cell. NOTE All other unused signal balls without Pad Configuration Register can be left unconnected. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Terminal Configuration and Functions 83 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1)(2)(3) PARAMETERS VSUPPLY (steady-state) Supply voltage ranges VIO (steady-state) Input and output voltage ranges ADVANCE INFORMATION MIN MAX Core CVDD -0.3 1.3 V Core CVDD1 -0.3 1.3 V Analog (AVDDA_DDRPLL, AVDDA_DSSPLL, AVDDA_MAINPLL, AVDDA_NSSPLL, AVDDA_UARTPLL, AVDDA_ICSSPLL, AVDDA_ARMPLL) -0.3 1.98 V 1.35 V (DVDD_DDR) -0.3 1.98 V Analog 1.8 V (DVDD_DDRDLL, VDDAHV, DVDD18) -0.3 2.45 V 3.3 V (DVDD33, DVDD33_USB) -0.3 3.63 V I/O 1.35 V (DVDD_DDR) -0.3 1.98 V I/Os 1.8 V (DVDD_DDRDLL, VDDAHV, DVDD18) -0.3 2.45 V I/Os 3.3 V (DVDD33, DVDD33_USB) -0.3 3.63 V 105 V/s SR Maximum slew rate, all supplies VIO (transient overshoot and undershoot) Input and output voltage ranges (transient overshoot and undershoot)(4) TSTG Storage temperature after soldered onto PC board UNIT 20% overshoot / undershoot for 20% of signal duty cycle -65 V 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4, Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) See I/Os supplied by this power pin in Table 4-1, Pin Attributes. (4) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be VSS - 0.20 × DVDD18. 5.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) Electrostatic discharge (1) Charged-device model (CDM), per JEDEC specification JESD22C101(2) UNIT ±2000 V ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Power-On-Hour (POH) Limits(1)(2)(3) COMMERCIAL TEMPERATURE RANGE JUNCTION TEMP (Tj) 0°C to 90°C EXTENDED TEMPERATURE RANGE LIFETIME (POH) JUNCTION TEMP (Tj) 100000 -40°C to 105°C AUTOMOTIVE TEMPERATURE RANGE LIFETIME (POH) JUNCTION TEMP (Tj) LIFETIME (POH) 100000 Automotive Profile(4) 20000 (1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. (2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures. (3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH. (4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C, and 10%@125°C. 84 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.4 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN(1) NOM MAX(1) 0.9 0.945 V UNIT CVDD Core voltage domain supply 0.855 CVDD1 Core memory array power supply 0.855 0.9 0.945 V AVDDA_DDRPLL DDR PLL supply 1.71 1.80 1.89 V AVDDA_DSSPLL DSS PLL supply 1.71 1.80 1.89 V AVDDA_MAINPLL CORE PLL supply 1.71 1.80 1.89 V AVDDA_NSSPLL NSS PLL supply 1.71 1.80 1.89 V AVDDA_UARTPLL UART PLL supply 1.71 1.80 1.89 V AVDDA_ICSSPLL ICSS PLL supply 1.71 1.80 1.89 V AVDDA_ARMPLL ARM PLL supply 1.71 1.80 1.89 V DVDD_DDRDLL DDR EMIF PHY DLL 1.8V power supply voltage 1.71 1.80 1.89 V VDDAHV SERDES 1.8-V supply 1.71 1.80 1.89 V DVDD_DDR DDR EMIF I/Os 1.35V power supply voltage 1.28 1.35 1.42 V DVDD18 I/O supply 1.71 1.80 1.89 V DVDD33 I/O supply 3.135 3.3 3.435 V DVDD33_USB USB 3.3-V supply 3.135 3.3 3.435 V VSS_OSC_AUDIO AUDOSC Ground 0 V VSS_OSC_SYS SYSOSC Ground 0 V VSS Ground supply 0 V Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications ADVANCE INFORMATION INPUT POWER SUPPLY VOLTAGE RANGE 85 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com over operating free-air temperature range (unless otherwise noted) MIN(1) Operating junction temperature range TJ(2) NOM MAX(1) Automotive –40 125 Extended –40 105 0 90 Commercial UNIT °C OUTPUT POWER SUPPLY VOLTAGE RANGE DDR3_VREFSSTL DDR EMIF Reference Power Supply 0.5 × DVDD_DDR V (1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth. (2) Refer to Section 5.3 for limitations. 5.5 Operating Performance Points This section describes the operating conditions of the device. This section also contains the description of each operating performance point for processor clocks and device core clocks. Table 5-1 describes the standard processor clock-speed characteristics versus the operating performance point of the device. ADVANCE INFORMATION Table 5-1. Supported Max Frequency 5.6 SUBSYSTEM PLL OUTPUT MAX FREQ. (MHz) ARM A15 ARM_PLLOUT 600 C66x CHIP_CLK1 600 DDR EMIF DDR_PLLOUT 400 Power Consumption Summary Table 5-2 summarizes the maximum current ratings at each power terminal. NOTE Data in the Maximum Current Ratings table (Table 5-2) represents worst-case power consumption based on various applications of the device using practical operating conditions. The data primarily benefits the power supply designer trying to understand the worst-case power consumption expected from each power rail. Table 5-2. Maximum Current Ratings at Power Terminals(1) PARAMETER SUPPLY NAME Maximum current rating for core power supply CVDD CVDD1 MAX UNIT Commercial Temperature TBD mA Extended Temperature TBD mA Automotive Temperature TBD mA Commercial Temperature TBD mA Extended Temperature TBD mA Automotive Temperature TBD mA DESCRIPTION Maximum current rating for core memory array power supply DVDD_DDR Maximum current rating for DDR EMIF I/O power supply TBD mA AVDDA_DDRPLL, AVDDA_DSSPLL, AVDDA_MAINPLL, AVDDA_NSSPLL, AVDDA_UARTPLL, AVDDA_ICSSPLL, AVDDA_ARMPLL, DVDD_DDRDLL, VDDAHV, DVDD18 Maximum current rating for 1.8-V power supply TBD mA DVDD33, DVDD33_USB Maximum current rating for 3.3-V power supply TBD mA 86 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (1) Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more information, see the K2G Power Consumption Summary application report. 5.7 Electrical Characteristics NOTE The interfaces or signals described in Table 5-3 through Table 5-8 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions). Table 5-3. HSTL DC Electrical Characteristics over recommended operating conditions (unless otherwise noted)(1) TEST CONDITIONS MIN TYP MAX UNIT BALL NUMBERS: AB4, AA5, AC8, AA9, AA11, AB11, AC11, AC12, Y11, AE12, AD12, AD2, Y4, AC3, AC2, AE3, AA4, AD3, AB3, AA6, Y7, Y6, AC5, AB6, Y5, AC4, AB5, AB7, AB8, AC7, AA7, AA8, AC6, AE7, AD7, AA10, AE10, AD10, AC10, AC9, AB10, AB9, Y8, AD13, AA14, AB13, AD17, AC15, Y15, AC16, AA15, AB16, AE17, AC14, AB15, AC17, AB17, AB14, AA16, AA17, AA12, Y17, Y16, AC13, AE13, Y13, AB18, AA13, Y18 VOH High-level output threshold DVDD_DDR = 1.35V (IOH = 8 mA) DVDD_DDR – 0.4 VOL Low-level output threshold DVDD_DDR = 1.35V (IOH = 8 mA) 0.4 CPAD Pad capacitance (including package capacitance) V 0.2 × DVDD_DDR V 3.44 pF BALL NAMES in MUXMODE 0 (SINGLE-ENDED SIGNALS) (RECEIVER MODE): DDR3_DQM[3:0], DDR3_CB[03:00], DDR3_CBDQM, DDR3_CBDQS_P, DDR3_CBDQS_N, DDR3_D[31:00], DDR3_CEn0, DDR3_BA[2:0], DDR3_A[15:00], DDR3_CASn, DDR3_RASn, DDR3_WEn, DDR3_CKE0, DDR3_ODT0, DDR3_RESETn BALL NUMBERS: AB4, AA5, AC8, AA9, AA11, AB11, AC11, AC12, Y11, AE12, AD12, AD2, Y4, AC3, AC2, AE3, AA4, AD3, AB3, AA6, Y7, Y6, AC5, AB6, Y5, AC4, AB5, AB7, AB8, AC7, AA7, AA8, AC6, AE7, AD7, AA10, AE10, AD10, AC10, AC9, AB10, AB9, Y8, AD13, AA14, AB13, AD17, AC15, Y15, AC16, AA15, AB16, AE17, AC14, AB15, AC17, AB17, AB14, AA16, AA17, AA12, Y17, Y16, AC13, AE13, Y13, AB18, AA13, Y18 VIH High-level input threshold DVDD_DDR = 1.35V DDR3_VREFSSTL + 0.09 V VIL Low-level input threshold DVDD_DDR = 1.35V DDR3_VREFSSTL – 0.09 V VCM Input common-mode voltage CPAD Pad capacitance (including package capacitance) VREFSSTL – 10% DVDD_DDR VREFSSTL + 10% DVDD_DDR V 3.44 pF BALL NAMES in MUXMODE 0 (DIFFERENTIAL SIGNALS) (DRIVER MODE) (SINGLE-ENDED RECEIVER MODE): DDR3_DQS0_P, DDR3_DQS0_N, DDR3_DQS1_P, DDR3_DQS1_N, DDR3_DQS2_P, DDR3_DQS2_N, DDR3_DQS3_P, DDR3_DQS3_N, DDR3_CLKOUT_P0, DDR3_CLKOUT_N0, DDR3_CLKOUT_P1, DDR3_CLKOUT_N1 BALL NUMBERS: AD1, AE2, AD4, AE4, AE6, AD6, AE9, AD9, AE15, AD15, AE16, AD16 VOH High-level output threshold IOH = 0.1 mA VOL Low-level output threshold IOL = 0.1 mA CPAD Pad capacitance (including package capacitance) ZO Output impedance (drive strength) 0.8 × DVDD_DDR 3.3 V 0.2 × DVDD_DDR V 3.44 pF 3.35 34 Ω 50 Ω BALL NAMES in MUXMODE 0 (DIFFERENTIAL SIGNALS) (DIFFERENTIAL RECEIVER MODE): DDR3_DQS0_P, DDR3_DQS0_N, DDR3_DQS1_P, DDR3_DQS1_N, DDR3_DQS2_P, DDR3_DQS2_N, DDR3_DQS3_P, DDR3_DQS3_N, DDR3_CLKOUT_P0, DDR3_CLKOUT_N0, DDR3_CLKOUT_P1, DDR3_CLKOUT_N1 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 87 ADVANCE INFORMATION PARAMETER BALL NAMES in MUXMODE 0 (SINGLE-ENDED SIGNALS) (DRIVER MODE): DDR3_DQM[3:0], DDR3_CB[03:00], DDR3_CBDQM, DDR3_CBDQS_P, DDR3_CBDQS_N, DDR3_D[31:00], DDR3_CEn0, DDR3_BA[2:0], DDR3_A[15:00], DDR3_CASn, DDR3_RASn, DDR3_WEn, DDR3_CKE0, DDR3_ODT0, DDR3_RESETn 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-3. HSTL DC Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NUMBERS: AD1, AE2, AD4, AE4, AE6, AD6, AE9, AD9, AE15, AD15, AE16, AD16 VSWING Input voltage swing DVDD_DDR = 1.35V VCM Input common-mode voltage CPAD Pad capacitance (including package capacitance) VREFSSTL – 10% DVDD_DDR 3.3 DVDD_DDR + 0.4 V VREFSSTL + 10% DVDD_DDR V 3.44 pF 3.35 (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Table 5-4. I2C OPEN DRAIN DC Electrical Characteristics over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN TYP MAX UNIT BALL NAMES in Mode 0: I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, I2C2_SCL, I2C2_SDA ADVANCE INFORMATION BALL NUMBERS: U5, W5, V6, W4, V5, V4 (I2C STANDARD MODE – 3.3 V) 0.7 × VDDS(2) VDDS(2) + 0.5 V – 0.5 0.3 × VDDS(2) V 0.05 × VDDS(2) — V – 10 10 µA 8 µA 10 pF 400 pF VIH Input high-level threshold VIL Input low-level threshold VHYS Hysteresis IIN Input current at each I/O pin with an input voltage between 0.1 × VDDS and 0.9 × VDDS IOZ IOZ (IPAD current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the RX + weak pullup or pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ. CIN Input capacitance Cb Capacitive load for each bus line VOL3 Output low-level threshold open-drain at 3-mA sink current 0 IOLmin Low-level output current at VOL = 0.4 V 3 mA IOLmin Low-level output current at VOL = 0.6 V for full drive load (400 pF and 400 KHz) 6 mA tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 400 pF — 0.4 V 250 ns 0.7 × VDDS(2) VDDS(2) + 0.5 V – 0.5 0.3 × VDDS(2) V 0.05 × VDDS(2) — V – 10 10 µA 8 µA 10 pF 400 pF (I2C FAST MODE – 3.3 V) VIH Input high-level threshold VIL Input low-level threshold VHYS Hysteresis IIN Input current at each I/O pin with an input voltage between 0.1 × VDDS and 0.9 × VDDS IOZ IOZ (IPAD current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the RX + weak pullup or pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ. CIN Input capacitance Cb Capacitive load for each bus line VOL3 Output low-level threshold open-drain at 3-mA sink current 0 IOLmin Low-level output current at VOL = 0.4 V 3 mA IOLmin Low-level output current at VOL = 0.6 V for full drive load (400 pF and 400 KHz) 6 mA 88 Specifications 0.4 V Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-4. I2C OPEN DRAIN DC Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted)(1) PARAMETER tOF MAX UNIT Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 200 pF (proper external resistor value should be used as per I2C spec) 20 + 0.1 × CB MIN TYP 250 ns Output fall time from VIHmin to VILmax with a bus capacitance CB from 300 pF to 400 pF (proper external resistor value should be used as per I2C spec) 40 290 (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. ADVANCE INFORMATION (2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [11] column. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 89 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-5. Analog OSC Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN TYP MAX UNIT 1.8-V MODE BALL NAMES in Mode 0: AUDOSC_IN, AUDOSC_OUT, SYSOSC_IN, SYSOSC_OUT BALL NUMBERS: C17, A17, AC19, AE19 VIH 0.65 × VDDS(2) Input high-level threshold VIL Input low-level threshold COSC Crystal Shunt capacitance CLC Load Capacitance 12 TDC Output duty cycle on core port 45 V (2) V 4 pF 24 pF 55 % 0.35 × VDDS 50 (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. (2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [11] column. ADVANCE INFORMATION Table 5-6. LVDS Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN TYP MAX UNIT 1.8-V MODE BALL NAMES in Mode 0: SYSCLK_P, SYSCLK_N, DDR_CLK_N, DDR_CLK_P, CPTS_REFCLK_N, CPTS_REFCLK_P, OBSCLK_N, OBSCLK_P BALL NUMBERS: AD25, AC25, AD24, AE24, L21, K21, L1, K1 VIN (DC) Single-Ended Input Voltage VCM Common mode input voltage VIH, VIL (DC) Input decision threshold CPAD Pad capacitance (including package capacitance) VDDS(2) 0 0.1 VDDS (2) – 0.1 Vcm ± 100 V V mV 5 pF (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. (2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [11] column. Table 5-7. MLB LVDS Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted)(1) PARAMETER MIN TYP MAX UNIT 1.8-V MODE BALL NAMES in Mode 0: MLBP_SIG_P, MLBP_SIG_N, MLBP_DAT_P, MLBP_DAT_N, MLBP_CLK_P, MLBP_CLK_N BALL NUMBERS: L24, M24, K23, K22, M23, L23 VIH, VIL Input decision threshold VOD Differential output voltage (measured with 50 Ω resistor between positive and negative pads) Vcm ± 50 300 500 mV VCM Common mode output voltage 1.0 1.5 V CPAD Pad capacitance (including package capacitance) 5 pF mV (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. 90 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-8. LVCMOS DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) (1) PARAMETER MIN TYP MAX UNIT 1.8-V MODE BALL NAMES: ALL others BALL NUMBERS: ALL others 0.65 × VDDS(2) VIH Input high-level threshold VIL Input low-level threshold VHYS Input hysteresis voltage VOH Output high-level threshold (IOH = - 2 mA) VOL Output low-level threshold (IOL = 2 mA) IDRIVE Pin Drive strength at PAD Voltage = 0.45V or VDDS 0.45V IIN Input current at each I/O pin 3 µA IOZ IOZ (IPAD current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the RX + weak pullup or pulldown leakage. PAD is swept from VSS to VDDS and the Max(I(PAD)) is measured and is reported as IOZ. 3 µA IIN with pulldown Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA Input current at each I/O pin with weak pullup enabled measured when PAD = VSS 60 120 200 µA enabled CPAD Pad capacitance (including package capacitance) 4 pF ZO Output impedance (drive strength) IIN with pullup 228 VDDS (2) 260 V mV – 0.45 V 0.45(3) 7 V mA 40 ADVANCE INFORMATION enabled V 0.35 × VDDS(2) Ω 3.3-V MODE VIH Input high-level threshold 2 VIL Input low-level threshold VHYS Input hysteresis voltage VOH Output high-level threshold (IOH = 100 µA) VOL Output low-level threshold (IOL = 100 µA) IDRIVE Pin Drive strength at PAD Voltage = 0.45V or VDDS 0.45V IIN IOZ IWEAK PU/PD 0.8 (3) (4) V 200 VDDS (2) V mV – 0.2 V 0.2 (3) V 6 mA Input current at each I/O pin 10 µA IOZ (IPAD current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the RX + weak pullup or pulldown leakage. PAD is swept from VSS to VDDS and the Max(I(PAD)) is measured and is reported as IOZ. 10 µA Weak Pull-Up/ Pull-Down Current (when PAD = VDDS for weak pull down and PAD = VSS for weak pullup) 100 µA ILEAKAGE Leakage Current(BIDI) 80 µA IIN with pulldown Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA Input current at each I/O pin with weak pullup enabled measured when PAD = VSS 60 120 200 µA enabled CPAD Pad capacitance (including package capacitance) 4 pF ZO Output impedance (drive strength) 50 Ω enabled IIN with pullup 40 (1) For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. (2) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [11] column. (3) Meets the 1.8V JEDEC specification. (4) Meets the 3.3V JEDEC specification. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 91 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.7.1 www.ti.com USB0_PHY and USB1_PHY DC Electrical Characteristics NOTE USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable. 5.7.2 SERDES/CML DC Electrical Characteristics NOTE The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 2.0. ADVANCE INFORMATION 92 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.8 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Thermal Resistance Characteristics for ZBB Package This section provides the thermal resistance characteristics for the ZBB package used on this device. For reliability and operability concerns, the maximum junction temperature of the Device has to be at or below the TJ value identified in Section 5.4 Recommended Operating Conditions. NOTE Power dissipation of 1.5 W and an ambient temperature of 85ºC is assumed for ZBB package. NO. NAME DESCRIPTION °C/W(1) AIR FLOW (m/s)(2) T1 RΘJC Junction-to-case 6.3 N/A T2 RΘJB Junction-to-board 7.1 N/A T3 RΘJA Junction-to-free air 14.3 0.00 11.4 1.00 RΘJMA Junction-to-moving air 10.6 2.00 T6 10.1 1.00 T7 0.19 0.00 0.31 1.00 0.39 2.00 T10 0.5 3.00 T11 6.29 0.00 T12 5.89 1.00 5.81 2.00 5.78 3.00 T4 T5 T8 T9 T13 ΨJT ΨJB Junction-to-package top Junction-to-board T14 ADVANCE INFORMATION It is recommended to perform thermal simulations at the system level with the worst case device power consumption(3). (1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: – JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) – JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements (2) m/s = meters per second. (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 93 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.9 www.ti.com Timing and Switching Characteristics The timing parameter symbols used in Section 5.9 are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 5-9: Table 5-9. Timing Parameters Subscripts ADVANCE INFORMATION 94 Specifications SYMBOL PARAMETER c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level F Fall time H High L Low R Rise time V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.9.1 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Power Supply Sequencing This section describes the power-up sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable. ADVANCE INFORMATION Figure 5-1 describes the Power-Up Sequencing of the device. Figure 5-1. Power-Up Sequencing (1) Power-up begins by powering up DVDD33 first. (2) PORn is asserted and held until all supplies are within their specified recommended operating range. (3) Oscillator Power-up time (approx. 1-2ms). (4) BOOTMODE pins are latched at rising edge of PORn (synchronously using SYSOSC_IN / OUT or SYSCLK_P / N). (5) RESETSTATn and BOOTCOMPLETE are outputs for informational purposes. (6) Oscillator stabilization time (approx. 2ms). (7) If externally sourced, must be present prior to PORn. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 95 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.9.2 www.ti.com Reset Timing 5.9.2.1 Reset Electrical Data/Timing For more details about features and additional description information on the subsystem multiplexing signals, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-10, Table 5-11, Figure 5-2, and Figure 5-3 present the reset timing requirements and switching characteristics. Table 5-10. Reset Timing Requirements NO. PARAMETER MIN MAX UNIT PORn Pin RST1 tw(PORn) Pulse width - pulse width PORn low 500C(1) ns 500C(1) ns RESETn Pin RST2 tw(RESETn) Pulse width - pulse width RESETn low (1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL. ADVANCE INFORMATION Table 5-11. Reset Switching Characteristics NO. PARAMETER MIN MAX UNIT PORn Pin RST3 td(CVDD - PORn) RST4 td(PORn - Delay time - PORn high after CVDD/CVDD1 ramped Delay time - RESETSTATn high after PORn high 2 ms (1) ns 50000C(1) ns 50000C RESETSTATn) RESETn Pin RST5 td(RESETn- Delay time - RESETSTATn high after RESETn high RESETSTATn) (1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL. RST1 PORn RESETn RST4 RESETSTATn Figure 5-2. PORn Reset Timing PORn RST2 RESETn RST5 RESETSTATn Figure 5-3. Soft/Hard Reset Timing 96 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-12 and Figure 5-4 present the boot configuration timing requirements. Table 5-12. Boot Configuration Timing Requirements NO. PARAMETER MIN MAX UNIT BC1 tsu(BOOTMODE-PORn) Setup time – BOOTMODE valid before PORn asserted 12C(1) ns BC2 th(PORn-BOOTMODE) Hold time – BOOTMODE valid after PORn asserted 12C(1) ns (1) C = 1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL. BC1 PORn BOOTMODE[15:0] BC2 5.9.3 Clock Specifications 5.9.3.1 Input Clocks / Oscillators Various external clock inputs are needed to drive the device. Summary of these input clock signals are: • SYSOSC_IN / SYSOSC_OUT - external main crystal interface pins connected to internal oscillator which sources reference clock for all the PLLs. When internal oscillator is bypassed, reference clock input must be provided on SYSOSC_IN pin by an external clock source/generator. • SYSCLK_P / SYSCLK_N - optional pins to provide reference clock input to the PLLs. • DDR_CLK_P / DDR_CLK_N - optional clock input to DDR EMIF PLL. • AUDOSC_IN / AUDOSC_OUT - optional audio crystal interface pins connected to secondary internal oscillator dedicated for Audio Applications. This clock feeds McASPs and McBSP. • PCIE_CLK_P / PCIE_CLK_N - SERDES reference clock for PCIESS. • USB0_XO / USB1_XO - optional USB0_PHY / USB1_PHY reference clock input. • CPTS_REFCLK_P / CPTS_REFCLK_N - CPTS reference clock inputs. Figure 5-5 shows the external input clock sources to peripherals. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 97 ADVANCE INFORMATION Figure 5-4. Boot Configuration Timing 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com DEVICE MAINPLL_OD_SEL SYSCLKSEL Selects Main PLL output divide-by-2 System Clock Select SYSCLK_P Optional pins to provide reference clock input to the PLLs. SYSCLK_N SYSOSC_IN SYSOSC_OUT RESETn RESETFULLn ADVANCE INFORMATION PORn BOOTMODE[15:0] External main crystal interface pins connected to internal oscillator which sources reference clock for all the PLLs. Device Warm Reset Input Device Cold Reset Input Power ON Reset Boot Mode Configuration / devices select DDR_CLK_P Optional clock input to DDR3 PLL DDR_CLK_N AUDOSC_IN AUDOSC_OUT Optional audio crystal interface pins connected to secondary internal oscillator dedicated for Audio Applications. This clock feeds McASPs and McBSP. PCIE_CLK_P SerDes reference clock for PCIESS PCIE_CLK_N USB0_XO Optional USB0/USB1 PHY reference clock input USB1_XO CPTS_REFCLK_P CPTS reference clock input CPTS_REFCLK_N SPRS932_CLOCK_01 Figure 5-5. Input Clocks Interface The system clock may be sourced either from the SYSOSC_* pins or from an external source via the SYSCLK_* pins, selection is via SYSCLKSEL. For more information about SYSTEM OSC, see section Clock Management in chapter Device Configuration of the device TRM. 5.9.3.1.1 OSC0 External Crystal An external crystal is connected to the device pins (SYSOSC_IN and SYSOSC_OUT). In that case the SYSCLK_P and SYSCLK_N pins are left unused. Figure 5-6 describes the crystal implementation. 98 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Device SYSOSC_IN SYSOSC_OUT VSS_OSC_SYS Rd (Optional) Crystal Cf2 Cf1 SPRS932_CLOCK_02 ADVANCE INFORMATION Figure 5-6. Crystal Implementation(1) (1) Rd=0 Ω for no damping case. NOTE The load capacitors, Cf1 and Cf2 in Figure 5-6, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the SYSOSC_IN and SYSOSC_OUT pins. CL= Cf1Cf2 (Cf1+Cf2) SPRS932_CLOCK_03 Figure 5-7. Load capacitance equation Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 99 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-13 summarizes the required electrical constraints. Table 5-13. OSC0 Crystal Circuit Requirements NAME DESCRIPTION MIN TYP MAX UNIT fc Parallel resonance crystal frequency 19.2, 24, 25, 26 Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF ESR(Cf1,Cf2) Crystal ESR 100 Ω 19.2 MHz, 24 MHz, 25 MHz, 26 MHz TBD pF 19.2 MHz, 24 MHz, 25 MHz TBD pF 26 MHz TBD pF 19.2 MHz, 24 MHz, 25 MHz TBD pF 26 MHz TBD pF 19.2 MHz, 24 MHz, 25 MHz TBD pF ESR=30 Ω ESR=50 Ω CO Crystal shunt capacitance ESR=65 Ω ESR=100 Ω ADVANCE INFORMATION 26 MHz MHz TBD LM Crystal motional inductance for fp = 24 MHz TBD CM Crystal motional capacitance TBD fa(SYSOSC_IN) Frequency accuracy (1) , SYSOSC_IN pF mH fF TBD ppm (1) Frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency stability across worst case environmental conditions, and frequency shifts due to aging. When selecting a crystal, the system design must consider the temperature and aging characteristics of a crystal based on the worst case environment and life expectancy of the system. 5.9.3.1.2 External Single-ended Input Clock A LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the reference clock source for all the PLLs. The external connections to support this are shown in Figure 5-8. The SYSOSC_IN pin is connected to the LVCMOS-Compatible clock source. The SYSOSC_OUT pin is left unconnected. The VSS_OSC_SYS pin is connected to board ground (VSS). Device SYSOSC_IN SYSOSC_OUT VSS_OSC_SYS NC SPRS932_CLOCK_06 Figure 5-8. LVCMOS-Compatible Clock Input Table 5-14 summarizes the SYSOSC_IN input clock electrical characteristics. 100 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-14. SYSOSC_IN Input Clock Electrical Characteristics—Bypass Mode NAME f DESCRIPTION MIN Frequency TYP MAX UNIT 19.2, 24, 25, 26 MHz CIN Input capacitance TBD TBD TBD pF IIN Input current (3.3V mode) TBD TBD TBD µA Table 5-15 details the SYSOSC_IN input clock timing requirements. Table 5-15. SYSOSC_IN Input Clock Timing Requirements DESCRIPTION MIN CK0 fc(SYSOSC_IN) Frequency, SYSOSC_IN CK1 tw(SYSOSC_IN) Pulse duration, SYSOSC_IN low or high TYP MAX 19.2, 24, 25, 26 TBD (1) UNIT MHz TBD ns tj(SYSOSC_IN) Period jitter , SYSOSC_IN TBD ns tR(SYSOSC_IN) Rise time, SYSOSC_IN TBD ns tF(SYSOSC_IN) Fall time, SYSOSC_IN TBD ns fa(SYSOSC_IN) Frequency accuracy(2), SYSOSC_IN TBD ppm (1) Period jitter is meant here as follows: – The maximum value is the difference between the longest measured clock period and the expected clock period – The minimum value is the difference between the shortest measured clock period and the expected clock period (2) Crystal characteristics should account for tolerance+stability+aging. CK0 CK1 CK1 SYSOSC_IN SPRS932_CLOCK_07 Figure 5-9. SYSOSC_IN Input Clock 5.9.3.1.3 External Differential Input Clock The optional LVDS-compatible clock input can be used instead of the internal oscillator to provide the system LVDS clock. The external connections to support this are shown in Figure 5-10. The SYSCLK_P and SYSCLK_N pins are connected to the LVDS-compatible clock source. The SYSOSC_IN and SYSOSC_OUT pins are left unconnected. Device SYSCLK_P SYSCLK_N SYSOSC_IN SYSOSC_OUT NOT USED NOT USED SPRS932_CLOCK_04 Figure 5-10. LVDS-Compatible Clock Input Table 5-16 summarizes the SYSCLK_P/N input clock electrical characteristics. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 101 ADVANCE INFORMATION NAME 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-16. SYSCLK_P/N Input Clock Electrical Characteristics—Bypass Mode NAME f DESCRIPTION MIN TYP Frequency MAX UNIT 19.2, 24, 25, 26 MHz CIN Input capacitance TBD TBD TBD pF IIN Input current TBD TBD TBD µA Table 5-17 details the SYSCLK_P/N input clock requirements. Table 5-17. SYSCLK_P/N Input Clock Requirements NAME DESCRIPTION CK0 fc(SYSCLK_P/N) CK1 MIN Frequency, SYSCLK_P/N TYP MAX 19.2, 24, 25, 26 0.48 × SYSCLK_P/N UNIT MHz 0.52 × SYSCLK_P/N ns 0.015 × SYSCLK_P/N ns ns ADVANCE INFORMATION tw(SYSCLK_P/N) Pulse duration, SYSCLK_P/N low or high tj(SYSCLK_P/N) Period jitter(1), SYSCLK_P/N tR(SYSCLK_P/N) Rise time, SYSCLK_P/N TBD tF(SYSCLK_P/N) Fall time, SYSCLK_P/N TBD ns fa(SYSCLK_P/N) Frequency accuracy(2), SYSCLK_P/N TBD ppm (1) Period jitter is meant here as follows: – The maximum value is the difference between the longest measured clock period and the expected clock period – The minimum value is the difference between the shortest measured clock period and the expected clock period (2) Frequency accuracy should include all components of frequency error - initial frequency tolerance, frequency stability across worst case environmental conditions, and frequency shifts due to aging. CK0 CK1 CK1 SYSCLK_P SYSCLK_N SPRS932_CLOCK_05 Figure 5-11. SYSCLK_P/N Input Clock 5.9.3.2 Output Clocks The device provides several system clock outputs. Summary of these output clock outputs are as follows: • CLKOUT – CLKOUT port provides an option to output 50 MHz or 25 MHz clock. This clock can be used as a reference clock for RMII or MII Ethernet companion devices. • SYSCLKOUT – SYSCLK1 from the main PLL controller is divided by 6 and output as a LVCMOS clock source (SYSCLKOUT). This output can be used to test if the main chip clock is functioning or not. SYSCLKOUT cannot be used as a clock source for external devices on the board. This is for test and debug purpose only. 102 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.9.3.3 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 PLLs Power is supplied to the PLL by internal regulators that derive power from the off-chip power-supply. Most of the Device is driven by the output from the main PLL except the following items: • ARM subsystem has its own dedicated PLL driven by the output of the SYSCLKSEL mux. • DDR subsystem has its own dedicated PLL to drive DDR EMIF and DDR EMIF PHY. • ICSS has clocks from several PLLs - UART_PLL to generate constant 192 MHz clock, ICSS_PLL to generate 225 MHz core clock and NSS/IEP_PLL to generate 200 MHz ICSS core clock and 250 MHz Ethernet clocks. • DSS has its own dedicated PLL, to generate Pixel Clock. • PCIESS require separate ref clocks to drive SERDES PHYs. • USB supports optional external ref clock input. NOTE For more information, see: • Device Configuration / Clock Management / PLLs section • Peripherals / Display Subsystem Overview section of the device TRM. NOTE The input reference clocks (SYSCLK_P/N or SYSOSC_IN/OUT) are specified and the lock time is guaranteed by the PLL controller, as documented in the Device Configuration chapter of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 103 ADVANCE INFORMATION There are total seven Phase Locked Loops (PLLs) in the device: • MAIN_PLL with PLL_CONTROLLER: (SoC, Peripherals) The Main PLL — which is used to drive the switch fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the various clock divisions, gating, and synchronization. • ARM_PLL: The ARM PLL, which is used to drive the ARM. • DSS_PLL: (Display Subsystem) The DSS PLL, which is used to drive the DSS. • UART_PLL: (ICSS UART) The UART PLL, which is used to drive the UART in ICSS, QSPI, MMC/SD and USB. • ICSS_PLL: (ICSS PRUs) The ICSS PLL, which is used to drive the ICSS. • NSS/IEP_PLL: (NSS, ICSS) The NSS/IEP PLL, which is used to drive the NSS_L and ICSS. • DDR_PLL: (DDR EMIF / DDR PHY) The DDR PLL is used to drive the DDR EMIF PHY for the DDR EMIF. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 5.9.3.3.1 DDR_PLL Settings Table 5-18 lists the recommended and supported values to set up the DDR3-800 configurations. Table 5-18. DDR3-800 Configurations Parameter Value Configuration Register Register Value Configuration 1 Reference Clock Input 19.2 MHz N/A N/A PLL Reference Divider 1 BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD 0 PLL Multiplier 167 BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM 166 PLL Output Divider 16 BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD 15 PHY PLL Frequency Select (In DDR3 Initialization) N/A DDR_PHY_PLLCR[19-18] FRQSEL 0x3 PHY PLL Charge Pump Proportional Current Control (In DDR3 Initialization) N/A DDR_PHY_PLLCR[16-13] CPPC 0xE N/A Configuration 2 ADVANCE INFORMATION Reference Clock Input 24 MHz N/A PLL Reference Divider 1 BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD 0 PLL Multiplier 133 BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM 132 PLL Output Divider 16 BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD 15 PHY PLL Frequency Select (In DDR3 Initialization) N/A DDR_PHY_PLLCR[19-18] FRQSEL 0x3 PHY PLL Charge Pump Proportional Current Control (In DDR3 Initialization) N/A DDR_PHY_PLLCR[16-13] CPPC 0xE 25 MHz N/A N/A Configuration 3 Reference Clock Input PLL Reference Divider 1 BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD 0 PLL Multiplier 128 BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM 127 PLL Output Divider 16 BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD 15 PHY PLL Frequency Select (In DDR3 Initialization) N/A DDR_PHY_PLLCR[19-18] FRQSEL 0x3 PHY PLL Charge Pump Proportional Current Control (In DDR3 Initialization) N/A DDR_PHY_PLLCR[16-13] CPPC 0xE Configuration 4 Reference Clock Input 26 MHz N/A N/A PLL Reference Divider 1 BOOTCFG_DDR3A_PLL_CTL0[5-0] PLLD 0 PLL Multiplier 123 BOOTCFG_DDR3A_PLL_CTL0[18-6] PLLM 122 PLL Output Divider 16 BOOTCFG_DDR3A_PLL_CTL0[22-19] CLKOD 15 PHY PLL Frequency Select (In DDR3 Initialization) N/A DDR_PHY_PLLCR[19-18] FRQSEL 0x3 PHY PLL Charge Pump Proportional Current Control (In DDR3 Initialization) N/A DDR_PHY_PLLCR[16-13] CPPC 0xE 5.9.3.3.2 DLL Characteristics Table 5-19 summarizes the DLL characteristics of recommended operating conditions. Table 5-19. DLL Characteristics NAME MIN TYP MAX finput Input clock frequency (EMIF_DLL_FCLK) TBD TBD TBD MHz tlock Lock time TBD TBD TBD cycles Relock time (a change of the DLL frequency implies that DLL must relock) TBD TBD TBD cycles trelock 104 DESCRIPTION Specifications UNIT Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.9.3.4 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 System Clocks Operating Frequency Ranges Table 5-20 lists the operating frequency ranges for the system clocks of the device. Table 5-20. System Clocks Operating Frequency Range System Clocks (1) Bypass Min (MHz) Bypass Max (MHz) Minimum Operating Frequency (MHz) Main PLL 19.2 26 400 ARM PLL 19.2 26 200 DSS PLL 19.2 26 74.25 NSS/IEP PLL 19.2 26 600 UART PLL 19.2 26 384 ICSS PLL 19.2 26 200 DDR PLL 19.2 26 303 (2) (3) (1) Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only. (2) Interconnect clock on DSS is CPU/4. This will range from 100 MHz to 250 MHz. 5.9.3.5 Device Inputs and Outputs Module Clocks Frequencies Table 5-21 lists the clock inputs to the device. Table 5-21. Clock Inputs to the Device Clock Frequency (MHz) (2) I/O Buffer Type Duty Cycle (%) Jitter Requirements Min Max Min / Max Requirements (ps) Type and Condition(1) SYSOSC_IN / SYSOSC_OUT Internal HF Oscillator 19.2 26 45/55 50 Peak-to-peak, period DDR_CLK_N / DDR_CLK_P LVDS 19.2 26 45/55 100 Peak-to-peak, period CPTS_RFCLK_N / CPTS_RFCLK_P LVDS 30.72 307.2 45/55 100 Peak-to-peak, period SYSCLK_N / SYSCLK_P LVDS 19.2 26 45/55 100 Peak-to-peak, period AUDOSC_IN / AUDOSC_OUT Internal HF Oscillator 11.2896 49.152 45/55 100 Peak-to-peak, period PCIE_CLK_N PCIE_CLK_P SERDES/CML 100 45/55 3.1 RMS Jitter from 1.5 - 200MHz (3) USB0_XO / USB1_XO USB_PHY (4) 9.6 50 40/60 100 Peak-to-peak, period TCK LVCMOS DC 35 40/60 N/A RMII_REFCLK LVCMOS 50 50 40/60 50 Peak-to-peak, period RGMII_RXC LVCMOS 2.5 125 40/60 100 Peak-to-peak, period RGMII_TXC LVCMOS 2.5 125 40/60 100 Peak-to-peak, period MCASPx_AHCLKR MCASPx_AHCLKX LVCMOS N/A 50 (5) 40/60 100 Peak-to-peak, period MCASPx_ACLKR MCASPx_ACLKX LVCMOS N/A 50 (5) 40/60 100 Peak-to-peak, period MCASPx_AFSR MCASPx_AFSX LVCMOS 0.008 Configurable N/A MCBSP_CLKR MCBSP_CLKX LVCMOS N/A 40/60 100 0.192 50 (6) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Peak-to-peak, period Specifications 105 ADVANCE INFORMATION (3) When Main PLL is configured to 400 MHz mode, DSS can only support a Max Pixel clock of 74.25 MHz. For lower resolution Displays the DSS clock can be lower than 74.25 MHz. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-21. Clock Inputs to the Device (continued) Clock Frequency (MHz) (2) I/O Buffer Type Duty Cycle (%) Jitter Requirements Min Max Min / Max Requirements (ps) Type and Condition(1) MLB_CLK (3-pin mode) LVCMOS 11.2896 49.152 40/60 100 Peak-to-peak, period MLB_CLK_N MLB_CLK_P (6-pin mode) LVCMOS 11.2896 98.308 40/60 100 Peak-to-peak, period SPIx_CLK LVCMOS N/A 50 40/60 100 Peak-to-peak, period QSPI_RCLK LVCMOS N/A 96 40/60 100 Peak-to-peak, period I2Cx_SCL LVCMOS N/A 0.4 40/60 N/A (1) Over 12 kHz to 20 MHz bandwidth unless otherwise noted. (2) Frequency tolerance: +/- 100ppm, except for RMII_REFCLK frequency tolerance is +/- 50ppm and USB_CLK. USB_CLK frequency tolerance is +/- 400ppm. (3) After applying a filter function. See section Peripheral Component Interconnect Express Subsystem (PCIe SS) in chapter Peripherals of the device TRM for full refclk requirements. ADVANCE INFORMATION (4) Jitter requirement for direct pin connection to the USB Oscillator pads. (5) The minimum pulse width for McASP clocks is (Period/2 - [2.5ns]). (6) The minimum pulse width for McBSP clocks is (Period/2 - [2.5ns]). Table 5-22 lists the clock outputs from the device. Table 5-22. Clock Outputs from the Device Clock I/O Buffer Type DDR3_CLKOUT_Nx / DDR3_CLKOUT_Px SYSCLKOUT (3) HSTL Frequency (MHz) (2) Duty Cycle (%) Jitter Requirements Min Max Min / Max Requirements (ps) Type and Condition(1) 303 400 45/55 100 Peak-to-peak, period 166.67 40/60 100 Peak-to-peak, period 125 40/60 100 Peak-to-peak, period 40/60 100 Peak-to-peak, period LVCMOS RGMII_TXC LVCMOS 2.5 MDIO_CLK LVCMOS 2.5 MCASPx_AHCLKR MCASPx_AHCLKX LVCMOS 50 40/60 100 Peak-to-peak, period MCASPx_ACLKR McASPx_ACLKX LVCMOS 50 40/60 100 Peak-to-peak, period MCASPx_AFSR MCASPx_AFSX LVCMOS 0.192 Configurable N/A MCBSP_CLKR MCBSP_CLKX LVCMOS 50 40/60 100 Peak-to-peak, period MMC0_CLK MMC1_CLK LVCMOS 96 40/60 100 Peak-to-peak, period SPIx_CLK LVCMOS 50 40/60 100 Peak-to-peak, period QSPI_CLK LVCMOS 96 40/60 100 Peak-to-peak, period 106 0.008 I2Cx_SCL LVCMOS 0.4 40/60 N/A GPMC_CLK LVCMOS 100 40/60 N/A DSS_PCLK LVCMOS N/A 150 40/60 N/A CLKOUT LVCMOS 25 50 40/60 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (1) Over 12 kHz to 20 MHz bandwidth unless otherwise noted. (2) Frequency tolerance: +/- 100ppm. (3) SYSCLKOUT cannot be used as a clock source for external devices on the board. This is for test and debug purpose only. 5.9.3.6 Recommended Clock and Control Signal Transition Behavior All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are more susceptible to glitches due to noise, and special care must be taken for slow input clocks. 5.9.3.7 Interface Clock Specifications 5.9.3.7.1 Interface Clock Terminology The interface clock is used at the system level to sequence the data and to control transfers accordingly with the interface protocol. The two interface clock characteristics are: • The maximum clock frequency • The maximum operating frequency The interface clock frequency documented here is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the Device IC and does not take into account any system consideration (PCB, peripherals). The system designer must take into account these system considerations and the Device IC timing characteristics to properly define the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 107 ADVANCE INFORMATION 5.9.3.7.2 Interface Clock Frequency 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.9.4 www.ti.com Peripherals 5.9.4.1 DCAN For more details about features and additional description information on the device Controller Area Network Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-23, Table 5-24, and Figure 5-12 present timing requirements and switching characteristics for DCANx Interface. Table 5-23. Timing Requirements for DCANx Receive NO. MIN CAN1 fbaud(baud) Maximum programmable baud rate tw(RX) Pulse duration, receive data bit MAX UNIT 1 H - 2(1) H + 2(1) Mbps ns (1) H = period of baud rate, 1/programmed baud rate. Table 5-24. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit ADVANCE INFORMATION NO. PARAMETER CAN2 fbaud(baud) Maximum programmable baud rate tw(TX) Pulse duration, transmit data bit MIN MAX UNIT 1 H - 2(1) H + 2(1) Mbps ns (1) H = period of baud rate, 1/programmed baud rate. CAN1 DCANx_RX CAN2 DCANx_TX Figure 5-12. DCANx Timings For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals of the device TRM. 5.9.4.2 DSS For more details about features and additional description information on the device Display Subsystem – Video Output Ports, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-25 and Figure 5-13 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-25. DPI Video Output Switching Characteristics NO. 108 PARAMETER D1 tc(clk) Cycle time, output pixel clock DSS_PCLK D2 tw(clkL) D3 MIN MAX UNIT 6.67 ns Pulse duration, output pixel clock DSS_PCLK low P(1) × 0.45 ns tw(clkH) Pulse duration, output pixel clock DSS_PCLK high P(1) × 0.45 ns D4 tt(clk) Transition time, output pixel clock DSS_PCLK (10%-90%) TBD TBD ns D5 td(clk-ctlV) Delay time, output pixel clock DSS_PCLK transition to output data DSS_DATA[23:0] valid -1.39 1.15 ns Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-25. DPI Video Output Switching Characteristics (continued) NO. PARAMETER D6 td(clk-dV) Delay time, output pixel clock DSS_PCLK transition to output control signals DSS_VSYNC, DSS_HSYNC, DSS_DE, and DSS_FID valid MIN MAX UNIT -1.39 1.15 ns (1) P = output DSS_PCLK period in ns. D2 D1 D3 D4 Falling-edge Clock Reference DSS_PCLK Rising-edge Clock Reference DSS_PCLK D6 DSS_VSYNC ADVANCE INFORMATION D6 DSS_HSYNC D5 DSS_DATA[23:0] data_1 data_2 data_n D6 DSS_DE D6 DSS_FID even odd SWPS049-018 (1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. (2) The polarity and the pulse width of DSS_HSYNC and DSS_VSYNC are programmable, refer to section Display Subsystem (DSS) in chapter Peripherals of the device TRM. (3) The DSS_PCLK frequency can be configured, refer to section Display Subsystem in chapter Peripherals of the device TRM. Figure 5-13. DPI Video Output 5.9.4.3 (1)(2)(3) DDR EMIF For more details about features and additional description information on the device DDR3L Memory Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. The device has a dedicated interface to DDR3L SDRAM. It supports JEDEC JESD79-3F and JESD79-3-1 standards compliant DDR3L SDRAM devices with the following features: • 16-bit or 32-bit data path to external SDRAM memory • Memory device capacity: Up to 4 GB address space available over one chip select 5.9.4.4 EMAC For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 109 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 5.9.4.4.1 EMAC MDIO Interface Timings Table 5-26, Table 5-27, and Figure 5-14 present timing requirements for MDIO. Table 5-26. Timing Requirements for MDIO Input NO. PARAMETER MIN MDIO1 tsu(MDIO_MDC) Setup time, MDIO_DATA valid before MDIO_CLK high MDIO2 th(MDIO_MDC) Hold time, MDIO_DATA valid after MDIO_CLK high MAX UNIT 90 ns 0 ns Table 5-27. Switching Characteristics Over Recommended Operating Conditions for MDIO Output NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO_CLK 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO_CLK high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO_CLK low 160 MDIO6 tt(MDC) Transition time, MDIO_CLK MDIO7 td(MDC_MDIO) Delay time, MDIO_CLK High to MDIO_DATA valid ns 10 5 ns 390 ns ADVANCE INFORMATION MDIO3 MDIO4 MDIO5 MDIO_CLK MDIO6 MDIO6 MDIO1 MDIO2 MDIO_DATA (input) MDIO7 MDIO_DATA (output) EMAC_MDIO_01 Figure 5-14. EMAC MDIO Diagrams receive and transmit 5.9.4.4.2 EMAC MII Timings Table 5-28 and Figure 5-15 present timing requirements for MII in receive operation. Table 5-28. Timing Requirements for MII_RXCLK—MII Operation NO. MII1 PARAMETER tc(RXCLK) MII2 tw(RXCLKH) Pulse duration, MII_RXCLK high MII3 tw(RXCLKL) Pulse duration, MII_RXCLK low MII4 110 tt(RXCLK) Specifications SPEED MIN MAX 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns 10 Mbps 140 260 ns Cycle time, MII_RXCLK UNIT 100 Mbps 14 26 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 5 ns 100 Mbps 5 ns Transition time, MII_RXCLK Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 MII4 MII1 MII3 MII2 MII_RXCLK MII4 EMAC_MII_01 Figure 5-15. Clock Timing (EMAC Receive)—MII operation Table 5-29 and Figure 5-16 present timing requirements for MII in transmit operation. Table 5-29. Timing Requirements for MII_TXCLK—MII Operation MII2 MII3 MII4 PARAMETER tc(TXCLK) tw(TXCLKH) tw(TXCLKL) tt(TXCLK) SPEED MIN MAX 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns Cycle time, MII_TXCLK Pulse duration, MII_TXCLK high UNIT 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 5 ns 100 Mbps 5 ns Pulse duration, MII_TXCLK low Transition time, MII_TXCLK MII4 MII1 MII2 MII3 MII_TXCLK MII4 EMAC_MII_02 Figure 5-16. Clock Timing (EMAC Transmit)—MII operation Table 5-30 and Figure 5-17 present timing requirements for EMAC MII Receive 10 Mbps and 100 Mbps. Table 5-30. Timing Requirements for EMAC MII Receive 10 Mbps and 100 Mbps NO. PARAMETER MIN MAX UNIT tsu(RXD-RXCLK) MII5 tsu(RXDV-RXCLK) Setup time, receive selected signals valid before MII_RXCLK 8 ns Hold time, receive selected signals valid after MII_RXCLK 8 ns tsu(RXER-RXCLK) th(RXCLK-RXD) MII6 th(RXCLK-RXDV) th(RXCLK-RXER) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 111 ADVANCE INFORMATION NO. MII1 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com MII5 MII6 MII_RXCLK (input) MII_RXD3−MII_RXD0, MII_RXDV, MII_RXER (inputs) EMAC_MII_03 Figure 5-17. EMAC Receive Interface Timing MII operation Table 5-31 and Figure 5-18 present timing requirements for EMAC MII Transmit 10 Mbps and 100 Mbps. Table 5-31. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 Mbps and 100 Mbps NO. PARAMETER td(TXCLK-TXD) MII7 td(TXCLK-TXEN) Delay time, MII_TXCLK to transmit selected signals valid MIN MAX 10 Mbps SPEED 5 25 UNIT ns 100 Mbps 5 25 ns ADVANCE INFORMATION MII7 MII_TXCLK (input) MII_TXD3−MII_TXD0, MII_TXEN (outputs) EMAC_MII_04 Figure 5-18. EMAC Transmit Interface Timing MII operation 5.9.4.4.3 EMAC RMII Timings Table 5-32, Table 5-33, and Figure 5-19 present timing requirements for EMAC RMII receive. Table 5-32. Timing Requirements for EMAC RMII_REFCLK—RMII Operation NO. PARAMETER MIN MAX UNIT RMII1 tc(REFCLK) Cycle time, RMII_REFCLK 19.999 20.001 ns RMII2 tw(REFCLKH) Pulse duration, RMII_REFCLK high 7 13 ns RMII3 tw(REFCLKL) Pulse duration, RMII_REFCLK low 7 13 ns RMII4 tt(REFCLK) Transition time, RMII_REFCLK 5 ns Table 5-33. Timing Requirements for EMAC RMII Receive NO. PARAMETER MIN tsu(RXD-REFCLK) RMII5 tsu(CRS_DV-REFCLK) MAX UNIT 4 Setup time, receive selected signals valid before RMII_REFCLK ns tsu(RXER-REFCLK) th(REFCLK-RXD) RMII6 th(REFCLK-CRS_DV) 2 Hold time, receive selected signals valid after RMII_REFCLK ns th(REFCLK-RXER) 112 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 RMII1 RMII3 RMII2 RMII6 RMII5 RMII_REFCLK RMII4 RMII4 RMII_RXD1−RMII_RXD0, RMII_CRS_DV, RMII_RXER (inputs) EMAC_RMII_01 Figure 5-19. EMAC Receive Interface Timing RMII operation Table 5-34, Table 5-34, and Figure 5-20 present switching characteristics for EMAC RMII Transmit 10 Mbps and 100 Mbps. Table 5-34. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII_REFCLK —RMII Operation PARAMETER MIN MAX 19.999 20.001 ns Pulse duration, RMII_REFCLK high 7 13 ns Pulse duration, RMII_REFCLK low 7 13 ns 5 ns tc(REFCLK) Cycle time, RMII_REFCLK RMII8 tw(REFCLKH) RMII9 tw(REFCLKL) RMII10 tt(REFCLK) Transition time, RMII_REFCLK UNIT Table 5-35. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 Mbps and 100 Mbps NO. PARAMETER RMII11 RMII12 RMII13 td(REFCLK-TXD) td(REFCLK-TXEN) Delay time, RMII_REFCLK high to selected transmit signals valid tr(TXD) Rise time, TXD outputs tr(TXEN) Rise time, TXEN output tf(TXD) Fall time, TXD outputs tf(TXEN) Fall time, TXEN output MIN MAX UNIT 2 13 ns 1 5 ns 1 5 ns RMII7 RMII10 RMII8 RMII11 RMII9 RMII_REFCLK RMII10 RMII_TXD1−RMII_TXD0, RMII_TXEN (outputs) RMII13 RMII12 EMAC_RMII_02 Figure 5-20. EMAC Transmit Interface Timing RMII Operation 5.9.4.4.4 EMAC RGMII Timings Table 5-36, Table 5-37, and Figure 5-21 present timing requirements for receive RGMII operation. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 113 ADVANCE INFORMATION NO. RMII7 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-36. Timing Requirements for RGMII_RXC—RGMII Operation NO. PARAMETER RGMII1 RGMII2 RGMII3 RGMII4 tc(RXC) Cycle time, RGMII_RXC tw(RXCH) Pulse duration, RGMII_RXC high tw(RXCL) Pulse duration, RGMII_RXC low tt(RXC) Transition time, RGMII_RXC SPEED MIN MAX UNIT 10 Mbps 360 440 ns 100 Mbps 36 44 ns 1000 Mbps 7.2 8.8 ns 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns Table 5-37. Timing Requirements for EMAC RGMII Input Receive for 10 Mbps, 100 Mbps, and 1000 Mbps ADVANCE INFORMATION NO. PARAMETER MIN MAX UNIT RGMII5 tsu(RXD-RXC) Setup time, receive selected signals valid before RGMII_RXC high and low 1 ns RGMII6 th(RXC-RXD) Hold time, receive selected signals valid after RGMII_RXC high and low 1 ns RGMII1 RGMII2 RGMII_RXC RGMII4 RGMII4 RMGII3 (A) RGMII5 1st Half-byte 2nd Half-byte (B) RGRXD[3:0] RGRXD[7:4] (B) RXDV RXERR RGMII_RXD[3:0] RGMII_RXCTL RGMII6 EMAC_RGMII_01 A. B. RGMII_RXC must be externally delayed relative to the data and control pins. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 5-21. EMAC Receive Interface Timing, RGMII operation Table 5-38, Table 5-39, and Figure 5-23 present switching characteristics for transmit - RGMII for 10 Mbps, 100 Mbps, and 1000 Mbps. Table 5-38. Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps NO. RGMII1 tc(TXC) 114 Specifications PARAMETER SPEED MIN MAX UNIT 10 Mbps 360 440 ns Cycle time, RGMII_TXC 100 Mbps 36 44 ns 1000 Mbps 7.2 8.8 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-38. Switching Characteristics Over Recommended Operating Conditions for Transmit - RGMII operation for 10 Mbps, 100 Mbps, and 1000 Mbps (continued) NO. PARAMETER RGMII2 tw(TXCH) RGMII3 tw(TXCL) RGMII4 tt(TXC) Pulse duration, RGMII_TXC high Pulse duration, RGMII_TXC low Transition time, RGMII_TXC SPEED MIN MAX UNIT 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns RGMII1 RGMII4 RGMII3 RGMII4 RGMII_TXC Figure 5-22. RGMII_TCX Timing - RGMII Mode Table 5-39. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII Mode (1) MIN MAX UNIT RGMII5 NO. td(TXD-TXC) Delay time, TXD to TXC PARAMETER -0.35 0.65 ns RGMII6 td(TXCTL-TXC) Delay time, TXCTL to TXC -0.35 0.65 ns RGMII7 tt(TXD) Transition time, TXD 0.75 ns RGMII8 tt(TXCTL) Transition time, TXCTL 0.75 ns (1) PCB traces for RGMII_TXD[3:0] and RGMII_TXCTL should insert an additional 150ps of delay relative to the PCB trace delay of RGMII_TXC. This provides the expected output timing as defined by the RGMII specification for a transmitter not operating in RGMII-ID timing mode. Timing analysis should be performed on this interface using actual timing requirements/characteristics of the attached RGMII PHY. In some cases, additional PCB delays may be required to provide proper timing margins. (A) RGMII_TXC RGMII5 RGMII5 RGMII7 (B) RGMII_TXD[3:0] 1st Half-byte 2nd Half-byte RGMII6 (B) RGMII_TXCTL A. B. TXEN RGMII6 RGMII8 TXERR RGMII_TXC must be externally delayed relative to the data and control pins. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 5-23. EMAC Transmit Interface Timing RGMII Mode Table 5-40. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode(1) NO. PARAMETER MIN MAX UNIT RGMII5 td(TXD-TXC) Delay time, TXD to TXC (0.25 × tc(TXC)) - 0.24 (0.25 × tc(TXC)) + 0.60 ns RGMII6 td(TXCTL-TXC) Delay time, TXCTL to TXC (0.25 × tc(TXC)) - 0.24 (0.25 × tc(TXC)) + 0.60 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 115 ADVANCE INFORMATION RGMII2 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-40. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit - RGMII_TXD[3:0], and RGMII_TXCTL - RGMII ID Mode(1) (continued) NO. PARAMETER MIN MAX RGMII7 tt(TXD) Transition time, TXD 0.75 RGMII8 tt(TXCTL) Transition time, TXCTL 0.75 UNIT (1) PCB traces for RGMII_TXD[3:0] and RGMII_TXCTL should insert an additional 150ps of delay relative to the PCB trace delay of RGMII_TXC. This provides the expected output timing as defined by the RGMII specification for a transmitter operating in RGMII-ID timing mode. Timing analysis should be performed on this interface using actual timing requirements/characteristics of the attached RGMII PHY. In some cases, additional PCB delays may be required to provide proper timing margins. (A) RGMII_TXC RGMII5 RGMII5 RGMII7 (B) 1st Half-byte RGMII_TXD[3:0] 2nd Half-byte RGMII6 (B) TXEN RGMII_TXCTL ADVANCE INFORMATION A. B. RGMII6 RGMII8 TXERR RGMII_TXC must be externally delayed relative to the data and control pins. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 5-24. EMAC Transmit Interface Timing - RGMII ID Mode For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the device TRM. 5.9.4.5 GPMC For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.4.5.1 GPMC and NOR Flash—Synchronous Mode Table 5-42 and Table 5-43 assume testing over the recommended operating conditions and electrical characteristic conditions shown in Table 5-41 (see Figure 5-25 through Figure 5-29). Table 5-41. GPMC and NOR Flash Timing Conditions—Synchronous Mode PARAMETER MIN TYP MAX UNIT 0.9 2.8(1) ns 0.9 (1) ns 20 pF Input Conditions tR Input signal rise time tF Input signal fall time 2.8 Output Condition CLOAD Output load capacitance 5 (1) Max tR & tF = 25% of clock period when GPMC_CLK = 88.67 MHz. Table 5-42. GPMC and NOR Flash Timing Requirements—Synchronous Mode NO. MIN MAX UNIT F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high 3.5 ns F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high 2.5 ns F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[x](1) valid before output clock GPMC_CLK high 3.5 ns 116 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-42. GPMC and NOR Flash Timing Requirements—Synchronous Mode (continued) NO. F22 MIN th(clkH-waitV) Hold time, input wait GPMC_WAIT[x](1) valid after output clock GPMC_CLK high MAX UNIT 2.5 ns (1) In GPMC_WAIT[x], x is equal to 0 or 1. Table 5-43. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2) PARAMETER MIN MAX (18) , output clock GPMC_CLK UNIT F0 1 / tc(clk) Frequency F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high 0.5P(15) 0.5P(15) 100 ns F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low 0.5P(15) 0.5P(15) ns tdc(clk) Duty cycle error, output clock GPMC_CLK tJ(clk) Jitter standard deviation(19), output clock GPMC_CLK tR(clk) 500 ps 33.33 ps Rise time, output clock GPMC_CLK 2 ns tF(clk) Fall time, output clock GPMC_CLK 2 ns tR(do) Rise time, output data GPMC_AD[15:0] 2 ns tF(do) Fall time, output data GPMC_AD[15:0] 2 ns F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x](14) transition F(6) - 2.2 F(6) + 4.5 ns F3 td(clkH-csnIV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x](14) invalid E(5) - 2.2 E(5) + 4.5 ns F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge B(2) - 4.5 B(2) + 3.1 ns F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid -2.3 4.5 ns F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge B(2) - 1.9 B(2) + 2.3 ns F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11) D(4) - 2.3 D(4) + 1.9 ns F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) D(4) - 2.3 D(4) + 1.9 ns F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13) D(4) - 2.3 D(4) + 1.9 ns F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition G(7) - 2.3 G(7) + 4.5 ns F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid D(4) - 2.3 D(4) + 4.5 ns F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition H(8) - 2.3 H(8) + 3.5 ns F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid H(8) - 2.3 H(8) + 3.5 ns F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition I(9) - 2.3 I(9) + 4.5 ns F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11) J(10) - 2.3 J(10) + 2.7 ns F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) J(10) - 2.3 J(10) + 2.7 ns F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13) J(10) - 2.3 J(10) + 2.7 ns F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11) J(10) - 2.3 J(10) + 1.9 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 -500 MHz Specifications ADVANCE INFORMATION NO. 117 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-43. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2) (continued) NO. MIN MAX F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) J(10) - 2.3 J(10) + 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13) J(10) - 2.3 J(10) + 1.9 ns F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[x](14) low Read A(1) ns Write A(1) ns Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C(3) ns Write C(3) ns Pulse duration, output address valid and address latch Read enable GPMC_ADVn_ALE low Write K(16) ns K(16) ns F19 F20 PARAMETER tw(be[x]nV) tw(advnV) UNIT (17) (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (2) B = ClkActivationTime × GPMC_FCLK(17) ADVANCE INFORMATION (3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (6) For csn falling edge (CS activated): – Case GpmcFCLKDivider = 0: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) (7) For ADV falling edge (ADV activated): – Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode: – Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode: – Case GpmcFCLKDivider = 0: 118 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com – – SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction): – Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) ADVANCE INFORMATION For OE rising edge (OE deactivated): – Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (9) For WE falling edge (WE activated): – Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK (17) – Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (10) J = GPMC_FCLK(17) (11) First transfer only for CLK DIV 1 mode. (12) Half cycle; for all data after initial transfer for CLK DIV 1 mode. (13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK. (14) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. (15) P = GPMC_CLK period in ns (16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider. (19) The jitter probability density can be approximated by a Gaussian function. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 119 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com F1 F0 F1 GPMC_CLK F2 F3 F18 GPMC_CSn[x] F4 GPMC_A[10:1] Valid Address F6 F7 F19 GPMC_BE0n_CLE F19 GPMC_BE1n F6 F8 F8 F20 F9 GPMC_ADVn_ALE ADVANCE INFORMATION F10 F11 GPMC_OEn_REn F13 F12 GPMC_AD[15:0] D0 GPMC_WAIT[x] A. B. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-25. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0) 120 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 F1 F0 F1 GPMC_CLK F2 F3 GPMC_CSn[x] F4 GPMCA[10:1] Valid Address F6 F7 GPMC_BE0n_CLE F7 GPMC_BE1n F6 F8 F8 F9 GPMC_ADVn_ALE F10 F11 GPMC_OEn_REn F13 D0 GPMC_AD[15:0] F21 ADVANCE INFORMATION F13 F12 F12 D1 D2 D3 F22 GPMC_WAIT[x] A. B. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-26. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0) F1 F1 F0 GPMC_CLK F2 F3 GPMC_CSn[x] F4 Valid Address GPMC_A[10:1] F17 F6 F17 F17 GPMC_BE0n_CLE F17 F17 F17 GPMC_BE1n F6 F8 F8 F9 GPMC_ADVn_ALE F14 F14 GPMC_WEn F15 GPMC_AD[15:0] D0 D1 F15 D2 F15 D3 GPMC_WAIT[x] A. B. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-27. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 121 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com F1 F0 F1 GPMC_CLK F2 F3 GPMC_CSn[x] F6 F7 GMPC_BE0n_CLE Valid F6 F7 Valid GPMC_BE1n F4 GPMC_A[27:17] Address (MSB) F12 F4 GPMC_AD[15:0] F5 F13 Address (LSB) D0 F8 D1 F12 D2 F8 D3 F9 GPMC_ADVn_ALE ADVANCE INFORMATION F10 F11 GPMC_OEn_REn GPMC_WAIT[x] A. B. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-28. GPMC and Multiplexed NOR Flash—Synchronous Burst Read 122 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 F1 F1 F0 GPMC_CLK F2 F3 F18 GPMC_CSn[x] F4 GPMC_A[27:17] Address (MSB) F17 F6 F17 F6 F17 F17 GPMC_BE1n F17 F17 BPMC_BE0n_CLE F8 F8 F20 F9 ADVANCE INFORMATION GPMC_ADVn_ALE F14 F14 GPMC_WEn F15 GPMC_AD[15:0] Address (LSB) D0 F22 D1 F15 D2 F15 D3 F21 GPMC_WAIT[x] A. B. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-29. GPMC and Multiplexed NOR Flash—Synchronous Burst Write Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 123 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 5.9.4.5.2 GPMC and NOR Flash—Asynchronous Mode Table 5-44 and Table 5-45 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-30 through Figure 5-35). Table 5-44. GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode(1)(2) NO. MIN MAX UNIT ADVANCE INFORMATION FI1 Delay time, output data GPMC_AD[15:0] generation from internal functional clock GPMC_FCLK(3) 6.5 ns FI2 Delay time, input data GPMC_AD[15:0] capture from internal functional clock GPMC_FCLK(3) FI3 Delay time, output chip select GPMC_CSn[x] generation from internal functional clock GPMC_FCLK(3) 4 ns 6.5 ns FI4 Delay time, output address GPMC_A[27:1] generation from internal functional clock GPMC_FCLK(3) 6.5 ns FI5 Delay time, output address GPMC_A[27:1] valid from internal functional clock GPMC_FCLK(3) 6.5 ns FI6 Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n generation from internal functional clock GPMC_FCLK(3) 6.5 ns FI7 Delay time, output enable GPMC_OEn_REn generation from internal functional clock GPMC_FCLK(3) 6.5 ns FI8 Delay time, output write enable GPMC_WEn generation from internal functional clock GPMC_FCLK(3) 6.5 ns FI9 Skew, internal functional clock GPMC_FCLK(3) 100 ps (1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. (3) GPMC_FCLK is general-purpose memory controller internal functional clock. 124 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-45. GPMC and NOR Flash Timing Requirements—Asynchronous Mode NO. FA5(1) MIN tacc(d) MAX Data access time UNIT H(5) ns (4) ns ns (2) FA20 tacc1-pgmode(d) Page mode successive data access time P FA21(3) tacc2-pgmode(d) Page mode first data access time H(5) (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. NO. FA0 FA1 FA3 PARAMETER MIN MAX UNIT tR(d) Rise time, output data GPMC_AD[15:0] 2 ns tF(d) Fall time, output data GPMC_AD[15:0] 2 ns tw(be[x]nV) Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time Read N(12) ns Write (12) Pulse duration, output chip select GPMC_CSn[x](13) low Read A(1) Write (1) Delay time, output chip select GPMC_CSn[x](13) valid to output address valid and address latch enable GPMC_ADVn_ALE invalid Read B(2) - 0.2 B(2) + 2.0 Write B(2) - 0.2 B(2) + 2.0 tw(csnV) td(csnV-advnIV) N A ns ns FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn invalid (Single read) C(3) - 0.2 C(3) + 2.0 ns FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[x](13) valid J(9) - 0.2 J(9) + 2.0 ns FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[x](13) valid J(9) - 0.2 J(9) + 2.0 ns FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSn[x](13) valid to output address valid and address latch enable GPMC_ADVn_ALE valid K(10) - 0.2 K(10) + 2.0 ns FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn valid L(11) - 0.2 L(11) + 2.0 ns FA16 tw(aIV) Pulse durationm output address GPMC_A[26:1] invalid between 2 successive read and write accesses FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[x](13) valid to output enable GPMC_OEn_REn invalid (Burst read) FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSn[x](13) valid to output write enable GPMC_WEn valid E(5) - 0.2 E(5) + 2.0 ns FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSn[x](13) valid to output write enable GPMC_WEn invalid F(6) - 0.2 F(6) + 2.0 ns FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid 2.8 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 G(7) I(8) - 0.2 ADVANCE INFORMATION Table 5-46. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode ns I(8) + 2.0 D(4) ns ns Specifications 125 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-46. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued) NO. PARAMETER FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[x](13) valid FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end MIN MAX J(9) - 0.2 J(9) + 2.8 UNIT ns 2.8 ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) with n being the page burst access number (2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) (5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) ADVANCE INFORMATION (7) G = Cycle2CycleDelay × GPMC_FCLK(14) (8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14) (10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. 126 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 GPMC_FCLK GPMC_CLK FA5 FA1 GPMC_CSn[x] FA9 Valid Address GPMC_A[10:1] FA0 FA10 GPMC_BE0n_CLE Valid GPMC_BE1n Valid FA0 FA10 FA3 FA12 FA4 FA13 GPMC_OEn_REn Data IN 0 GPMC_AD[15:0] Data IN 0 GPMC_WAIT[x] A. B. C. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-30. GPMC and NOR Flash—Asynchronous Read—Single Word Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 127 ADVANCE INFORMATION GPMC_ADVn_ALE 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com GPMC_FCLK GPMC_CLK FA5 FA5 FA1 FA1 GPMC_CSn[x] FA16 FA9 FA9 GPMC_A[10:1] Address 0 Address 1 FA0 FA10 FA0 FA10 Valid GPMC_BE0n_CLE Valid FA0 GPMC_BE1n FA0 Valid FA10 Valid FA10 FA3 FA3 FA12 FA12 ADVANCE INFORMATION GPMC_ADCn_ALE FA4 FA4 FA13 FA13 GPMC_OEn_REn GPMC_AD[15:0] Data Upper GPMC_WAIT[x] A. B. C. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-31. GPMC and NOR Flash—Asynchronous Read—32-Bit 128 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 GPMC_FCLK GPMC_CLK FA21 FA20 FA20 FA20 Add1 Add2 Add3 D0 D1 D2 FA1 GPMC_CSn[x] FA9 Add0 GPMC_A[10:1] Add4 FA0 FA10 GPMC_BE0n_CLE FA0 FA10 GPMC_BE1n FA12 FA18 FA13 GPMC_OEn_REn GPMC_AD[15:0] D3 D3 GPMC_WAIT[x] A. B. C. D. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-32. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 129 ADVANCE INFORMATION GPMC_ADVn_ALE 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com GPMC_FCLK GPMC_CLK FA1 GPMC_CSn[x] FA9 GPMC_A[10:1] Valid Address FA0 FA10 GPMC_BE0n_CLE FA0 FA10 GPMC_BE1n FA3 FA12 GPMC_ADVn_ALE FA27 ADVANCE INFORMATION FA25 GPMC_WEn FA29 GPMC_AD[15:0] Data OUT GPMC_WAIT[x] A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-33. GPMC and NOR Flash—Asynchronous Write—Single Word 130 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 GPMC_FCLK GPMC_CLK FA1 FA5 GPMC_CSn[x] FA9 GPMC_A[27:17] Address (MSB) FA0 FA10 GPMC_BE0n_CLE Valid FA0 FA10 GPMC_BE1n Valid FA3 FA4 FA13 GPMC_OEn_REn FA29 GPMC_AD[15:0] FA37 Address (LSB) Data IN Data IN GPMC_WAIT[x] A. B. C. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-34. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 131 ADVANCE INFORMATION FA12 GPMC_ADVn_ALE 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com GPMC_FCLK GPMC_CLK FA1 GPMC_CSn[x] FA9 GPMC_A[27:17] Address (MSB) FA0 FA10 GPMC_BE0n_CLE FA0 FA10 GPMC_BE1n FA3 FA12 GPMC_ADVn_ALE FA27 ADVANCE INFORMATION FA25 GPMC_WEn FA29 GPMC_AD[15:0] FA28 Valid Address (LSB) Data OUT GPMC_WAIT[x] A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-35. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word 132 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.9.4.5.3 GPMC and NAND Flash—Asynchronous Mode Table 5-47 and Table 5-48 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-36 through Figure 5-39). Table 5-47. GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode(1)(2) MIN MAX UNIT Delay time, output data GPMC_AD[15:0] generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI2 Delay time, input data GPMC_AD[15:0] capture from internal functional clock GPMC_FCLK(3) 4.0 ns GNFI3 Delay time, output chip select GPMC_CSn[x] generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI4 Delay time, output address valid and address latch enable GPMC_ADVn_ALE generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI5 Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI6 Delay time, output enable GPMC_OEn_REn generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI7 Delay time, output write enable GPMC_WEn generation from internal functional clock GPMC_FCLK(3) 6.5 ns GNFI8 Skew, functional clock GPMC_FCLK(3) 100 ps (1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. (3) GPMC_FCLK is general-purpose memory controller internal functional clock. Table 5-48. GPMC and NAND Flash Timing Requirements—Asynchronous Mode NO. GNF12(1) MIN tacc(d) Access time, input data GPMC_AD[15:0] MAX J(2) UNIT ns (1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3) (3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 133 ADVANCE INFORMATION NO. GNFI1 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-49. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode NO. PARAMETER tR(d) Rise time, output data GPMC_AD[15:0] MIN MAX UNIT 2 ns 2 ns ADVANCE INFORMATION tF(d) Fall time, output data GPMC_AD[15:0] GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn valid GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSn[x](13) valid to output write enable GPMC_WEn valid B(2) - 0.2 B(2) + 2.0 ns GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid C(3) - 0.2 C(3) + 2.0 ns GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid D(4) - 0.2 D(4) + 2.8 ns GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid E(5) - 0.2 E(5) + 2.8 ns GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid F(6) - 0.2 F(6) + 2.0 ns GNF6 tw(wenIV-csnIV) Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSn[x](13) invalid G(7) - 0.2 G(7) + 2.0 ns GNF7 tw(aleH-wenV) Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid C(3) - 0.2 C(3) + 2.0 ns GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid F(6) - 0.2 F(6) + 2.0 ns GNF9 tc(wen) Cycle time, write H(8) ns + 2.0 ns K(10) ns (13) GNF10 td(csnV-oenV) Delay time, output chip select GPMC_CSn[x] output enable GPMC_OEn_REn valid GNF13 tw(oenV) Pulse duration, output enable GPMC_OEn_REn valid A(1) valid to GNF14 tc(oen) Cycle time, read GNF15 tw(oenIV-csnIV) Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSn[x](13) invalid I (9) - 0.2 L ns I (9) (11) M(12) - 0.2 ns M(12) + 2.0 ns (1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14) (4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14) (5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14) (6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14) (11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14) (13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. 134 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 GPMC_FCLK GNF1 GNF6 GNF2 GNF5 GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADCn_ALE GPMC_OEn_REn GNF0 GPMC_WEn GNF3 GNF4 GPMC_AD[15:0] (1) Command In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. ADVANCE INFORMATION Figure 5-36. GPMC and NAND Flash—Command Latch Cycle GPMC_FCLK GNF1 GNF6 GNF7 GNF8 GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GNF9 GNF0 GPMC_WEn GNF3 GPMC_AD[15:0] (1) GNF4 Address In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. Figure 5-37. GPMC and NAND Flash—Address Latch Cycle Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 135 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com GPMC_FCLK GNF12 GNF10 GNF15 GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADVn_ALE GNF14 GNF13 GPMC_OEn_REn GPMC_AD[15:0] DATA GPMC_WAIT[x] (1) ADVANCE INFORMATION (2) (3) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-38. GPMC and NAND Flash—Data Read Cycle GPMC_FCLK GNF1 GNF6 GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GNF9 GNF0 GPMC_WEn GNF3 GPMC_AD[15:0] (1) GNF4 DATA In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. Figure 5-39. GPMC and NAND Flash—Data Write Cycle For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory Subsystem of the device TRM. 5.9.4.6 I2C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-50 and Figure 5-40 assume testing over the recommended operating conditions and electrical characteristic conditions. 136 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-50. Timing Requirements for I2C Input Timings I1 MIN MAX FAST MODE MIN MAX UNIT tc(SCL) Cycle time, SCL 10 2.5 µs I2 tsu(SCLH-SDAL) Setup Time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs I3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs I4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs I5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs (1) I6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 I7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0(2) I8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 I9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(4) 300 ns I10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(4) 300 ns I11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(4) 300 ns 300 (4) 300 I12 tf(SCL) Fall time, SCL I13 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) 4 I14 tw(SP) Pulse duration, spike (must be suppressed) 0 100 3.45(3) ns 0(2) 0.9(3) µs 1.3 20 + 0.1Cb µs ns 0.6 50 µs 0 50 ns (1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (4) Cb is line load in pF. I9 I11 I2Cx_SDA I6 I8 I14 I4 I13 I5 I10 I2Cx_SCL I12 I1 I3 I7 I2 I3 Stop Start Repeated Start Stop Figure 5-40. I2C Receive Timing(1) (1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2. Table 5-51 and Figure 5-41 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-51. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings NO. I15 PARAMETER tc(SCL) Cycle time, SCL STANDARD MODE MIN 10 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 MAX FAST MODE MIN MAX 2.5 Specifications UNIT µs 137 ADVANCE INFORMATION STANDARD MODE NO. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-51. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings (continued) NO. STANDARD MODE PARAMETER MIN MAX FAST MODE MIN MAX UNIT I16 tsu(SCLH-SDAL) Setup Time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs I17 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs I18 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs I19 tw(SCLH) Pulse duration, SCL high 4 0.6 µs I20 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 I21 th(SCLL-SDAV) Hold time, SDA valid after SCL low I22 tw(SDAH) Pulse duration, SDA high between STOP and START conditions I23 tr(SDA) Rise time, SDA 0 3.45 4.7 ns 0 0.9 1.3 µs µs 1000 20 + 0.1Cb(1) 300 ns (1) ADVANCE INFORMATION I24 tr(SCL) Rise time, SCL 1000 300 ns I25 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(1) 300 ns I26 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(1) 300 ns I27 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) 4 20 + 0.1Cb 0.6 µs (1) Cb is line load in pF. NOTE I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of driving high when transmitting logic-1. I26 I24 I2C[x]_SDA I23 I21 I19 I25 I28 I20 I2C[x]_SCL I27 I16 I18 I22 I17 I18 Stop Start Repeated Start Stop Figure 5-41. I2C Transmit Timing(1) (1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2. For more information, see section Inter-IC module (I2C) in chapter Peripherals of the device TRM. 138 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.9.4.7 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 McASP For more details about features and additional description information on the device Multichannel Audio Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-52, Table 5-53, and Figure 5-42 present timing requirements for McASP0 to McASP2. Table 5-52. Timing Requirements for McASP(4) MIN ASP1 tc(AHCLKRX) Cycle time, McASP[x]_AHCLKR/X ASP2 tw(AHCLKRX) Pulse duration, McASP[x]_AHCLKR/X high or low ASP3 tc(ACLKRX) ASP4 tw(ACLKRX) tsu(AFSRX-ACLKRX) 20 ns ns Cycle time, McASP[x]_ACLKR/X 20 ns Pulse duration, McASP[x]_ACLKR/X high or low (3) ns 0.5R - 2.5 Setup time, McASP[x]_AFSR/X input valid before McASP[x]_ACLKR/X ACLKR/X ext in ACLKR/X ext out ACLKR/X int ASP6 th(ACLKRX-AFSRX) Hold time, McASP[x]_AFSR/X input valid after McASP[x]_ACLKR/X tsu(AXR-ACLKRX) Setup time, McASP[x]_AXR input valid before McASP[x]_ACLKR/X th(ACLKRX-AXR) Hold time, McASP[x]_AXR input valid after McASP[x]_ACLKR/X 4 ns 4 -1 1.6 ACLKR/X ext out 1.6 ns 12.3 ACLKR/X ext in 4 ACLKR/X ext out 4 ACLKR/X int ASP8 12.3 ACLKR/X ext in ACLKR/X int ASP7 UNIT 0.5P - 2.5(2) ACLKR/X int ASP5 MAX ADVANCE INFORMATION NO. ns -1 ACLKR/X ext in 1.6 ACLKR/X ext out 1.6 ns (1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 (2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in ns. (3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns. (4) x in McASP[x]_* is 0, 1 or 2 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 139 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com ASP2 ASP1 ASP2 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) ASP4 ASP3 McASP[x]_ACLKR/X (CLKRP = CLKXP = 0) McASP[x]_ACLKR/X (CLKRP = CLKXP = 1) ASP4 (A) (B) ASP6 ASP5 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) ADVANCE INFORMATION McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) ASP8 ASP7 McASP[x]_AXR[x] (Data In/Receive) A. B. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). C31 Figure 5-42. McASP Input Timing (1) x in McASP[x]_* is 0, 1 or 2 140 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-53 and Figure 5-43 present switching characteristics over recommended operating conditions for McASP0 to McASP2. Table 5-53. Switching Characteristics Over Recommended Operating Conditions for McASP(4) NO. MIN ns ns ns tc(AHCLKRX) Cycle time, McASP[x]_AHCLKR/X tw(AHCLKRX) Pulse duration, McASP[x]_AHCLKR/X high or low ASP11 tc(ACLKRX) Cycle time, McASP[x]_ACLKR/X 20 Pulse duration, McASP[x]_ACLKR/X high or low (3) Delay time, McASP[x]_ACLKR/X transmit edge to McASP[x]_AFSR/X output valid ASP13 td(ACLKRX-AFSRX) Delay time, McASP[x]_ACLKR/X transmit edge to McASP[x]_AFSR/X output valid with Pad Loopback 20 ASP15 td(ACLKX-AXR) 7.25 ACLKR/X ext in 2 14 ACLKR/X ext out 2 14 0 7.25 2 14 2 14 ACLKX int 0 7.25 ACLKX ext in 2 14 ns tdis(ACLKX-AXR) Delay time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output valid with Pad ACLKX ext out Loopback Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance with Pad Loopback ns 0 Delay time, McASP[x]_ACLKX transmit edge ACLKX int to McASP[x]_AXR output valid ACLKX ext in ASP14 0.5P - 2.5 ACLKR/X int ns ADVANCE INFORMATION tw(ACLKRX) UNIT 0.5P - 2.5(3) ASP9 ASP10 ASP12 MAX (2) ns ACLKX ext out 2 14 (1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 (2) 50 MHz (3) P = AHCLKR and AHCLKX period. (4) x in McASP[x]_* is 0, 1 or 2 Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 141 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 ASP9 www.ti.com ASP10 ASP10 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) ASP12 ASP11 McASP[x]_ACLKR/X (CLKRP = CLKXP = 1) McASP[x]_ACLKR/X (CLKRP = CLKXP = 0) ASP12 (A) (B) ASP13 ASP13 ASP13 ASP13 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) ADVANCE INFORMATION McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) ASP13 ASP13 ASP13 McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) McASP[x]_AXR[x] (Data Out/Transmit) ASP14 ASP15 A. B. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). C31 Figure 5-43. McASP Output Timing (1) x in McASP[x]_* is 0, 1 or 2 For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the device TRM. 142 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 5.9.4.8 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 McBSP For more details about features and additional description information on the device Multichannel Buffered Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-54, Table 5-55, and Figure 5-44 present timing requirements and switching characteristics for McBSP Interface. Table 5-54. McBSP Timing Requirements(1) MIN BSP2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext BSP3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext BSP5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low BSP6 th(CKRL-FRH) BSP7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low BSP8 th(CKRL-DRV) Hold time, DR valid after CLKR low BSP10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low BSP11 th(CKXL-FXH) Hold time, external FSX high after CLKX low Hold time, external FSR high after CLKR low 2P (2) MAX UNIT (3) ns P-1(4) ns or 20 CLKR int 14 CLKR ext 4 CLKR int 6 CLKR ext 3 CLKR int 14 CLKR ext 4 CLKR int 3 CLKR ext 3 CLKR int 14 CLKR ext 4 CLKR int 6 CLKR ext 3 ns ns ns ns ns ns (1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = 1/SYSCLK1 period in ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. Table 5-55. McBSP Switching Characteristics(1) NO. PARAMETER MIN MAX UNIT 1 14.5 ns BSP1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input. BSP2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P(2) or 20(3) BSP3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 2(4) C + 2(4) ns –4 5.5 ns CLKR int 1 14.5 ns CLKX int –4 5.5 CLKX ext 1 14.5 CLKX int –4 7.5 CLKX ext 1 14.5 CLKX int –4 + D1(5) 5.5 + D2(5) CLKX ext 1 + D1(5) 14.5 + D2(5) –4 + D1(6) 5 + D2(6) (6) 14.5 + D2(6) BSP4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid BSP9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid BSP12 tdis(CKXH-DXHZ) Disable time, DX HiZ following last data bit from CLKX high BSP13 td(CKXH-DXV) Delay time, CLKX high to DX valid BSP14 td(FXH-DXV) Delay time, FSX high to DX valid applies ONLY when in data delay 0 (XDATDLY = 00b) mode CLKR int FSX int FSX ext Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 –2 + D1 ns Specifications ns ns ns ns 143 ADVANCE INFORMATION NO. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com (1) Minimum delay times also represent minimum output hold times. (2) P = 1/SYSCLK1 period in ns. (3) Use whichever value is greater. (4) C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK1 period in ns) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) If CLKGDV is even: (1) H = CLKX high pulse width = (CLKGDV/2 + 1) × S (2) L = CLKX low pulse width = (CLKGDV/2) × S If CLKGDV is odd: (1) H = (CLKGDV + 1)/2 × S (2) L = (CLKGDV + 1)/2 × S CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit. (5) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P (6) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P ADVANCE INFORMATION CLKS BSP1 BSP2 BSP3 BSP3 CLKR BSP4 BSP4 FSR (int) BSP5 BSP6 FSR (ext) BSP7 Bit(n-1) DR BSP8 (n-2) (n-3) BSP2 BSP3 BSP3 CLKX BSP9 FSX (int) BSP11 BSP10 FSX (ext) FSX (XDATDLY=00b) BSP12 DX Bit 0 BSP14 (B) BSP13 Bit(n-1) BSP13 (n-2) (n-3) Figure 5-44. McBSP Timing Table 5-56. McBSP Timing Requirements for FSR When GSYNC = 1 NO. 144 MIN MAX UNIT BSPF1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns BSPF2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 CLKS BSPF1 BSPF2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 5-45. FSR Timing When GSYNC = 1 MLB For more details about features and additional description information on the device Media Local Bus, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE MLB in 6-pin mode may require pullups/ pulldowns on SIG and DAT bus signals. For additional details, please consult the MediaLB Interface Specification. Table 5-57 and Figure 5-46 present Timing Requirements for MLBCLK 3-Pin Option. Table 5-57. Timing Requirements for MLBCLK 3-Pin Option NO. PARAMETER DESCRIPTION MODE MIN M31 tc(MLBCLK) Cycle time, MLB_CLK 512FS 39 ns 1024FS 19.5 ns M32 tw(MLBCLKH) Pulse duration, MLB_CLK high M33 tw(MLBCLKL) Pulse duration, MLB_CLK low M34 tt(MLBCLKH) Transition time, MLB_CLK high tt(MLBCLKL) Transition time, MLB_CLK low MAX UNIT 512FS 14 ns 1024FS 9.3 ns 512FS 14 ns 1024FS 6.1 ns 512FS TBD ns 1024FS TBD ns 512FS TBD ns 1024FS TBD ns M32 M34 M31 MLB_CLK M33 M34 Figure 5-46. MLB_CLK Timing Table 5-58, Table 5-59, and Figure 5-47 present Timing Requirements and Switching Characteristics for MLB 3-Pin Option. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 145 ADVANCE INFORMATION 5.9.4.9 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-58. Timing Requirements for Receive Data for the MLB 3-Pin Option NO. PARAMETER DESCRIPTION MODE MIN M35 tsu(MLBDAT-MLBCLKL) Setup time, MLB_DAT/MLB_SIG input valid before MLB_CLK low 512FS 1 ns 1024FS 1 ns 512FS 4 ns 1024FS 2 ns M36 th(MLBCLKL-MLBDAT) Hold time, MLB_DAT/MLB_SIG input valid after MLB_CLK low MAX UNIT Table 5-59. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT M37 td(MLBCLKH-MLBDATV) Delay time, MLB_CLK rising to MLB_DAT/MLB_SIG valid 512FS 0 10 ns 1024FS 0 7 ns 512FS 0 14 ns 1024FS 0 6.1 ns MIN MAX UNIT M38 tdis(MLBCLKL- Disable time, MLB_CLK falling to MLB_DAT/MLB_SIG HiZ MLBDATZ) M35 M36 ADVANCE INFORMATION MLB_CLK MLB_SIG MLB_DAT (receive) MLB_SIG MLB_DAT (transmit) M37 M38 SPRS93v_MLB_TIMING_2 Figure 5-47. MLB 3-Pin Timing Table 5-60 and Figure 5-48 present Timing Requirements for MLKCLK 6-Pin Option. Table 5-60. Timing Requirements for MLBCLK 6-Pin Option (1) NO. PARAMETER DESCRIPTION MODE M61 tc(CLKx) Cycle time, MLBP_CLK_x 2048FS 10 ns M62 tw(CLKxH) Pulse duration, MLBP_CLK_x high 2048FS 4.5 ns M63 tw(CLKxL) Pulse duration, MLBP_CLK_x low 2048FS 4.5 ns M64 tt(CLKxH) Transition time, MLBP_CLK_x high 2048FS TBD ns tt(CLKxL) Transition time, MLBP_CLK_x low 2048FS TBD ns (1) x in MLBP_CLK_x is P or N. M62 M64 M61 MLBP_CLK_x M63 M64 (1) Figure 5-48. MLB_CLKP/N Timing (1) x in MLBP_CLK_x is P or N. Table 5-61, Table 5-62, and Figure 5-49 present Timing Requirements and Switching Characteristics for MLB 6-Pin Option. 146 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-61. Timing Requirements for Receive Data for the MLB 6-Pin Option (1) NO. PARAMETER DESCRIPTION MODE MIN M65 tsu(DATx-CLKxH) Setup time, MLBP_DAT_x/MLBP_SIG_x input valid before MLBP_CLK_x rising 2048FS 1 MAX UNIT ns M66 th(CLKxH-DATx) Hold time, MLBP_DAT_x_/MLBP_SIG_x input valid after MLBP_CLK_x rising 2048FS 0.5 ns (1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N. Table 5-62. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT M67 td(CLKxH-DATxV) Delay time, MLBP_CLK_x rising to MLB_DAT_x/MLB_SIG_x valid 2048FS 0.5 7 ns M68 tdis(CLKxH-DATxZ) Disable time, MLBP_CLK_x rising to MLBP_DAT_x/MLBP_SIG_x HiZ 2048FS 0.5 7 ns (1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N. M66 MLBP_CLK_x MLBP_SIG_x MLBP_DAT_x (receive) MLBP_SIG_x MLBP_DAT_x (transmit) M68 M67 SPRS93v_MLB_TIMING_4 (1) Figure 5-49. MLB 6-Pin Timing (1) x in MLBP_CLK_x, MLBP_DAT_x, and MLBP_SIG_x is P or N. For more information, see section Media Local Bus (MLB) in chapter Peripherals of the device TRM. 5.9.4.10 MMC/SD For more details about features and additional description information on the device Multi Media Card, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE The MMC/SD/SDIOi (i = 0 to 1) controller is also referred to as MMCi. Table 5-63. MMC Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tr Input signal rise time (10% to 90%) 1 2.2 ns tf Input signal fall time (90% to 10%) 1 2.2 ns 2 40 pF Output Condition Cload Output load capacitance Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 147 ADVANCE INFORMATION M65 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-64. Timing Requirements for MMC0_CMD and MMC0_DATn(1) (see Figure 5-50) NO. 3.3 V PARAMETER MIN TYP MAX UNIT MMC1 tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge 3.9 ns MMC2 th(CLKH-CMDV) Hold time, MMC_CMD valid after MMC_CLK rising clock edge 2.5 ns MMC3 tsu(DATV-CLKH) Setup time, MMC_DATn valid before MMC_CLK rising clock edge 3.9 ns MMC4 th(CLKH-DATV) Hold time, MMC_DATn valid after MMC_CLK rising clock edge 2.5 ns (1) n in MMC_DATn is 0 to 7. Table 5-65. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in SDR mode(1) (see Figure 5-50) NO. 1.8 V PARAMETER MIN TYP MAX UNIT ADVANCE INFORMATION MMC1 tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge 4.2 ns MMC2 th(CLKH-CMDV) Hold time, MMC_CMD valid after MMC_CLK rising clock edge 2.5 ns MMC3 tsu(DATV-CLKH) Setup time, MMC_DATn valid before MMC_CLK rising clock edge 4.2 ns MMC4 th(CLKH-DATV) Hold time, MMC_DATn valid after MMC_CLK rising clock edge 2.5 ns (1) n in MMC_DATn is 0 to 7. MMC1 MMC2 MMCi_CLK (Output) MMCi_CMD (Input) MMCi_DATn (Inputs) MMC3 MMC4 Figure 5-50. MMCi_CMD and MMCi_DATn Input Timing(1) (1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 0 or 1, where n = 0 to 7. Table 5-66. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode(3) (see Figure 5-51) NO. 1.8 V PARAMETER MIN TYP MAX UNIT MMC1 tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge 4.2 ns MMC2 th(CLKH-CMDV) Hold time, MMC_CMD valid after MMC_CLK rising clock edge 2.5 ns MMC3 tsu(DATV-CLKH) Setup time, MMC_DATn valid before MMC_CLK rising or falling clock edge 0.5(1) ns 148 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-66. Timing Requirements for MMC1_CMD and MMC1_DATn when operating in DDR mode(3) (continued) (see Figure 5-51) NO. 1.8 V PARAMETER MMC4 MIN Hold time, MMC_CLK rising or falling clock edge after MMC_DATn valid th(CLKH-DATV) TYP UNIT MAX 1.62(2) ns (1) The minimum setup time of 0.5ns is a function of the maximum output delay of 7ns defined in the JESD84 standard plus the combined PCB delay of the MMC_CLK and MMC_DATn signal traces. Therefore, the PCB shall be designed with less than 9.2ns of combined delay in the MMC_CLK and MMC_DATn signal traces when operating at the maximum frequency of 48 MHz. (2) The minimum hold time of 1.62ns exceeds the minimum output delay of 1.5ns defined in the JESD84 standard. Therefore, the PCB shall be designed with greater than 120ps of combined delay in the MMC_CLK and MMC_DATn signal traces. (3) n in MMC_DATn is 0 to 7. MMC1 MMC2 MMCi_CMD (Input) MMCi_DATn (Inputs) MMC3 MMC3 MMC4 MMC4 (1) Figure 5-51. MMC1_CMD and MMC1_DATn Input Timing - DDR Mode (1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 1, where n = 0 to 7. Table 5-67. Switching Characteristics for MMCi_CLK(2) (see Figure 5-52) NO. PARAMETER MMC5 MMC6 MIN fop(CLK) Operating frequency, MMC_CLK tcop(CLK) Operating period: MMC_CLK fid(CLK) Identification mode frequency, MMC_CLK tcid(CLK) Identification mode period: MMC_CLK tw(CLKL) Pulse duration, MMC_CLK low TYP MAX UNIT 48 MHz 400 kHz 20.8 ns 2500 ns (0.5 × P) - tf(CLK)(1) ns (0.5 × P) - tr(CLK) (1) MMC7 tw(CLKH) Pulse duration, MMC_CLK high MMC8 tr(CLK) Rise time, All Signals (10% to 90%) 2.2 ns ns MMC9 tf(CLK) Fall time, All Signals (90% to 10%) 2.2 ns (1) P = MMC_CLK period. (2) i in MMCi_CLK is 0 or 1. MMC5 MMC6 MMC7 MMC8 MMC9 MMCi_CLK (Output) Figure 5-52. MMCi_CLK Timing(1) (1) i in MMCi_CLK is 0 or 1. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 149 ADVANCE INFORMATION MMCi_CLK (Output) 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-68. Switching Characteristics for MMC0_CMD and MMC0_DATn—HSPE=0(1) (see Figure 5-53) NO. 3.3 V PARAMETER MIN TYP MAX UNIT MMC10 td(CLKL-CMD) Delay time, MMC_CLK falling clock edge to MMC_CMD transition -7.4 4.4 ns MMC11 td(CLKL-DAT) Delay time, MMC_CLK falling clock edge to MMC_DATn transition -7.4 4.4 ns (1) n in MMC_DATn is 0 to 7. Table 5-69. Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in SDR mode(1) (see Figure 5-53) NO. 1.8 V PARAMETER MIN TYP MAX UNIT ADVANCE INFORMATION MMC10 td(CLKL-CMD) Delay time, MMC_CLK falling clock edge to MMC_CMD transition -7.4 7.4 ns MMC11 td(CLKL-DAT) Delay time, MMC_CLK falling clock edge to MMC_DATn transition -7.4 7.4 ns (1) n in MMC_DATn is 0 to 7. MMC10 MMCi_CLK (Output) MMCi_CMD (Output) MMCi_DATn (Outputs) MMC11 Figure 5-53. MMCi_CMD and MMCi_DATn Output Timing—HSPE=0(1) (1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 0 or 1, where n = 0 to 7. Table 5-70. Switching Characteristics for MMC1_CMD and MMC1_DATn—HSPE=0 when operating in DDR mode(1) (see Figure 5-54) NO. 1.8 V PARAMETER MIN TYP MAX UNIT MMC10 td(CLKL-CMD) Delay time, MMC_CLK falling clock edge to MMC_CMD transition -4.4 2.2 ns MMC11 td(CLKL-DAT) Delay time, MMC_CLK rising or falling clock edge to MMC_DATn transition -4.4 2.2 ns 150 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (1) n in MMC_DATn is 0 to 7. MMC10 MMCi_CLK (Output) MMCi_CMD (Output) MMCi_DATn (Outputs) MMC11 MMC11 Figure 5-54. MMC1_CMD and MMC1_DATn Output Timing—HSPE=0 – DDR Mode(1) (1) i in MMCi_CLK, MMCi_CMD, and MMCi_DATn is 1, where n = 0 to 7. For more details about features and additional description information on the device Peripheral Component Interconnect Express, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.4.12 PRU-ICSS The device has integrated two identical PRU subsystems (PRU-ICSS_0 and PRU-ICSS_1). The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device. For more details about features and additional description information on the device Programmable RealTime Unit Subsystem and Industrial Communication Subsystem, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE The PRU-ICSS_0 and PRU-ICSS_1 support an internal wrapper multiplexing that expands the device top-level multiplexing. Signal naming in this section must match the internal wrapper multiplexing. For more information, please refer to the Device TRM, Chapter Processors and Accelerators, Section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS). 5.9.4.12.1 Programmable Real-Time Unit (PRU-ICSS PRU) NOTE The PRU-ICSS PRU signals have different functionality depending on the mode of operation. The signal naming in this section matches the naming used in the PRU Module Interface section in the device TRM. 5.9.4.12.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing Table 5-71. PRU-ICSS PRU Timing Requirements - Direct Input Mode NO. PRDI1 PARAMETER tw(GPI) Pulse width, GPI Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 MIN 2×P MAX (1) UNIT ns Specifications 151 ADVANCE INFORMATION 5.9.4.11 PCIESS 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com (1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1. PRDI1 GPI[m:0] SPRS91x_TIMING_PRU_01 Figure 5-55. PRU-ICSS PRU Direct Input Timing (1) m in GPI[m:0] = 19. Table 5-72. PRU-ICSS PRU Switching Requirements – Direct Output Mode NO. PARAMETER PRDO1 tw(GPO) Pulse width, GPO PRDO2 tsk(GPO) Skew between GPO[19:0] signals MIN 2×P MAX (1) UNIT ns 3 ns (1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1. ADVANCE INFORMATION PRDO1 GPO[n:0] PRDO2 SPRS91x_TIMING_PRU_02 Figure 5-56. PRU-ICSS PRU Direct Output Timing (1) n in GPO[n:0] = 19. 5.9.4.12.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing Table 5-73. PRU-ICSS PRU Timing Requirements – Parallel Capture Mode NO. PARAMETER MIN MAX UNIT PRPC1 tw(CLOCKIN) Cyle time, CLOCKIN 20 ns PRPC2 tw(CLOCKINL) Pulse duration, CLOCKIN low 10 ns PRPC3 tw(CLOCKINH) Pulse duration, CLOCKIN high 10 ns PRPC4 tsu(DATAIN-CLOCKIN) Setup time, DATAIN valid before CLOCKIN 4.4 ns PRPC5 th(CLOCKIN-DATAIN) Hold time, DATAIN valid after CLOCKIN 0 ns (1) P = ICSS_n_COREn_CLK clock period, where n = 0 or 1. PRPC1 PRPC3 PRPC2 CLOCKIN DATAIN PRPC5 PRPC4 SPRS91x_TIMING_PRU_03 Figure 5-57. PRU-ICSS PRU Parallel Capture Timing – Rising Edge Mode 152 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 PRPC1 PRPC3 PRPC2 CLOCKIN DATAIN PRPC5 PRPC4 SPRS91x_TIMING_PRU_04 Figure 5-58. PRU-ICSS PRU Parallel Capture Timing – Falling Edge Mode 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing Table 5-74. PRU-ICSS PRU Timing Requirements – Shift In Mode PARAMETER tw(DATAIN) Pulse width, DATAIN MIN MAX 2 × P(1) + 3 UNIT ns (1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the PRUSS_GPCFGn register. For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM. PRSI1 DATAIN SPRS91x_TIMING_PRU_05 Figure 5-59. PRU-ICSS PRU Shift In Timing Table 5-75. PRU-ICSS PRU Switching Requirements – Shift Out Mode NO. PARAMETER PRSO1 tc(CLOCKOUT) Cycle time, CLOCKOUT PRSO2 tw(CLOCKOUT) Pulse width, CLOCKOUT PRSO3 td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid MIN MAX 13.3 0.4 × P (1) UNIT ns 0.5 × P -1.5 (1) ns 3 ns (1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the PRUSS_GPCFGn register. For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM. PRSO1 PRSO2 CLOCKOUT DATAOUT PRSO3 SPRS91x_TIMING_PRU_06 Figure 5-60. PRU-ICSS PRU Shift Out Timing 5.9.4.12.2 PRU-ICSS EtherCAT™ (PRU-ICSS ECAT) 5.9.4.12.2.1 PRU-ICSS ECAT Electrical Data and Timing Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 153 ADVANCE INFORMATION NO. PRSI1 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-76. PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx NO. PARAMETER MIN EDCS1 tw(EDC_SYNCx_OUT) Pulse width, EDC_SYNCx_OUT EDCS2 tsu(EDIO_DATA_INEDC_SYNCx_OUT) EDCS3 th(EDC_SYNCx_OUT- MAX UNIT 100.00 ns Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT rising edge 20.00 ns Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT rising edge 20.00 ns EDIO_DATA_IN) EDC_SYNCx_OUT EDCS1 EDCS2 EDCS3 EDIO_DATA_IN[3:0] ADVANCE INFORMATION SPRS91x_TIMING_PRU_ECAT_02 Figure 5-61. PRU-ICSS ECAT Input Validated With SYNCx Timing Table 5-77. PRU-ICSS ECAT Timing Requirements – LATCHx_IN NO. PARAMETER EDCL1 tw(EDC_LATCHx_IN) MIN Pulse duration, EDC_LATCHx_IN 3×P MAX (1) UNIT ns (1) P = ICSS_n_IEP_CLK, where n = 0 or 1. EDC_LATCHx_IN EDCL1 SPRS91x_TIMING_PRU_ECAT_04 Figure 5-62. PRU-ICSS ECAT LATCHx_IN Timing Table 5-78. PRU-ICSS ECAT Switching Requirements – Digital IOs NO. PARAMETER EDIOD1 tsk(EDIO_DATA_OUT) MIN EDIO_DATA_OUT skew MAX 8 UNIT ns EDIO_DATA_OUT[n:0] EDIOD1 SPRS91x_TIMING_PRU_EDIO_DATA_OUT Figure 5-63. PRU-ICSS EDIO DATA_OUT Timing (1) n in EDIO_DATA_OUT[n:0] = 3. 5.9.4.12.3 PRU-ICSS MII_RT and Switch 5.9.4.12.3.1 PRU-ICSS MDIO Electrical Data and Timing 154 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-79. PRU-ICSS MDIO Timing Requirements – MDIO_DATA NO. PARAMETER PRMDI1 tsu(MDIO-MDC) Setup time, MDIO valid before MDC high PRMDI2 th(MDIO-MDC) Hold time, MDIO valid from MDC high MIN MAX UNIT 90 ns 0 ns PRMDI1 PRMDI2 MDIO_CLK (Output) MDIO_DATA (Input) SPRS91x_TIMING_PRU_MII_RT_01 Table 5-80. PRU-ICSS MDIO Switching Characteristics – MDIO_CLK NO. PARAMETER MIN MAX UNIT PRMC1 tc(MDC) Cycle time, MDC 400 ns PRMC2 tw(MDCH) Pulse duration, MDC high 160 ns PRMC3 tw(MDCL) Pulse duration, MDC low 160 ns PRMC4 tt(MDC) Transition time, MDC 5 ns PRMC4 PRMC1 PRMC3 PRMC2 MDIO_CLK PRMC4 SPRS91x_TIMING_PRU_MII_RT_02 Figure 5-65. PRU-ICSS MDIO_CLK Timing Table 5-81. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA NO. PRMDO1 td(MDC-MDIO) PARAMETER Delay time, MDC high to MDIO valid MIN MAX UNIT 10 390 ns PRMDO1 MDIO_CLK (Output) MDIO_DATA (Output) SPRS91x_TIMING_PRU_MII_RT_03 Figure 5-66. PRU-ICSS MDIO_DATA Timing – Output Mode 5.9.4.12.3.2 PRU-ICSS MII_RT Electrical Data and Timing Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 155 ADVANCE INFORMATION Figure 5-64. PRU-ICSS MDIO_DATA Timing – Input Mode 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 5-82. PRU-ICSS MII_RT Timing Requirements – MII_RXCLK NO. PARAMETER PMIR1 PMIR2 PMIR3 PMIR4 tc(RXCLK) tw(RXCLKH) tw(RXCLKL) tt(RXCLK) Cycle time, RXCLK Pulse duration, RXCLK high Pulse duration, RXCLK low Transition time, RXCLK SPEED MIN MAX 10 Mbps 399.96 400.04 UNIT ns 100 Mbps 39.996 40.004 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 3 ns 100 Mbps 3 ns PMIR1 PMIR3 PMIR2 MII_RXCLK ADVANCE INFORMATION PMIR4 SPRS91x_TIMING_PRU_MII_RT_04 Figure 5-67. PRU-ICSS MII_RXCLK Timing Table 5-83. PRU-ICSS MII_RT Timing Requirements – MII_TXCLK NO. PMIT1 PARAMETER tc(TXCLK) Cycle time, TXCLK PMIT2 tw(TXCLKH) Pulse duration, TXCLK high PMIT3 tw(TXCLKL) Pulse duration, TXCLK low PMIT4 tt(TXCLK) Transition time, TXCLK SPEED MIN MAX 10 Mbps 399.96 400.04 UNIT ns 100 Mbps 39.996 40.004 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 140 260 ns 100 Mbps 14 26 ns 10 Mbps 3 ns 100 Mbps 3 ns PMIT4 PMIT1 PMIT3 PMIT2 MII_TXCLK PMIT4 SPRS91x_TIMING_PRU_MII_RT_05 Figure 5-68. PRU-ICSS MII_TXCLK Timing 156 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-84. PRU-ICSS MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER NO. PMIR5 PMIR6 PARAMETER tsu(RXD-RXCLK) Setup time, RXD[3:0] valid before RXCLK tsu(RXDV-RXCLK) Setup time, RXDV valid before RXCLK tsu(RXER-RXCLK) Setup time, RXER valid before RXCLK tsu(RXD-RXCLK) Setup time, RXD[3:0] valid before RXCLK tsu(RXDV-RXCLK) Setup time, RXDV valid before RXCLK tsu(RXER-RXCLK) Setup time, RXER valid before RXCLK th(RXCLK-RXD) Hold time, RXD[3:0] valid after RXCLK th(RXCLK-RXDV) Hold time, RXDV valid after RXCLK th(RXCLK-RXER) Hold time, RXER valid after RXCLK th(RXCLK-RXD) Hold time, RXD[3:0] valid after RXCLK th(RXCLK-RXDV) Hold time, RXDV valid after RXCLK th(RXCLK-RXER) Hold time, RXER valid after RXCLK SPEED MIN MAX UNIT 10 Mbps 8 ns 100 Mbps 8 ns 10 Mbps 8 ns 100 Mbps 8 ns PMIR6 MII_RXCLK (Input) MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) SPRS91x_TIMING_PRU_MII_RT_06 Figure 5-69. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing Table 5-85. PRU-ICSS MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN NO. PMIT5 PARAMETER td(TXCLK-TXD) Delay time, TXCLK high to TXD[3:0] valid td(TXCLK-TXEN) Delay time, TXCLK to TXEN valid td(TXCLK-TXD) Delay time, TXCLK high to TXD[3:0] valid td(TXCLK-TXEN) Delay time, TXCLK to TXEN valid SPEED MIN MAX UNIT 10 Mbps 4 25 ns 100 Mbps 4 25 ns PMIT5 MII_TXCLK (input) MII_TXD[3:0], MII_TXEN (outputs) SPRS91x_TIMING_PRU_MII_RT_07 Figure 5-70. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 157 ADVANCE INFORMATION PMIR5 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 5.9.4.12.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART) Table 5-86. PRU-ICSS UART Timing Conditions PARAMETER MIN TYP MAX UNIT Output Condition CLOAD Output load capacitance 5 25 pF Table 5-87. Timing Requirements for PRU-ICSS UART Receive NO. PARAMETER PRUR1 tw(RX) Pulse duration, receive start, stop, data bit MIN MAX (1) (1) 0.96U 1.05U UNIT ns (1) U = UART baud time = 1 / programmed baud rate. For more information, see section PRU-ICSS UART Clock Generation and Control in the device TRM. Table 5-88. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit NO. PARAMETER PRUT1 ADVANCE INFORMATION PRUT2 ƒ(baud) MIN MAX UNIT 0 12 MHz -2 ns Maximum programmable baud rate tw(TX) Pulse duration, transmit start, stop, data bit U (1) -2 U (1) (1) U = UART baud time = 1 / programmed baud rate. For more information, see section PRU-ICSS UART Clock Generation and Control in the device TRM. PRUR1 PRUR1 pri_uart0_rxd (1) Start Bit Data Bits PRUT2 PRUT2 pri_uart0_txd (1) Start Bit Data Bits (1) i in pri_uart0_txd and pri_uart0_rxd = 1 or 2 SPRS91x_TIMING_PRU_UART_01 Figure 5-71. PRU-ICSS UART Timing 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes Table 5-89. PRU-ICSS PRU Timing Requirements - Sigma Delta Mode PARAMETER DESCRIPTION PRSD1 NO. tw(SDx_CLK) Pulse width, SDx_CLK 20 ns PRSD2 tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns PRSD3 th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge 5 ns 158 Specifications MIN MAX UNIT Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 PRSD1 SDx_CLK PRSD1 SDx_D PRSD3 PRSD2 SPRS91x_TIMING_PRU_07 Figure 5-72. PRU-ICSS PRU SD_CLK Falling Active Edge PRSD1 SDx_D PRSD3 PRSD2 SPRS91x_TIMING_PRU_08 Figure 5-73. PRU-ICSS PRU SD_CLK Rising Active Edge Table 5-90. PRU-ICSS PRU Timing Requirements - EnDAT Mode NO. PRTE1 PARAMETER DESCRIPTION tw(ENDATx_IN) Pulse width, ENDATx_IN MIN MAX 40 UNIT ns Table 5-91. PRU-ICSS PRU Switching Requirements - EnDAT Mode NO. PARAMETER DESCRIPTION PRSE2 tw(ENDATx_CLK) Pulse width, ENDATx_CLK MIN MAX PRSE3 td(ENDATx_OUT- Delay time, ENDATx_CLK fall to ENDATx_OUT -10 10 ns Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN -10 10 ns 20 UNIT ns ENDATx_CLK) PRSE4 td(ENDATx_OUT_ENENDATx_CLK) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 159 ADVANCE INFORMATION SDx_CLK 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com ENDATx_IN PRTE1 PRSE2 ENDATx_CLK PRSE2 ENDATx_OUT PRSE3 ADVANCE INFORMATION ENDATx_OUT_EN PRSE4 SPRS91x_TIMING_PRU_09 Figure 5-74. PRU-ICSS PRU EnDAT Timing For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM. 5.9.4.13 QSPI For more details about features and additional description information on the device Quad Serial Port Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-92 and Table 5-93 present timing requirements and switching characteristics for QSPI interface. Table 5-92. Timing Requirements for QSPI NO. 160 PARAMETER MIN Q7 tsu(D-RTCLK) Setup time, QSPI_D[3:0] valid before active QSPI_RTCLK edge Q8 th(RTCLK-D) Hold time, QSPI_D[3:0] valid after inactive QSPI_RTCLK edge Specifications MAX UNIT 1.5 ns 0 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 QSPI_CSnj Q5 Q1 Q4 Q3 Q2 QSPI_CLK QSPI_RTCLK Q6 Q6 Q7 Command Bit n-1 QSPI_D[3:0] Q7 Q8 Read Data Bit 1 Command Bit n-2 Q8 Read Data Bit 0 QSPI_Read_Clock mode 0 Figure 5-75. QSPI Read (Mode [3:0]) Table 5-93. Switching Characteristics for QSPI Q1 PARAMETER tc(CLK) MIN Cycle time, QSPI_CLK MAX UNIT 10.42(1) ns (2) ns Q2 tw(CLK L) Pulse duration, QSPI_CLK low 0.48 × P Q3 tw(CLK H) Pulse duration, QSPI_CLK high 0.48 × P(2) ns Q4 td(CSn-CLK) Delay time, QSPI_CSn active edge to QSPI_CLK transition 5.00 ns Q5 td(CLK-CSn) Delay time, QSPI_CLK transition to QSPI_CSn inactive edge 5.00 ns Q6 td(CLK-D0) Delay time, QSPI_CLK active edge to QSPI_D[0] transition 0 2 ADVANCE INFORMATION NO. ns (1) Maximum supported frequency is 96 MHz (Mode 0 only). (2) P = QSPI_CLK period. PHA=0 QSPI_CSnj Q5 Q1 Q4 Q3 POL=0 Q2 QSPI_CLK Q6 QSPI_D[0] Q6 Q6 Command Bit n-1 Command Bit n-2 Q6 Write Data Bit 1 Write Data Bit 0 QSPI_D[3:1] QSPI_Write_Clock mode 0 Figure 5-76. QSPI Write (Mode [3:0]) For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the device TRM. 5.9.4.14 SPI For more details about features and additional description information on the device Serial Port Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 161 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the device TRM. 5.9.4.14.1 SPI—Slave Mode Table 5-94, Table 5-95, Figure 5-77, and Figure 5-78 present Timing Requirements for SPI - Slave Mode. Table 5-94. Timing Requirements for SPI Input Timings—Slave Mode NO. PARAMETER MIN MAX UNIT S1 tc(SPICLK) Cycle time, SPI_CLK S2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P S3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(1) S4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] (SIMO) valid before SPI_CLK active edge(2)(3) 2 ns S5 th(SPICLK-SIMO) Hold time, SPI_D[x] (SIMO) valid after SPI_CLK active edge(2)(3) 2 ns (2) 2 ns th(SPICLK-CS) Hold time, SPI_CS valid after SPI_CLK last edge 2 ns td(CS-SPICLK) Required delay from SPIx_CS asserted at slave to first SPI_CLK edge at slave. Phase = 0 C+5 (4) ns td(CS-SPICLK) Required delay from SPIx_CS asserted at slave to first SPI_CLK edge at slave. Phase = 1 A + 5(4) ns td(SPICLK-CS) Required delay from final SPI_CLK edge before SPI_CS is deasserted at slave. Phase = 0 G + 5(4) ns td(SPICLK-CS) Required delay from final SPI_CLK edge before SPI_CS is deasserted at slave. Phase = 1 E + 5(4) ns td(CSH-SPCN) Minimum delay from slave deselected (SPI_CS deasserted) to SPI_CLK edge (for another slave on the bus) C + 5(4) ns S8 S9 tsu(CS-SPICLK) 40 Setup time, SPI_CS valid before SPI_CLK first edge (2) ns 0.45P (1) (1) ns 0.45P(1) ns ADVANCE INFORMATION (1) P = SPI_CLK period. (2) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to drive output data and capture input data. (3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. (4) A = (2 × P2) + (0.5 × SPI_CLK) C = (2 × P2) E = (1 × P2) G = (1 × P2) + (0.5 × SPI_CLK) P2 = 1 / (SYSCLK1 / 6) Table 5-95. Switching Characteristics for SPI Output Timings—Slave Mode NO. PARAMETER S6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to SPI_D[x] (SOMI) transition(1)(2) S7 tena(CS-SOMI) Delay from master asserting SPIx_CS to slave driving SPIx_SOMI valid(2) S10 tdis(CS-SOMI) Delay from master deasserting SPIx_CS to slave 3stating SPIx_SOMI(2) 162 Specifications MIN MAX UNIT 0 12 ns 0 5 ns 1 x P2(3) 1 x P2(3) + 5 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (1) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. (3) P2 = 1 / (SYSCLK1 / 6). PHA=0 EPOL=1 SPI_CS[x] (In) S1 S3 S8 SPI_SCLK (In) S2 S9 POL=0 S1 S3 S2 POL=1 SPI_SCLK (In) SPI_D[x] (SIMO, In) S4 S5 S5 Bit n-1 Bit n-2 Bit n-3 ADVANCE INFORMATION S4 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (In) S1 S3 S8 SPI_SCLK (In) S9 S2 POL=0 S1 S2 S3 POL=1 SPI_SCLK (In) SPI_D[x] (SIMO, In) S4 S4 S5 S5 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 SPI_01 Figure 5-77. SPI Slave Mode Receive Timing Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 163 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (In) S1 S3 S8 S2 S9 POL=0 SPI_SCLK (In) S1 S3 S2 POL=1 SPI_SCLK (In) SPI_D[x] (SOMI, Out) S7 S6 Bit n-1 Bit n-2 Bit n-3 Bit 0 Bit n-4 ADVANCE INFORMATION PHA=1 EPOL=1 SPI_CS[x] (In) S1 S3 S8 S9 S2 POL=0 SPI_SCLK (In) S1 S2 S3 POL=1 SPI_SCLK (In) S6 SPI_D[x] (SOMI, Out) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 SPI_02 Figure 5-78. SPI Slave Mode Transmit Timing 5.9.4.14.2 SPI—Master Mode Table 5-97, Table 5-98, Figure 5-79 and Figure 5-80 present Timing Requirements for SPI - Master Mode. Table 5-96. SPI Timing Conditions—Master Mode PARAMETER MIN MAX UNIT Input Conditions tr Input signal rise time 4 ns tf Input signal fall time 4 ns 20 pF MAX UNIT Output Condition Cload Output load capacitance Table 5-97. Timing Requirements for SPI Input Timings—Master Mode NO. PARAMETER (1) S4 tsu(SOMI-SPICLK) S5 th(SPICLK-SOMI)(1) 164 Specifications MIN (2) Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active edge 3 ns Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active edge(2) 2 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (1) This timing applies to all configurations regardless of SPIx_CLK polarity and which clock edges are used to capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Table 5-98. Switching Characteristics for SPI Output Timings—Master Mode NO. S1 PARAMETER tc(SPICLK) MIN MAX 20(5) Cycle time, SPI_CLK (1) UNIT ns (1) ns 0.45P(1) ns S2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P S3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(1) S3R tr(SPICLK) Rising time, SPI_CLK 5 ns S3F tf(SPICLK) Falling time, SPI_CLK 5 ns S6 td(SPICLK-SIMO) Delay time, SPI_CLK active edge to SPI_D[x] (SIMO) transition(2) -2 2 ns Mode 1 and 3(3) A - 5(4) B + 5(4) ns Mode 0 and 2(3) C - 5(4) D + 5(4) ns Mode 1 and 3(3) E - 5(4) F + 5(4) ns Mode 0 and 2(3) G - 5(4) H + 5(4) ns S8 S9 td(CS-SPICLK) td(SPICLK-CS) Delay time, SPI_CS active to SPI_CLK first edge Delay time, SPI_CLK last edge to SPI_CS inactive 0.45P (1) P = SPI_CLK period. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. ADVANCE INFORMATION (3) The polarity of SPIx_CLK and the active edge (rising or falling) on which spix_simo is driven and spix_somi is latched is all software configurable: – PHASE = 1 Mode 3 and Mode 1. – PHASE = 0 Mode 2 and Mode 0. (4) A = (2 × P2) + (0.5 × SPI_CLK) B = (2 × P2) + (C2TDELAY +1) × P2) + (0.5 × SPI_CLK) C = (2 × P2) D = (2 × P2) + (C2TDELAY +1) × P2) E = (1 × P2) F = (1 × P2) + ((T2CDELAY+1) × P2) G = (1 × P2) + (0.5 × SPI_CLK) H = (1 × P2) + ((T2CDELAY+1) × P2) + (0.5 × SPI_CLK) P2 = 1/(SYSCLK1 / 6) (5) Minimum clock period is dependent on SYSCLK1 and SPI module prescaler settings and may be higher than shown in the table. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 165 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (Out) S3F S1 S3R S3 S8 SPI_SCLK (Out) S9 S2 POL=0 S1 S3F S2 S3R S3 POL=1 SPI_SCLK (Out) S4 SPI_D[x] (SOMI, In) S4 S5 S5 Bit n-1 Bit n-2 Bit n-3 Bit 0 Bit n-4 ADVANCE INFORMATION PHA=1 EPOL=1 SPI_CS[x] (Out) S3F S1 S3R S3 S8 SPI_SCLK (Out) S9 S2 POL=0 S1 S3F S2 S3R S3 POL=1 SPI_SCLK (Out) SPI_D[x] (SOMI, In) S4 S4 S5 S5 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 SPI_03 Figure 5-79. SPI Master Mode Receive Timing 166 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 PHA=0 EPOL=1 SPI_CS[x] (Out) S3F S1 S3R S3 S8 SPI_SCLK (Out) S9 S2 POL=0 S1 S3F S2 S3R S3 POL=1 SPI_SCLK (Out) S6 SPI_D[x] (SIMO, Out) Bit n-1 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (Out) S3F S1 S3R S3 S8 SPI_SCLK (Out) S9 S2 POL=0 S1 S2 S3F S3R S3 POL=1 SPI_SCLK (Out) S6 SPI_D[x] (SIMO, Out) Bit n-1 Bit n-2 Bit n-3 Bit 0 Bit 1 SPI_04 Figure 5-80. SPI Master Mode Transmit Timing 5.9.4.15 Timers For more details about features and additional description information on the device Timers, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-99. Timer Input Timing Requirements NO. PARAMETER MIN (1) MAX UNIT T1 tw(TINPH) Pulse duration, high 12C ns T2 tw(TINPL) Pulse duration, low 12C(1) ns (1) C=1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL. Table 5-100. Timer Output Switching Characteristics NO. PARAMETER MIN (1) MAX UNIT T3 tw(TOUTH) Pulse duration, high 12C -3 ns T4 tw(TOUTL) Pulse duration, low 12C(1) - 3 ns Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 167 ADVANCE INFORMATION S7 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com (1) C=1/SYSCLK1 in ns. SYSCLK1 clock is sourced from the main PLL. T1 T2 TIMIx T3 T4 TIMOx TIMER_01 Figure 5-81. Timer Timing For more information, see section Timers in chapter Peripherals of the device TRM. ADVANCE INFORMATION 168 Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 5.9.4.16 UART For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-101, Figure 5-82, and Figure 5-85 present Timing Requirements for UART interface. Table 5-101. Timing Requirements for UART NO. MIN MAX UNIT Receive Timing U4 tw(RXSTART) Pulse width, receive start bit 0.96U(1) 1.05U(1) ns U5 tw(RXH) Pulse width, receive data/parity bit high 0.96U(1) 1.05U(1) ns (1) (1) ns 1.05U(1) ns U6 tw(RXL) Pulse width, receive data/parity bit low 0.96U tw(RXSTOP) Pulse width, receive stop bit 0.96U(1) 1.05U (1) U = UART baud time = 1 / programmed baud rate. U5 U4 RXD Stop/Idle Start Bit 1 Bit 0 Bit N-1 Bit N U5 U6 Parity Stop Idle Start Figure 5-82. UART Receive Timing Waveform Table 5-102, Figure 5-83, and Figure 5-84 present Switching Characteristics for UART interface. Table 5-102. Switching Characteristics Over Recommended Operating Conditions for UART NO. PARAMETER MIN MAX UNIT U(1) - 2 U(1) + 2 ns Transmit Timing U1 U2 U3 tw(TXSTART) Pulse width, transmit start bit tw(TXH) Pulse width, transmit data/parity bit high U -2 U(1) + 2 ns tw(TXL) Pulse width, transmit data/parity bit low U(1) - 2 U(1) + 2 ns tw(TXSTOP1) Pulse width, transmit stop bit 1 tw(TXSTOP15) Pulse width, transmit stop bit 1.5 U tw(TXSTOP2) Pulse width, transmit stop bit 2 td(RX-RTSH) Delay time, STOP bit received to RTS deasserted (1) (1) -2 U (1) +2 ns 1.5U(1) - 2 1.5U(1) + 2 ns 2U(1) - 2 2U(1) + 2 ns P(2) 5P(2) ns (2) 5P(2) ns Autoflow Timing Requirements U7 U8 td(CTSL-TX) Delay time, CTS asserted to START bit transmit P (1) U = UART baud time = 1 / programmed baud rate. (2) P = 1/(SYSCLK1/6). SYSCLK1 clock is sourced from the main PLL. U1 TXD Stop/Idle Start U2 Bit 0 Bit 1 Bit N-1 Bit N U2 U3 Parity Stop Idle Start Figure 5-83. UART Transmit Timing Waveform Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 169 ADVANCE INFORMATION (2) P = 1/(SYSCLK1/6). SYSCLK1 clock is sourced from the main PLL. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com U7 RXD Bit N-1 Bit N Stop Start RTS Figure 5-84. UART RTS (RXD Stop to RTS Output) – Autoflow Timing Waveform U8 TXD Bit N-1 Bit N Stop Start Bit 0 CTS Figure 5-85. UART CTS (CTS to TXD Start Output) — Autoflow Timing Waveform ADVANCE INFORMATION For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the device TRM. 5.9.4.17 USB The USB 2.0 subsystem is fully-compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the device TRM. 5.9.5 Emulation and Debug Subsystem 5.9.5.1 IEEE 1149.1 Standard-Test-Access Port (JTAG) For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-Access Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.5.1.1 JTAG Electrical Data and Timing Table 5-103, Table 5-104, and Figure 5-86 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-103. Timing Requirements for IEEE 1149.1 JTAG NO. J1 MIN MAX UNIT Cycle time, TCK 23 ns J1H tw(TCKH) Pulse duration, TCK high (40% of tc) 9.2 ns J1L tw(TCKL) Pulse duration, TCK low(40% of tc) 9.2 ns J3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high 2 ns tsu(TMS-TCK) Input setup time, TMS valid to TCK high 2 ns th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns J4 170 tc(TCK) Specifications Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Table 5-104. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. J2 PARAMETER td(TCKL-TDOV) MIN Delay time, TCK low to TDO valid MAX UNIT 8.24 ns J1 J1L J1H TCK J2 TDO J4 J3 TDI / TMS ADVANCE INFORMATION Figure 5-86. JTAG Test-Port Timing Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Specifications 171 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 6 Detailed Description 6.1 Overview The 66AK2G0x SoC is a low-cost, low-power device based on TI KeyStone II (KS2) Multicore SoC architecture. It is optimized to achieve better power efficiency at similar performance compared to the preceding devices in the KS2 family. In addition to cost and power optimization, the device also integrates peripherals that facilitate industrial communications, control automotive and performance audio applications. It incorporates the performance-optimized Cortex-A15 and a C66x DSP core, built to meet the processing and system-level integration needs of automotive amplifiers, enterprise media gateway, focused end equipment (FEE), and broad-market applications (software-defined radio (SDR), ProAudio, emerging equipment that requires a low-power A15 or C66-class SoC). NOTE For more information on features, subsystems, and architecture of superset 66AK2G0x System on Chip (SoC), see the device TRM. ADVANCE INFORMATION 172 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 6.2 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Functional Block Diagram 66AK2G0x Industrial Subsystem 1x ARM® Cortex®–A15 1x C66x DSP 2x PRU-ICSS 1MB L2 w/ ECC Network Subsystem Memory Subsystem EMAC MSMC 1MB RAM w/ ECC PMMC eAVB/1588v2 RGMII/RMII/MII 7x Timers 64-bits EMIF 36-bits DDR3L w/ ECC NAVSS Queue Manager PKTDMA EDMA Semaphore ELM Display Subsystem 1x Video Pipeline Blend/Scale/CSC SA Crypto Engine Message Manager GPMC ADVANCE INFORMATION 512KB L2 w/ ECC LCD DPI TeraNet Automotive Interfaces Control Interfaces General Connectivity 6x ePWM 2x GPIO 2x eCAP 3x UART High-Speed Serial Interfaces PCIe® Single Lane Gen 2 3x eQEP 4x SPI 2x USB 2.0 2x DCAN MediaLB® MOST150 Audio Peripherals 3x McASP McBSP 3x I2C Media & Data Storage QSPI Dual Role + PHY 2x MMC/SD intro_001 Copyright © 2016, Texas Instruments Incorporated Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 173 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 6.3 www.ti.com ARM A15 The ARM Subsystem (ARMSS) of the SoC integrates a single Cortex-A15 processor with additional logic for bus protocol conversion, local power management, and various debug and trace enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar execution engine with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON™ technology) and VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large physical address extension), and multiprocessing extensions. The ARM Subsystem includes a 512KB L2 cache and support for AMBA4 AXI and AXI coherence extension (ACE) protocols. NOTE The ARM Subsystem is also referred to as ARM CorePac. ADVANCE INFORMATION The ARM subsystem supports the following key features: • ARM Cortex-A15 processor, full implementation of ARMv7-A architecture instruction set • 32KB L1 instruction (L1I) and data (L1D) caches • 512KB L2 cache • Super scalar, variable-length, out-of-order pipeline (12 stage in-order, 3-12 stage out-of-order) • 128-bit instruction fetch • 3-wide instruction decode • 3-wide instruction dispatch • 8-wide instruction issue • Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack, and an indirect predictor • Integrated Neon and VFP (Vector Floating Point unit) • Support for security and virtualization extensions • Error Correction Code (ECC) protection for L1 data cache and L2 cache, parity protection for L1 instruction cache • 32-entry fully-associative L1 Translation Look-aside Buffers (TLBs), for instruction fetch, data loads, and data stores • 512-entry 4-way set-associative L2 TLB • AMBA 4.0 AXI Coherency Extension (ACE) master port which is directly connected to MSMC (Multicore Shared Memory Controller) for low-latency access to shared MSMC SRAM • Dedicated ARM clocking (ARM_PLL) for full flexibility in performance trade-offs • Support for four integrated generic timers, in addition to 1 dedicated SoC-level watchdog timer (TIMER_5) • Support for invasive (stop-mode) and non-invasive (tracing, performance monitoring) debug modes and cross triggering for multiprocessor debugging • Support for processor instruction trace using Program Trace Macrocell (PTM) and data trace (printf style debug) using System Trace Macrocell (STM) • Support for up to 480 interrupt requests via the ARM Interrupt Controller (ARM INTC) module The ARM subsystem does not support the following features: • ACP (Accelarator Coherancy Port) Slave • Native AXI Master interface (only MSMC option is used) 174 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 The ARM subsystem integrates the following major blocks: • Single-core ARM Cluster • AXI2VBUS_MASTER • Debug and Trace components • ARM_VBUSP registers • ARM INTC • Global Timebase Counter (GTC) • Various interfaces for interaction with other SoC subsystems and modules For more information, see section ARM Cortex-A15 Subsystem in chapter Processors and Accelerators of the device TRM. 6.4 C66x DSP Subsystem The DSP sybsystem (C66x CorePac) supports the following key features: • Fixed/Floating-point C66x CPU based on a superset of the C64x+ and C67x+ ISA • Program Memory Controller (PMC): – 32KB Level 1 Program (L1P) Cache/SRAM • Data Memory Controller (DMC): – 32KB L1 Data (L1D) Cache/SRAM • Unified Memory Controller (UMC): – 1024KB L2 Cache/SRAM • External Memory Controller (EMC): – Internal DMA (IDMA) engine – One 128-bit VBUSM slave port from TeraNet_DMA – One 32-bit VBUSP master port to TeraNet_CFG • XMC (Extended Memory Controller): – One 256-bit port to MSMC controller • Multistream prefetch buffer • Address extension/translation (32-bit to 36-bit) • Memory protection for multiple segments • Memory protection for all internal L1/L2 RAM • Error Detection for L1P • Error Detection and Correction for L1D • Error Detection and Correction for all L2 • Integrated C66x CorePac interrupt controller (INTC) that works in conjunction with Chip-level Interrupt Controller (CIC) for distribution of system interrupts to the C66x core. Interrupts can be routed directly to the C66x core or through the CIC module in a flexible manner • Integrated leakage and dynamic power management • Debug/emulation capabilities: – Support for halt mode, real time and monitor mode debug capabilities – Support for processor instruction trace and system trace (printf-style debug) • Dedicated timer module (TIMER_0) for the C66x CorePac, integrated at SoC level. TIMER_0 can be used as either general-purpose timer or watchdog timer Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 175 ADVANCE INFORMATION The C66x DSP is the next-generation fixed-point and floating-point DSP. The new DSP enhances the C674x, which merged the C67x+ floating point and the C64x+ fixed-point instruction set architectures. The C66x DSP is object-code compatible with the C64x+ and C674x DSP. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Fore more information about: • C66x CorePac, see the TMS320C66x DSP CorePac User's Guide (SPRUGW0). • C66x CPU core, see the TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7). • C66x cache memory system, see the TMS320C66x DSP Cache User's Guide (SPRUGY8). • C66x debug/trace support, see chapter On-chip Debug of the device TRM. 6.5 C66x Cache Subsystem The purpose of this section is to provide an overview of the C66x cache memory architecture and to specify its configuration in this device. Details on the C66x cache functionality can be found in the TMS320C66x DSP Cache User Guide (SPRUGY8). The device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). Each memory has a unique location in the memory map (see chapter Memory Map of the device TRM). ADVANCE INFORMATION After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache. For more information, see section C66x Cache Subsystem in chapter Processors and Accelerators of the device TRM. 6.6 PRU-ICSS The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) consists of: • Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1) • Data RAMs per PRU core • Instruction RAMs per PRU core • Shared RAM • Peripheral modules • Interrupt controller (ICSS_INTC). The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device. The device has integrated two identical PRU subsystems (PRU-ICSS_0 and PRU-ICSS_1). The PRU cores within each PRU-ICSS have access to all resources on the SoC through the Interface Master port, and the external host processors can access the PRU-ICSS resources through the Interface Slave port. The 32-bit interconnect bus connects the various internal and external masters to the resources inside the PRU-ICSS. The PRU cores within the subsystems also have access to all resources on the SoC through the TeraNet DMA Interconnect. A subsystem local Interrupt Controller — ICSS_INTC handles system input events and posts events back to the device-level host CPUs. The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s instruction memory. 176 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 The PRU subsystem includes the following main features: • Two PRU CPUs: – 20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO) – Asynchronous capture [Serial Capture Unit (SCU)] with EnDat 2.2 protocol and Sigma-Delta demodulation support NOTE: There is no Sigma-Delta modulator inside the PRU. However, Sigma-Delta support is enabled through digital filtering hardware in the PRU to perform Sinc filtering. – Multiplier with accumulation (MAC) – CRC16 and CRC32 HW accelerator – 16-KB program RAM per PRU CPU (signified IRAM0 for PRU0 and IRAM1 for PRU1) with ECC – 8-KB data RAM per PRU CPU (signified RAM0 for PRU0 and RAM1 for PRU1) with ECC – Two high-performance master (initiator) ports on the TeraNet_DMA interconnect — one per PRU • 64-KB general purpose memory RAM (signified RAM2) with ECC, shared between PRU0 and PRU1 • One Scratch-Pad (SPAD) memory: – 3 Banks of 30 × 32-bit registers • Broadside direct connect between PRU cores within subsystem. Optional address translation for PRU transaction to External Host • 16 software events generated by two PRUs • One Ethernet MII_RT module (ICSS_MII_RT_CFG) with two MII ports and configurable connections to PRUs • One MDIO Port (ICSS_MII_MDIO) to control external Ethernet PHY • One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions: – One Industrial Ethernet 64-bit timer with 9 capture and 16 compare events with slow and fast compensation • 16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS • Enhanced Capture Module (eCAP_0) • Interrupt Controller (ICSS_INTC): – Up to 64 input events supported – Supports up to to 10 interrupt channels – Generation of 10 Host interrupts: 2 Host interrupts to PRU0 and PRU1, 1 Host interrupt to PRUICSS_0 and PRU-ICSS_1, 7 Host interrupts exported from the ICSS for signaling the ARM interrupt controllers (pulse and level provided) – Each system event can be enabled and disabled – Each host event can be enabled and disabled – Hardware prioritization of events • One 32-bit VBUSP slave (target) port for memory mapped register and internal memories access • Two (master and slave) 32-bit VBUSP ports for low-latency interface between PRU-ICSS subsystems • Flexible power management support • Integrated 32-bit interconnect • All memories support ECC For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) in chapter Processors and Accelerators of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 177 ADVANCE INFORMATION www.ti.com 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 6.7 6.7.1 www.ti.com Memory Subsystem MSMC The Multicore Shared Memory Controller (MSMC) manages traffic among the device ARM, DSP, DMA, other master peripherals, and the DDR EMIF controller. It also provides a shared on-chip SRAM that is accessible by the ARM, DSP and the master peripherals in the device. ADVANCE INFORMATION The MSMC module has the following features: • CPU/1 frequency of operation (that is, frequency same as that of the ARM/DSP) • One 256-bit master interface for connection to external SDRAM (through DDR EMIF controller) • One 256-bit master interface for connection to TeraNet_DMA • One 256-bit slave interface for the DSP • One 256-bit slave interface for the ARM • One 256-bit slave interface for accesses to the shared SRAM • One 256-bit slave interface for accesses to the external SDRAM • Memory protection for accesses to both the shared SRAM and external SDRAM spaces • Address extension from 32-bit to 36-bit for larger addressing space • Error Detection and Correction (EDC) and scrubbing support for the MSMC SRAM • Level 2 or Level 3 shared SRAM that is accessible by the device ARM, DSP and the master peripherals • Coherency between ARM L1/L2 cache and EDMA/system master peripherals (through SES/SMS ports) in the SRAM space and SDRAM space For more information, see section Multicore Shared Memory Controller (MSMC) in chapter Memory Subsystem of the device TRM. 6.7.2 DDR EMIF This section describes the DDR External Memory Interface (EMIF) for the device. The DDR EMIF controller supports: • DDR3L Memory device compliant to JEDEC JESD79-3F and JESD79-3-1 (DDR3L addendum) standards • 16-bit and 32-bit SDRAM data bus without ECC • 32-bit SDRAM data bus with 4-bit ECC • CAS latencies of 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 • CAS write latencies of 5, 6, 7, 8, 9, 10, 11, and 12 • 1, 2, 4, and 8 internal banks • Burst length of 8 • Sequential burst type • 4GB address space available over one chip select • 33-bit system address for address space of 4GB • Page sizes with 256, 512, 1024, and 2048 words • Self-refresh mode • Power-down mode • Output impedance calibration • On-Die Termination (ODT) • Prioritized refresh scheduling • Programmable SDRAM refresh rate and backlog counter • Programmable SDRAM timing parameters 178 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com • • Only little endian mode ECC on SDRAM data bus: – 8-bit ECC per 64-bit data quanta without additional cycle latency – 1-bit correction and 2-bit detection – Statistics for 1-bit ECC and 2-bit ECC errors – Programmable address ranges to define ECC protected region – ECC calculated and stored on all writes to ECC protected address region – ECC verified on all reads to ECC protected address region – Two ECC modes supported: • Read-Modify-Write (RMW) ECC enabled to support sub quanta accesses to the ECC space. • RMW ECC disabled Class of service UDIMM address mirroring. The DDR EMIF controller does not support: • Any memory types except DDR3L • RDIMMs • ECC for 16-bit mode • Single ended DQS • Mixed 8-bit and 16-bit SDRAM configurations • 4-bit SDRAMs. For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem of the device TRM. 6.7.3 GPMC The general-purpose memory controller (GPMC) is a unified memory controller dedicated for interfacing with external memory devices like: • Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices • Asynchronous, synchronous, and page mode (available only in nonmultiplexed mode) burst NOR flash devices • NAND flash • Pseudo-SRAM devices The main features of the GPMC are: • 8- or 16-bit-wide data path to external memory device • Supports up to 4 chip select regions of programmable size and programmable base addresses in a total address space of 1 GB • Supports on-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with 512-byte page size or greater) • Fully pipelined operation for optimal memory bandwidth usage • The clock to the external memory is provided from GPMC_FCLK divided by 1, 2, 3, or 4 • Supports programmable autoclock gating when no access is detected • Independent and programmable control signal timing parameters for setup and hold time on a per-chip basis. Parameters are set according to the memory device timing parameters with a timing granularity of one GPMC_FCLK clock cycle. • Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin monitoring • Support bus keeping Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 179 ADVANCE INFORMATION • • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • • • www.ti.com Support bus turnaround Prefetch and write posting engine associated with DMA controller at system level to achieve full performance from the NAND device with minimum effect on NOR/SRAM concurrent access 32-bit TeraNet slave interface which supports non-wrapping and wrapping burst of up to 16x32 bits. The GPMC supports the following various access types: • Asynchronous read/write access • Asynchronous read page access (4-, 8-, and 16- Word16) • Synchronous read/write access • Synchronous read/write burst access without wrap capability (4-, 8-, and 16- Word16) • Synchronous read/write burst access with wrap capability (4-, 8-, and 16- Word16) • Address-data-multiplexed (AD) access • Address-address-data (AAD) multiplexed access • Little-endian access only ADVANCE INFORMATION The GPMC can communicate with a wide range of external devices: • External asynchronous or synchronous 8-bit wide memory or device (non burst device) • External asynchronous or synchronous 16-bit wide memory or device • External 16-bit nonmultiplexed NOR flash device • External 16-bit address and data multiplexed NOR Flash device • External 8-bit and 16-bit NAND flash device • External 16-bit pseudo-SRAM (pSRAM) device For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory Subsystem of the device TRM. 6.7.4 ELM When reading from NAND flash memories, some level of error-correction is required. In the case of NAND modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is delegated to the memory controller. The general-purpose memory controller (GPMC) probes data read from an external NAND flash and uses this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The error-location module (ELM) extracts error addresses from these syndrome polynomials. Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and give the location of each error bit. The actual data is not required to complete the error-correction algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits. The maximum acceptable number of errors that can be corrected depends on a programmable configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM depends on a static and fixed definition of the generator polynomial for each error-correction level that corresponds to the generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction error levels). A larger number of errors than the programmed error-correction level may be detected, but the ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated computation exit status register. If the computation is successful, that is, if the number of errors detected does not exceed the maximum value authorized for the chosen correction capability, the exit status register contains the information on the number of detected errors. 180 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 When the error-location process completes, an interrupt is triggered to inform the software that its status can be checked. The number of detected errors and their locations in the NAND block can be retrieved from the module through register accesses. The ELM has the following features: • 4, 8, and 16 bits per 512-byte block error-location, based on BCH algorithms • Eight simultaneous processing contexts • Page-based and continuous modes • Interrupt generation on error-location process completion: – When the full page has been processed in page mode – For each syndrome polynomial in continuous mode. For more information, see section Error Location Module (ELM) in chapter Memory Subsystem of the device TRM. 6.8.1 Interprocessor Communication MSGMGR The SoC implements a single instance of the Message Manager to provide inter-processor communication between the various processing units: • ARM (Cortex-A15) • DSP (C66x) • PMMC (CPU) • PRU-ICSS (PRUs) The Message Manager is a hardware engine used for queuing messages in a secure and self-contained manner. There is no limitation on the message format or content. It is software responsibility to define the message format. The Message Manager provides a multi-core and multi-process safe message interface which allows multiple users (message senders and receivers) to access the queues without the need for any mutual exclusion. It also allows for secure and authorized access to the queues. The general features of the Message Manager module include: • Provides hardware acceleration for pushing/popping messages to/from logical queues • Supports the following SoC configuration: – 64 queues – Up to 128 pending messages – 64-byte messages – 32 proxies (single proxy per page) • Support for highly-pipelined push/pop operations • Support for self-contained mode with zero SW initialization • Provides a secure front-end for the queues • Provides flexible message allocation with ability to store the same message multiple times in different queues or multiple times in the same queue • Queue depth limited only by the maximum number of messages • Support for little-endian (LE) operation only Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 181 ADVANCE INFORMATION 6.8 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Monitoring and trace functions include: • Provides hardware signals to monitor the empty status for all transmit source queues • Provides ability to read Linking RAM contents for debug purposes • Provides ability to generate an interrupt when there are no free entries in the Linking RAM • Provides ability to generate an interrupt due to a proxy fault For more information, see section Message Manager in chapter Interprocessor Communication of the device TRM. 6.8.2 SEM This chapter describes the operation of the Semaphore hardware module. The Semaphore module is accessible across all the cores on a multicore environment. The module supports up to 64 independent semaphores that help the application to implement shared-resource protection mechanism across multiple cores. Each of the semaphores can be accessed by the cores in direct, indirect, or combined modes. ADVANCE INFORMATION In a multicore environment where system resources must be shared it is important to control simultaneous accesses to the available resources. To ensure correct system operation, it is necessary to limit access to a resource by one and only one core at a time; that is, it is necessary to provide mutual exclusion for resources shared across multiple cores. The Semaphore module provides a mechanism that applications can use to implement mutual exclusion of shared resources across multiple cores. The following CPU cores can be semaphore masters on this device: • DSP C66x • ARM Cortex-A15 • PMMC CPU • ICSS0_PRU0 • ICSS0_PRU1 • ICSS1_PRU0 • ICSS1_PRU1 The Semaphore module supports the following features: • Provides mutual exclusion for a shared resource • A maximum of 16 semaphore masters (device cores) • A maximum of 64 independent semaphores • Semaphore request methods: – Direct request – Indirect request – Combined request • Endian independent • Atomic semaphore access • Lock-out mechanism for used semaphores • Queued requests for used semaphores • Semaphores access grant interrupt for queued requests • Allows the application to check the status of any of the semaphores • Error detection and interrupts For more information, see section Semaphore Module in chapter Interprocessor Communication of the device TRM. 182 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 6.9 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 EDMA The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service userprogrammed data transfers between two memory-mapped slave endpoints on the device. Typical usage of the EDMA controller includes: • Servicing software-driven paging transfers (for example, data movement between external memory [such as SDRAM] and internal memory [such as DSP L2 SRAM]) • Servicing event-driven peripherals, such as a serial port • Performing sorting or sub-frame extraction of various data structures • Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the ARM CorePac The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The EDMACC serves to prioritize incoming software requests or events from peripherals and submits transfer requests (TR) to the EDMA transfer controller. The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets (TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller issues read/write commands to the source and destination addresses programmed for a given transfer. There are two EDMA controllers present on this device: • EDMA_0, integrating: – 1 Channel Controller, referenced as: EDMACC_0 – 2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1 (or EDMATC_1) • EDMA_1, integrating: – 1 Channel Controller, referenced as: EDMACC_1 – 2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1 (or EDMATC_3) The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to EDMA Channel Controllers functionality and features. The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and features. Each EDMACC has the following features: • Fully orthogonal transfer description: – 3 transfer dimensions: • Array (multiple bytes) • Frame (multiple arrays) • Block (multiple frames) – Single event can trigger transfer of array, frame, or entire block – Independent indexes on source and destination Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 183 ADVANCE INFORMATION The EDMA controller consists of two major principle blocks: • EDMA Channel Controller • EDMA Transfer Controller(s) 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • • • • ADVANCE INFORMATION • • • • www.ti.com Flexible transfer definition: – Increment or constant addressing modes – Linking mechanism allows automatic PaRAM set update – Chaining allows multiple transfers to execute with one event 64 DMA channels: – Channels triggered by either: • Event synchronization • Manual synchronization (CPU write to event set register) • Chain synchronization (completion of one transfer triggers another transfer) – Support for programmable DMA Channel to PaRAM mapping 8 Quick DMA (QDMA) channels: – QDMA channels are triggered automatically upon writing to PaRAM set entry – Support for programmable QDMA channel to PaRAM mapping 512 PaRAM sets: – Each PaRAM set can be used for a DMA channel, QDMA channel, or link set 2 transfer controllers/event queues: – 16 event entries per event queue Interrupt generation based on: – Transfer completion – Error conditions Debug visibility: – Queue water marking/threshold – Error and status recording to facilitate debug Memory protection support: – Proxied memory protection for TR submission – Active memory protection for accesses to PaRAM and registers Each EDMATC has the following features: • Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC manages the 3rd dimension) • Up to 4 in-flight transfer requests (TR) • Programmable priority levels • Support for increment or constant addressing mode transfers • Interrupt and error support • Supports only little-endian operation in this device • Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR For more information chapter EDMA Controller of the device TRM. 6.10 Peripherals 6.10.1 DCAN Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time applications. CAN has high immunity to electrical interference and the ability to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. The device supports two DCAN modules, referred to as DCAN_0 and DCAN_1, connecting to the CAN network through external (for the device) transceivers. The DCAN modules support bit rates up to 1 Mbit/s and are compliant to the CAN 2.0B Protocol Specification. 184 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 The DCAN module implements the following features: • Support for CAN protocol version 2.0 part A, B • Bit rates up to 1 Mbit/s • Dual clock source • 64 message objects in a dedicated message RAM • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Software module reset • Suspend mode for debug support • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM single error correction and double error detection mechanism (SECDED) • Direct access to message RAM during test mode. • Support for three interrupt lines: Level 0 and Level 1, and a separate ECC interrupt line • Local power down and wakeup support • Automatic message RAM initialization • Support for DMA access For more information, see section Dual Controller Area Network (DCAN) Interface in chapter Peripherals of the device TRM. 6.10.2 DSS The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS includes a DMA engine as part of the integrated Display Controller (DISPC) module, which allows direct access to the frame buffer (system memory). Various pixel processing capabilities are supported, such as: color space conversion, filtering, scaling, etc. The supported display interfaces (connections to external panel) are: • One parallel interface, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120. • One RFBI interface, supporting MIPI DBI 2.0. The modules integrated in DSS are: • Display Controller (DISPC), with the following main features – One Direct Memory Access (DMA) engine – One Video Pipeline (VID1) with color space conversion and in-loop up/down-scaling – One Overlay Manager (OVR1) – Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values) – One Video Port (VP1) with programmable timing generator to support up to 148.5 MHz pixel clock video formats defined in CEA-861-E and VESA DMT standards – Supported maximum FrameBuffer width of 4096 for all pixel formats – Configurable output mode: progressive or interlaced – Selection between RGB and YUV422 output pixel formats (YUV4:2:2 only available when BT-656 or BT-1120 output mode is enabled on the DPI interface) – Stall Mode support for RFBI Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 185 ADVANCE INFORMATION www.ti.com 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • www.ti.com Remote Frame Buffer Interface (RFBI) module, with the following main features: – Access to RFB direct "ARM interface": • Sending commands and data to the RFB panel, received from DISPC or from ARM (through the 32-bit interconnect slave port) • Reading data/status from the RFB through the 32-bit interconnect slave port – RFB interface: • 8/9/12/16-bit data bus (for up to QVGA @30fps) • Two programmable configurations for two peripheral devices connected to the RFBI module • Tearing Effect control logic: Horizontal Synchronization (HSync) and Vertical Synchronization (VSync) embedded in a single signal (TE) or using two signals (HS+VS) • Programmable pixel memory and output formats DSS provides two interfaces to SoC interconnect: • One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master port to read data from SoC system memory. • One 32-bit slave port. Used for configuration of the memory mapped registers inside DSS. It is further connected internally to DISPC and RFBI modules. ADVANCE INFORMATION For more information, see section Display Subsystem (DSS) in chapter Peripherals of the device TRM. 6.10.3 eCAP The enhanced Capture (eCAP) module can be used for: • Sample rate measurements of audio inputs • Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors) • Elapsed time measurements between position sensor pulses • Period and duty cycle measurements of pulse train signals • Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors. The eCAP module includes the following features: • 32-bit time base counter • 4-event time-stamp registers (each 32 bits) • Edge polarity selection for up to four sequenced time-stamp capture events • Interrupt on either of the four events • Single shot capture of up to four event time-stamps • Continuous mode capture of time-stamps in a four-deep circular buffer • Absolute time-stamp capture • Difference (Delta) mode time-stamp capture • All above resources dedicated to a single input pin • When not used in capture mode, the eCAP module can be configured as a single channel PWM output. For more information, see section Enhanced Capture (eCAP) Module in chapter Peripherals of the device TRM. 186 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 6.10.4 ePWM An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the ePWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly. In the further description the letter x within a signal or module name is used to indicate a generic ePWM instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the ePWM_x instance. Thus, EPWM1A and EPWM1B belong to ePWM_1, EPWM2A and EPWM2B belong to ePWM_2, and so forth. The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA and EPWMxB. A given ePWM module functionality can be extended with the so called High-Resolution Pulse Width modulator. ADVANCE INFORMATION Each ePWM module supports the following features: • Dedicated 16-bit time-base counter with period and frequency control • Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations: – Two independent PWM outputs with single-edge operation – Two independent PWM outputs with dual-edge symmetric operation – One independent PWM output with dual-edge asymmetric operation • Asynchronous override control of PWM signals through software • Programmable phase-control support for lag or lead operation relative to other ePWM modules • Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis • Dead-band generation with independent rising and falling edge delay control • Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions • A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs • Allows events to trigger both CPU interrupts and ADC start of conversions • Programmable event prescaling minimizes CPU overhead on interrupts • PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives. For more information, see section Enhanced PWM (ePWM) Module in chapter Peripherals of the device TRM. 6.10.5 eQEP A single track of slots patterns the periphery of an incremental encoder disk. These slots create an alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as index, marker, home position and zero reference. To derive direction information, the lines on the disk are read out by two different photo-elements that "look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB channel and vise versa. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 187 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Peripherals of the device TRM. ADVANCE INFORMATION 188 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 6.10.6 GPIO The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, user can write to an internal register to control the state driven on the output pin. When configured as an input, user can obtain the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA synchronization events in different interrupt/event generation modes. Each channel in the GPIO modules has the following features: • Supports 9 banks of 16 GPIO signals • Supports up to 9 banks of interrupt capable GPIOs • Interrupts: – Can enable interrupts for each bank of 16 GPIO signals – Interrupts can be triggered by rising and/or falling edge (or neither edge = disabled), specified for each interrupt capable GPIO signal • Set/clear functionality: – Software writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple software processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming). • Separate Input/Output registers: – Output register in addition to set/clear so that if preferred by software, some GPIO output signals can be toggled by direct write to the output register(s). – Output register, when read in, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device TRM. 6.10.7 I2C The multi-master inter-integrated circuit (I2C) peripheral provides an interface between the device and any I2C-bus-compatible device that is connected via the I2C serial bus. External components attached to the I2C bus can serially transmit/receive up to 8-bit data to/from the device through the two-wire I2C interface. Each I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus Specification (version 2.1): – Supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps) – Support for byte format transfer – 7-bit addressing mode – General call – START byte mode – Support for multiple master-transmitters and slave-receivers mode – Support for multiple slave-transmitters and master-receivers mode – Combined master transmit/receive and receive/transmit mode • 2 to 7 bit format transfer • Free data format mode Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 189 ADVANCE INFORMATION The device has two instances of GPIO144 modules (GPIO_0 and GPIO_1). The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 288 (2 instances × (9 banks x 16 pins)) pins. Since GPIO1_[143:68] are reserved in this Device, generalpurpose interface supports up to 212 pins. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • • • www.ti.com One read DMA event and one write DMA event that can be used by the DMA Seven interrupts that can be used by the CPU Module enable/disable capability I2C module unsupported features: • GPIO mode • High-speed (HS) mode • 10-bit device addressing mode The I2C module is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) Specification version 2.1. For more information, see section Inter-IC module (I2C) in chapter Peripherals of the device TRM. 6.10.8 McASP ADVANCE INFORMATION The Multi-channel Audio Serial Port (McASP) module functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP supports transmission and reception of time-division multiplexed (TDM) and Inter-IC Sound (I2S) protocols. In addition, it supports intercomponent digital audio interface transmission (DIT). The McASP consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. The McASP module also includes up to 16 serializers that can be individually enabled to either transmit or receive. The device integrates three McASP modules (McASP0, McASP1, and McASP2) with: • McASP0 supporting 16 serializers with independent TX/RX clock zones • McASP1 supporting 10 serializers with independent TX/RX clock zones • McASP2 supporting 6 serializers with independent TX/RX clock zones Each McASP module includes the following main features: • Up to 16 individually assignable serializers, each with its own data pins (AXR) • A single 32-bit buffer per serializer for transmit and receive operations • 2x interconnect slave interface ports: – A configuration (CFG) port – A slave DMA data port synchronized with functional clock • Two independent clock generator modules for transmit and receive: – Clocking flexibility allows the McASP to receive and transmit at different rates. For example, the McASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz. • Configurable functional clocks: – May be generated internally (master mode) – May be supplied by an external device (slave mode) – May be divided down internally • Independent transmit and receive modules, each providing: – Programmable clock and frame sync generator – TDM streams from 2 to 32, and 384 time slots – Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits – Data formatter for bit manipulation • Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC), codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components. • Support for wide variety of I2S and similar bit-stream formats 190 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 • • • • • • • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Integrated digital audio interface transmitter (DIT): – S/PDIF, IEC60958-1, AES-3 formats. – Enhanced channel status/user data RAM 384-slot TDM with external digital audio interface receiver (DIR) device: – For DIR reception, an external DIR receiver integrated circuit should be used with I2S output format and connected to the McASP receive section Support for 2x DMA requests (1 per direction) per each McASP module: – 1 level-sensitive transmit direct memory access (DMA) request common for all of the McASP serializers – 1 level-sensitive receive direct memory access (DMA) request common for all of the McASP serializers One transmit interrupt request common for all serializers per McASP module One receive interrupt request common for all serializers per McASP module Extensive error checking and recovery: – Transmit underruns and receiver overruns due to the system not meeting real-time requirements – Early or late frame sync in TDM mode – DMA error due to incorrect programming McASP Audio FIFO (AFIFO): – Provides additional data buffering – Provides added tolerance to variations in host/DMA controller response times – May be used as a DMA event pacer – Independent Read FIFO and Write FIFO – 256 bytes of RAM for each FIFO (read and write), where: • 256 bytes = four 32-bit words per serializer in the case of 16 data pins • 256 bytes = 64 32-bit words in the case of one data pin – Option to bypass Write FIFO and/or Read FIFO independently For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the device TRM. 6.10.9 McBSP The Multi-channel Buffered Serial Port (McBSP) provides a full-duplex serial communication interface between the device and other devices in a system. The primary use for the McBSP is for audio interface purposes. The main audio modes that are supported are the AC97 and I2S modes. In addition to the primary audio modes, the McBSP can be programmed to support other serial formats but is not intended to be used as a high-speed interface. The device communicates to the McBSP using 32-bit-wide control registers accessible via the internal peripheral bus. The McBSP provides the following functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or an internal, programmable frequency shift clock for data transfer In addition, the McBSP has the following capabilities: Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 191 ADVANCE INFORMATION www.ti.com 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • ADVANCE INFORMATION • • • • • • • www.ti.com Direct interface to: – T1/E1 framers – MVIP switching compatible and ST-BUS compliant devices including: • MVIP framers • H.100 framers • SCSA framers – IOM-2 compliant devices – AC97 compliant devices (the necessary multiphase frame synchronization capability is provided) – I2S compliant devices Multi-channel transmit and receive of up to 128 channels A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits μ-Law and A-Law companding 8-bit data transfers with the option of LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal clock and frame generation Additional McBSP Buffer FIFO (BFIFO): – Provides additional data buffering – Provides added tolerance to variations in host/DMA controller response times – May be used as a DMA event pacer – Independent Read FIFO and Write FIFO – 256 bytes of RAM for each FIFO (read and write) – Option to bypass Write FIFO and/or Read FIFO, independently McBSP module unsupported features: • The McBSP on this device does not support the SPI protocol. • 512 Channel Mode • Individual enable/disable channel control • Timeslot buffering • Super frame synchronization • ABIS Mode For more information, see section Multi-channel Buffered Serial Port (McBSP) in chapter Peripherals of the device TRM. 6.10.10 MLB The Media Local Bus subsystem (MLB) is based on a module designed by SMSC. This module provides a MediaLB/MediaLB+ controller and an interface to other MediaLB/MediaLB+ devices. The MediaLB/MediaLB+ interface allows also connection to a MOST (Media Oriented Systems Transport) network controller. The MLB supports the following features: • 3-pin MediaLB 3.3V LVCMOS I/Os compliant to MediaLB Physical Layer Specification v4.2 • 6-pin MediaLB+ low-voltage differential signaling (LVDS) I/Os (3 differential pairs) compliant to MediaLB Physical Layer Specification v4.2 • MediaLB core functionality compliant to MediaLB Physical Layer and Link Layer Specification v4.2 • Supports 256/512/1024Fs in 3-pin mode and 2048Fs in 6-pin mode • Supports all types of transfer (synchronous stream data, asynchronous packet data, control message data, and isochronous data) over 64 logical channels • Supports single 32-bit TeraNet_CFG slave interface for configuration 192 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com • • • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Supports single 32-bit TeraNet_DMA master interface with burst capability for DMA transfers into system memory. The maximum burst size is 32 Bytes Has 16 KB buffer for all types of transfers in the subsystem Dedicated BOOT_CFG bits for controlling the MLB priority on the system interconnect The MLB does not support: • 5-pin mode • Digital Transmission Content Protection (DTCP) cipher accelerators For more information, see section Media Local Bus (MLB) in chapter Peripherals of the device TRM. 6.10.11 MMC/SD The MMC/SD host controllers support the following main features: • Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC Standard Specification, v4.5. • Full compliance with SD command/response sets as defined in the SD Physical Layer Specification v3.01. • Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the SD part E1 Specification v3.00. • Full compliance with SD Host Controller Standard Specification sets as defined in the SD card Specification Part A2 v3.00. Main features of the MMC/SD host controllers: • Flexible architecture allowing support for new command structure • Designed for low power (Local Power Management) • Programmable clock generation • Card insertion/removal detection and write protect detection • The slave interface supports: – 32-bit wide data bus – Streaming burst supported only with burst length up to 7 – WNP supported • The master interface supports: – 32-bit wide data bus – Burst supported • Built-in 1024-byte buffer for read or write • Two DMA channels, one interrupt line • Support JC 64 v4.4.1 boot mode operations • Support SDA 3.00 Part A2 programming model • Support SDA 3.00 Part A2 DMA feature (ADMA2) Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 193 ADVANCE INFORMATION The multimedia card (MMC), secure digital (SD), and secure digital I/O (SDIO) high-speed controller (MMC/SD) provides an interface between a local host (LH) such as microprocessor unit (MPU) or digital signal processor (DSP) and either MMC, SD memory card, or SDIO card and handles MMC, SD, and SDIO transactions with minimal LH intervention. There are two MMC/SD host controllers inside the device. Each controller has an 8-bit wide data bus. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • • • www.ti.com Supported data transfer rates: – MMC0 supports the following data transfer rates (eMMC/SD): • SDR12 (3.3 V IOs): up to 12 MBps (24 MHz clock) • SDR25 (3.3 V IOs): up to 24 MBps (48 MHz clock) • HS mode (3.3 V IOs): up to 24 MBps (48 MHz clock) • DS mode (3.3 V IOs): up to 12 MBps (24 MHz clock) • Default SD mode 1-bit data transfer up to 24 Mbps (3 MBps) – MMC1 supports the following data transfer rates (eMMC): • SDR12 (1.8 V IOs): up to 12 MBps (24 MHz clock) • SDR25 (1.8 V IOs): up to 24 MBps (48 MHz clock) • DDR50 (1.8 V IOs): up to 48 MBps (48 MHz clock) • 1.8 V legacy modes with 1/4/8-bit single data rate at up to 26 MHz bus clock MMC0 Supports 3.3-V IO modes only MMC1 Supports 1.8-V IO modes only ADVANCE INFORMATION The differences between the MMC/SD host controller and a standard SD host controller defined by the SD Card Specification, Part A2, SD Host Controller Standard Specification, v3.00 are: • The clock divider in the MMC/SD host controller supports a wider range of frequency than specified in the SD Memory Card Specifications, v3.0. The MMC/SD host controller supports odd and even clock ratio. • The MMC/SD host controller supports configurable busy time-out. • ADMA2 64-bit mode is not supported. • There is no external LED control. The following features are not supported: • Byte or half-word accesses. Only word accesses to the slave port are supported. • MMC Out-of-band interrupt. • Dual voltage I/O (MMC0 Supports 3.3-V only. MMC1 Supports 1.8-V only). • No built-in hardware support for error correction codes (ECC). • SPI transfers are not supported. • Module doesn’t support card insertion/removal sensing with pull up resistor on MMCi_DAT[3] data bus line as specified in the SD Physical Layer Specification. For more information, see section Multimedia Card High Speed Interface (MMC/SD) in chapter Peripherals of the device TRM. 6.10.12 NSS Networking Subsystem (NSS) consists of DMA/Queue Management components – Navigator Subsystem (NAVSS), an Ethernet MAC (EMAC) Subsystem, and a packet Security Accelerator (SA). The NSS, presented by its general sub-components, supports the following features: 194 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 • • • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 NAVSS: – High Performance CPPI DMA Controller, 32 Receive Flows, 4 Loopback threads for infrastructure mode – CPPI Queue Manager (QM) features: • Single QM • Supports up to 128 queues – 21 QPEND signals for TX use, remaining 107 QPEND signals are for host use • 2048 buffers supported in Internal Linking RAM • Two Queue Proxies provided for host interaction (one per DSP and ARM): – Queue Proxy 0 assigned to DSP – Queue Proxy 1 assigned to ARM – Support for SER protection (SECDED) EMAC Subsystem: – One Gigabit Ethernet port: MII/RMII/RGMII interfaces: • Supports 10-, 100-, 1000-Mbps full duplex • Supports 10-, 100-Mbps half duplex – One Host Port 0 CPPI Streaming Packet Interface (PSI) – Support Ethernet Audio/Video Bridging (eAVB) (P802.1Qav/D6.0) – Maximum frame size 2016 bytes (2020 bytes with VLAN) – Eight priority level QOS support (802.1p) – IEEE 1588v2 (2008 annex D, annex E, and annex F) to facilitate Audio/Video bridge 802.1AS Precision Time Protocol: • Timestamp module capable of time stamping external timesync events like Pulse Per Second and also generating Pulse Per Second outputs • CPTS module that supports time stamping for IEEE 1588v2 with support for 8 hardware push events and generation of compare output pulses – DSCP Priority Mapping (IPv4 and IPv6) – Maximum frame size 2016 bytes (2020 with VLAN) – Address Lookup Engine (ALE) – Castagnoli or Ethernet CRC selectable for Ethernet ingress and egress (Host Port0 CRC is Ethernet only) – MDIO module for PHY management – EtherStats and 802.3Stats RMON statistics gathering – Support for SER protection (SECDED) Security Accelerator (SA): – Support IPSec and SRTP protocol stack – Support various encryption modes and algorithms such as: • ECB, CBC, CFB, OFB, F8, CTR, CBC-MAC, CCM, GCM, GMAC and AES-CMAC • AES, DES, 3DES, SHA-1, SHA-2 (224, 256-bit operation) and MD5 – Support for True random number generator (TRNG) and Public Key Accelerator (PKA) – Support for SER protection (SECDED) The NSS does not support the following features: • No external queue RAM supported • Priority Based Flow Control is not supported. • No Castignoli CRC to Host CPPI port. For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 195 ADVANCE INFORMATION www.ti.com 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 6.10.13 PCIESS Peripheral Component Interconnect Express (PCIE) controllers provide a high-speed glueless serial interconnect to peripherals utilizing high bandwidth applications. PCIe module is a multi-lane I/O interconnect that provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane, per direction, for serial links on backplanes and printed curcuit boards. It is a 2nd generation I/O interconnect technology succeeding PCI and ISA bus designed to be used as a general-purpose serial I/O interconnect. It is also used as a bridge to other interconnects such as SATA, USB2/3.0, GbE MAC, and so forth. The PCI Express standard's predecessor - PCI, is a parallel bus architecture that is increasingly difficult to scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its practical performance limits while simplifying the interface design. ADVANCE INFORMATION PCIe module supports the following features: • Dual operation mode: Root Complex (RC) or End Point (EP) • Supports a single bidirectional link interface (a single input port and a single output port) with one lane • Operated at a raw speed of 2.5 Gbps or 5.0 Gbps per lane per direction • Maximum outbound payload size of 128 bytes • Maximum inbound payload size of 256 bytes • Maximum remote read request size of 256 bytes • Ultra-low transmit and receive latency • Support for dynamic-width conversion • Automatic lane reversal • Polarity inversion on receive • Single virtual channel (VC) • Single traffic class (TC) • Single function in End Point (EP) mode • Automatic credit management • ECRC generation and checking • PCI device power management with the exception of D3cold with Vaux • PCI Express active state power management (ASPM) state L0s and L1 • PCI Express link power management states, except L2 state • PCI Express advanced error reporting • PCI Express messages for both transmit and receive • Filtering for posted, non-posted, and completion traffic • Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout • Access to configuration space registers and external application memory-mapped registers through BAR0 and through configuration access • Legacy interrupts reception (in RC) and generation (in EP) • MSI generation and reception • PHY loopback in RC mode PCIe module does not support the following features: • No support for multiple lanes • No support for multiple VCs • No support for multiple TCs 196 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com • • • • • • • • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 No support for function-level reset No support for PCI Express beacon for in-band wake No built-in hardware support for hot-plug No support for vendor messaging No support for I/O access in inbound direction in RC or EP mode No support for addressing modes other than incremental for burst transactions. Thus, the PCIe addresses cannot be in cacheable memory space No auxiliary power to maintain controller context when rezuming from D3cold state No support for L2 link state For more information, see section Peripheral Component Interconnect Express Subsystem (PCIe SS) in chapter Peripherals of the device TRM. The Quad Serial Peripheral Interface (QSPI™) module is a kind of Serial Peripheral Interface (SPI) module which allows single, dual or quad read and write access to external flash devices. This module has a memory mapped register interface, which provides a direct memory interface for accessing data from external flash devices, simplifying software requirements. The QSPI module has the following features: • Memory-Mapped Direct mode of operation for performing flash data transfers and executing code from flash memory. • Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive flash data transfers. • Local SRAM to reduce bus overhead and buffer flash data during indirect transfers. • Set of software accessible flash control registers to perform any flash command, including data transfers up to 8-bytes at a time. • Supports any device clock frequency, including frequencies of 96 MHz (QSPI mode 0 only). • Supports XIP (Execute in Place), also referred to as continuous mode. • Supports single, dual or quad I/O instructions. • Supports 16/32/64 byte cacheline wrap accesses. • Supports ECC for its internal SRAM buffer. • Programmable device sizes. • Programmable write protected regions to block system writes from taking effect. • Programmable delays between transactions. • Legacy mode allowing software direct access to low level transmit and receive FIFOs bypassing the higher layer processes. • Independent reference clock to decouple bus clock from SPI clock – allows slow system clocks. • Serial clock with programmable polarity. • Programmable baud rate generator to generate QSPI clocks. • Features included to improve high speed read data capture mechanism. • Option to use adapted clocks to further improve read data capturing. • Programmable interrupt generation. • Up to four external chip selects. • Supports Little-endian operation only. For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 197 ADVANCE INFORMATION 6.10.14 QSPI 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 6.10.15 SPI The SPI module is a master/slave high-speed synchronous serial input/output interface that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bittransfer rate. There are four separate SPI modules (SPI0, SPI1, SPI2, and SPI3) in the device. All these four modules support up to two external devices (two chip selects) and are able to work as both master and slave. The SPI module allows multiple programmable chip-selects. It is normally used for communication between the device and external peripherals. Typical applications include interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMS, and analog-to-digital converters. The SPI module may be used to connect to serial flash memory devices for booting. The SPI module supports EDMA events and can be used in conjunction with EDMA for data transfer with minimal CPU overhead. ADVANCE INFORMATION The SPI module has the following features: • 16-bit Shift register • 16-bit Receive buffer register and 16-bit Receive buffer emulation alias register • 16-bit Transmit data register and 16-bit Transmit data and format selection register • 8-bit Baud clock generator • Serial clock (SPIm_CLK) I/O pin • Slave in, master out (SPIm_SIMO) I/O pin • Slave out, master in (SPIm_SOMI) I/O pin • 2 Chip select signals (SPIm_SCSn0 and SPIm_SCSn1) • Programmable SPI clock frequency range • Programmable character length (2 to 16 bits) • Programmable clock phase (delay or no delay) • Programmable clock polarity (high or low) • Interrupt capability • DMA support (read/write synchronization events) • Operates at up to 50 MHz in master mode and 25 MHz in slave mode (actual speed depends on SPI functional clock and SPI clock divider) The SPI module allows software to program the following options: • SPIm_CLK frequency (SPI functional clock / 2 through SPI functional clock / 256) • 3-pin and 4-pin options • Character length (2 to 16 bits) and shift out direction (MSB/LSB first) • Clock phase (delay or no delay) and polarity (high or low) • Delay between transmissions in master mode • Chip select setup and hold times in master mode • Chip select hold in master mode The SPI module does not support the following features: • Multibuffer mode • Parallel mode and parity • GPIO mode For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the device TRM. 6.10.16 Timers There are total of 7 chip-level timers. 198 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 The device includes several types of timers used by the system software, including general-purpose (GP) timers, watchdog timers, and a wake-up timer, as it follows: • TIMER_0 is dedicated/tightly coupled for C66x CorePac. TIMER_0 can be used as general-purpose timer or watchdog timer • TIMER_1 through TIMER_4 are general-purpose timers • TIMER_5 is dedicated/tightly coupled for the ARM core 0. TIMER_5 can be used as general-purpose timer or watchdog timer • TIMER_6 is dedicated as device wake-up timer by interrupting PMMC CPU. TIMER_6 cannot be used by high-level software as a general-purpose timer or watchdog. TIMER_6 is neither connected to Timer pin manager block nor to Timer IOs. – On-the-fly read/write register (while counting) At the chip level there are 4 timer pins — two input pins (TIMI[1:0]) and two output pins (TIMO[1:0]). Each of TIMER_0 through TIMER_5 input can be configured to be driven by the timer input pins. Each of TIMO[1:0] output pin can be driven by any of the timer outputs. The selection of timer inputs and outputs is controlled by Timer pin manager. The Timer pin manager block is controlled by registers in BOOT_CFG module. For more information, see section Timers in chapter Peripherals of the device TRM. 6.10.17 UART The Universal Asynchronous Receiver/Transmitter peripheral is 16550 standard compatible asynchronous communications element. The UART can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. There are 3 UART (UART_0, UART_1 and UART_2) modules in the device. Only UART_0 supports full modem control functions. Each UART can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices. The UART_i (where i = 0 to 2) include the following features: • 16550 standard compatible • 16-byte FIFO buffer for receiver and 16-byte FIFO for transmitter • Baud generation based on programmable divisors operating from a fixed functional clock of 192 MHz • Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two options: – Baud rate = (functional clock / 16) / N – Baud rate = (functional clock / 13) / N • Break character detection and generation • Configurable data format: – Data bit: 5, 6, 7, or 8 bits – Parity bit: Even, odd, none – Stop-bit: 1, 1.5, 2 bit(s) • Flow control: Hardware (RTS/CTS) • The 192 MHz functional clock option allows baud rates up to 12Mbps The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 199 ADVANCE INFORMATION Each timer has two input pins (TINPL and TINPH) and two output pins (TOUTL and TOUTH). 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the device TRM. 6.10.18 USB Similar to earlier versions of USB bus, USB 2.0 is a general-purpose cable bus, supporting data exchange between a host device and a wide range of simultaneously accessible peripherals. The device supports two USB 2.0 subsystems with High Speed Dual-Role-Device (DRD) ports with integrated PHY. ADVANCE INFORMATION The USB 2.0 subsystem, supports the following USB features: • Dual-role-device (DRD) capability: – Supports USB 2.0 Peripheral (or Device) mode at Highspeed (480 Mbps) and Fullspeed (12 Mbps) – Supports USB 2.0 Host mode at Highspeed (480 Mbps), Fullspeed (12 Mbps), and Lowspeed (1.5 Mbps) – USB 2.0 static peripheral operation – USB 2.0 static host operation – xHCI Debug Capability – External Buffer Control (EBC) mode for IN (Tx) Endpoint • Each controller instance contains single xHCI with the following features: – Compatible to the xHCI Specification (Revision 1.1) in Host mode – Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is bidirectional – Internal DMA controller – Interrupt moderation and blocking – Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous – Supports high bandwidth ISO mode – Descriptor caching and data pre-fetching used to improve system performance – Dynamic FIFO memory allocation for all endpoints • Operation flexibility: – Uniform programming model for HS, FS, and LS operation – Multiple interrupt lines: • 16 interrupts associated with 16 programmable Event Rings for multi-core support • A MISC interrupt line for all miscellaneous events • ECC RAM • External requirements: – An external charge pump for VBUS 5 V generation – An external reference clock input for USB PHY operation – An external high-precision resistor for internal PHY termination calibration The following are USB features which are not supported: • USB 3.0 SuperSpeed (5 Gbps) or USB3.1 SuperSpeed+ (10 Gbps) operation in either host or device modes • OTG Functionality • HSIC (High Speed inter-chip) • ULPI Interface for external PHY • Battery Charger Support • Accessory Charger Adaptor Support • xHCI Virtualization • Hibernation (separate power domain for wake up from USB and save/ restore on wakeup) mode 200 Detailed Description Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com • SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 External Buffer Control (EBC) for OUT (Rx) Endpoint ADVANCE INFORMATION For more information, see section Universal Serial Bus Subsystem (USB) in chapter Peripherals of the device TRM. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Detailed Description 201 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 7 Applications, Implementation, and Layout NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test design implementation to confirm system functionality. 7.1 DDR3L Board Design and Layout Guidelines 7.1.1 DDR3L General Board Layout Guidelines ADVANCE INFORMATION To • • • • • • • • • • • 7.1.2 help ensure good signaling performance, consider the following board design guidelines: Avoid crossing splits in the power plane. Minimize Vref noise. Use the widest trace that is practical between decoupling capacitors and memory module. Maintain a single reference. Minimize ISI by keeping impedances matched. Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities. Use proper low-pass filtering on the Vref pins. Keep the stub length as short as possible. Add additional spacing for on-clock and strobe nets to eliminate crosstalk. Maintain a common ground reference for all bypass and decoupling capacitors. Take into account the differences in propagation delays between microstrip and stripline nets when evaluating timing constraints. DDR3L Board Design and Layout Guidelines 7.1.2.1 Board Designs TI only supports board designs using DDR3L memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3L memory controller are shown in Table 7-1 and Figure 7-1. Table 7-1. Switching Characteristics Over Recommended Operating Conditions for DDR3L Memory Controller NO. 1 PARAMETER tc(DDR3_CLKOUT_P/N) MIN Cycle time, DDR3_CLKOUT_P/N 2.5 MAX (1) 3.3 UNIT ns (1) This is the absolute maximum value of the clock period. Actual maximum clock period may be limited by DDR3L speed grade and operating frequency (see the DDR3L memory device data sheet). 1 DDR3_CLKOUT_P/N Figure 7-1. DDR3L Memory Controller Clock Timing 202 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 7.1.2.2 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 DDR3L Device Combinations Because there are several possible combinations of device counts and single- or dual-side mounting, Table 7-2 summarizes the supported device configurations. Table 7-2. Supported DDR3L Device Combinations NUMBER OF DDR3L DEVICES DDR3L DEVICE WIDTH (BITS) MIRRORED? DDR EMIF WIDTH (BITS) 1 16 N 16 2 8 Y(1) 16 2 16 N 32 2 16 3 16 N 32 4 8 N 32 4 8 5 8 Y (1) Y (2) N 32 32 3 (2) This is two mirrored pairs of DDR3L devices. 7.1.2.3 DDR3L Interface Schematic 7.1.2.3.1 32-Bit DDR3L Interface The DDR EMIF schematic varies, depending upon the width of the DDR3L devices used and the width of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR devices look like two 8-bit devices. Figure 7-2 and Figure 7-3 show the schematic connections for 32-bit interfaces using x16 devices. 7.1.2.3.2 16-Bit DDR3L Interface Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 7-2 and Figure 7-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off. When not using all or part of the DDR EMIF, the proper method of handling the unused pins is to tie off the DDR3_DQS*_Pi pins to ground via a 1k-Ω resistor and to tie off the DDR3_DQS*_Ni pins to the corresponding DVDD_DDR supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection against external electrical noise causing activity on the signals. The DVDD_DDR and DDR3_VREFSSTL power supply pins need to be connected to their respective power supplies even if the DDR EMIF is not being used. All other DDR EMIF pins can be left unconnected. Note: The only DDR EMIF configurations supported are 32-bits wide, 16-bits wide, or not used. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 203 ADVANCE INFORMATION (1) Two DDR3L devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of the board. 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 32-bit DDR EMIF 16-Bit DDR3L Devices DDR3_D31 DQ15 8 DDR3_D24 DQ8 DDR3_DQM3 DDR3_DQS3_P DDR3_DQS3_N UDM UDQS UDQS DDR3_D23 DQ7 8 DDR3_D16 DQ0 DDR3_DQM2 DDR3_DQS2_P DDR3_DQS2_N LDM LDQS LDQS DDR3_D15 DQ15 8 DDR3_D8 DQ8 DDR3_DQM1 DDR3_DQS1_P DDR3_DQS1_N UDM UDQS UDQS ADVANCE INFORMATION DDR3_D7 DQ7 8 DDR3_D00 DQ0 DDR3_DQM0 DDR3_DQS0_P DDR3_DQS0_N LDM LDQS LDQS DDR3_CLKOUT_P DDR3_CLKOUT_N DDR3_ODT0 DDR3_CEn0 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_A00 Zo CK CK CK CK ODT CS BA0 BA1 BA2 ODT CS BA0 BA1 BA2 A0 A0 Zo A15 A15 Zo CAS RAS WE CKE RST ZQ VREFDQ VREFCA CAS RAS WE CKE RST 0.1 µF DVDD_DDR Zo DDR_VTT 16 DDR3_A15 DDR3_CASn DDR3_RASn DDR3_WEn DDR3_CKE0/1 DDR3_RESETn ZQ DDR3_VREFSSTL 0.1 µF 0.1 µF DDR_VREF ZQ VREFDQ VREFCA ZQ 0.1 µF Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR memory device data sheet. Figure 7-2. 32-Bit, One-Bank DDR EMIF Interface Schematic Using Two 16-Bit DDR3L Devices 204 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 32-bit DDR EMIF 8-Bit DDR3L Devices 8-Bit DDR3L Devices DDR3_D31 DQ7 8 DDR3_D24 DQ0 DDR3_DQM3 NC DDR3_DQS3_P DDR3_DQS3_N DDR3_D23 DM/TQS TDQS DQS DQS DQ7 8 DDR3_D16 DQ0 DDR3_DQM2 NC DDR3_DQS2_P DDR3_DQS2_N DDR3_D15 DM/TQS TDQS DQS DQS DQ7 8 DDR3_D8 DQ0 DDR3_DQM1 NC DDR3_DQS1_P DDR3_DQS1_N DDR3_D7 DM/TQS TDQS DQS DQS DDR3_D00 DQ0 DDR3_DQM0 NC DDR3_DQS0_P DDR3_DQS0_N DDR3_CLKOUT_P* DDR3_CLKOUT_N* DM/TQS TDQS DQS DQS DDR3_ODT0 DDR3_CEn0 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_A00 Zo CK CK CK CK CK CK 0.1 µF CK CK DVDD_DDR Zo ODT CS BA0 BA1 BA2 ODT CS BA0 BA1 BA2 ODT CS BA0 BA1 BA2 ODT CS BA0 BA1 BA2 A0 A0 A0 A0 Zo A15 A15 A15 A15 Zo CAS RAS WE CKE RST ZQ VREFDQ VREFCA CAS RAS WE CKE RST CAS RAS WE CKE RST ZQ VREFDQ VREFCA CAS RAS WE CKE RST DDR_VTT 16 DDR3_A15 DDR3_CASn DDR3_RASn DDR3_WEn DDR3_CKE0/1 DDR3_RESETn ZQ DDR3_VREFSSTL 0.1 µF 0.1 µF ZQ VREFDQ VREFCA 0.1 µF ZQ ZQ 0.1 µF ZQ VREFDQ VREFCA DDR_VREF ZQ 0.1 µF Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR memory device data sheet. Figure 7-3. 32-Bit, One-Bank DDR EMIF Interface Schematic Using Four 8-Bit DDR3L Devices Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 205 ADVANCE INFORMATION DQ7 8 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 7.1.2.4 www.ti.com Compatible JEDEC DDR3L Devices Table 7-3 shows the parameters of the JEDEC DDR3L devices that are compatible with this interface. Table 7-3. Compatible JEDEC DDR3L Devices NO. PARAMETER 1 JEDEC DDR3L device speed grade(1) 2 JEDEC DDR3L device bit width CONDITION MIN DDR clock rate ≤ 400 MHz 800 (2) 3 JEDEC DDR3L device count MAX UNIT MT/s x8 x16 Bits 2 5 Devices (1) Refer to Table 7-1 Switching Characteristics Over Recommended Operating Conditions for DDR3L Memory Controller for the range of supported DDR clock rates. (2) For valid DDR3L device configurations and device counts, see Section 7.1.2.2, Figure 7-2, and Figure 7-3. 7.1.2.5 PCB Stackup ADVANCE INFORMATION The minimum stackup for routing the DDR EMIF interface is a six-layer stack up as shown in Table 7-4. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in Table 7-5. Table 7-4. Six-Layer PCB Stackup Suggestion LAYER TYPE DESCRIPTION 1 Signal Top routing mostly vertical 2 Plane Ground 3 Plane Split power plane 4 Plane Split power plane or Internal routing 5 Plane Ground 6 Signal Bottom routing mostly horizontal Table 7-5. PCB Stackup Specifications NO. PARAMETER MIN PS1 PCB routing/plane layers 6 PS2 Signal routing layers 3 PS3 Full ground reference layers under DDR3L routing region(1) 1 PS4 Full 1.5-V power reference layers under the DDR3L routing region(1) TYP MAX UNIT 1 (2) PS5 Number of reference plane cuts allowed within DDR3L routing region PS6 Number of layers between DDR3L routing layer and reference plane(3) 0 PS7 PCB routing feature size PS8 PCB trace width, w 4 PS9 Single-ended impedance, Zo 40 75 Ω PS10 Impedance control(5) Z Z+5 Ω 0 4 Z-5 Mils Mils (1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (2) No traces should cross reference plane cuts within the DDR3L routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation. (3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape. (5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9. 206 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 7.1.2.6 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Placement Figure 7-4 shows the required placement for the processor as well as the DDR3L devices. The dimensions for this figure are defined in Table 7-6. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3L devices are omitted from the placement. x3 x2 y1 ADVANCE INFORMATION x1 y2 y2 DDR3 Controller y2 y2 y2 PCB_DDR3_3 Figure 7-4. Placement Specifications Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 207 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 7-6. Placement Specifications DDR3L MAX UNIT KOD31 NO. X1 PARAMETER MIN 500 Mils KOD32 X2 600 Mils KOD33 X3 600 Mils KOD34 Y1 1800 Mils KOD35 Y2 600 Mils KOD36 DDR3L keepout region (1) KOD37 Clearance from non-DDR3L signal traces to DDR3L signal traces 4 (2) W (1) DDR3L keepout region to encompass entire DDR3L routing area. (2) Non-DDR3L signals allowed within DDR3L keepout region provided they are separated from DDR3L routing layers by a ground plane. 7.1.2.7 DDR3L Keepout Region ADVANCE INFORMATION The region of the PCB used for DDR3L circuitry must be isolated from other signals. The DDR3L keepout region is defined for this purpose and is shown in Figure 7-5. The size of this region varies with the placement and DDR3L routing. Additional clearances required for the keepout region are shown in Table 7-6. Non-DDR3L signals should not be routed on the DDR3L signal layers within the DDR3L keepout region. Non-DDR3L signals may be routed in the region, provided they are routed on layers separated from the DDR3L signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the DVDD_DDR power plane should cover the entire keepout region. Also note that the two signals from the DDR3L controller should be separated from each other by the specification in Table 7-6 (see KOD37). 208 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 DDR3L Keepout Region ADVANCE INFORMATION DDR3 Controller PCB_DDR3_3 Figure 7-5. DDR3L Keepout Region Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 209 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 7.1.2.8 www.ti.com Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3L and other circuitry. Table 7-7 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DDR EMIF controller and DDR3L devices. Additional bulk bypass capacitance may be needed for other circuitry. Table 7-7. Bulk Bypass Capacitors NO. PARAMETER MIN MAX UNIT 1 DVDD_DDR bulk bypass capacitor count(1) 1 Devices 2 DVDD_DDR bulk bypass total capacitance 22 μF (1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3L signal routing. 7.1.2.9 High-Speed Bypass Capacitors ADVANCE INFORMATION High-speed (HS) bypass capacitors are critcal for proper DDR3L interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 7-8 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to: 1. Fit as many HS bypass capacitors as possible. 2. Minimize the distance from the bypass cap to the pins/balls being bypassed. 3. Use the smallest physical sized capacitors possible with the highest capacitance readily available. 4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible. 5. Minimize via sharing. Note the limites on via sharing shown in Table 7-8. Table 7-8. High-Speed Bypass Capacitors NO. PARAMETER MIN TYP MAX UNIT 0201 0402 10 Mils 1 HS bypass capacitor package size(1) 2 Distance, HS bypass capacitor to processor being bypassed(2)(3)(4) 3 Processor HS bypass capacitor count per DVDD_DDR rail (12) See Section 7.3 and (11) Devices 4 Processor HS bypass capacitor total capacitance per DVDD_DDR rail (12) See Section 7.3 and (11) μF 400 (5) 5 Number of connection vias for each device power/ground ball 6 Trace length from device power/ground ball to connection via(2) 7 Distance, HS bypass capacitor to DDR3L device being bypassed(6) 8 DDR3L device HS bypass capacitor count(7) 9 DDR3L device HS bypass capacitor total capacitance(7) 10 Number of connection vias for each HS capacitor(8)(9) 11 Trace length from bypass capacitor connect to connection via(2)(9) Mils Vias 35 70 150 12 (10) 12 Number of connection vias for each DDR3L device power/ground ball 13 Trace length from DDR3L device power/ground ball to connection via(2)(8) Mils Mils Devices 0.85 μF 2 Vias 35 100 35 60 1 Mils Vias Mils (1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor. (2) Closer/shorter is better. (3) Measured from the nearest processor power/ground ball to the center of the capacitor package. (4) Three of these capacitors should be located underneath the processor, between the cluster of DVDD_DDR balls and ground balls, between the DDR3L interfaces on the package. (5) See the Via Channel™ escape for the processor package. (6) Measured from the DDR3L device power/ground ball to the center of the capacitor package. (7) Per DDR3L device. (8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board. 210 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (9) An HS bypass capacitor may share a via with a DDR3L device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR3L device pad should be less than 150 mils. (10) Up to a total of two pairs of DDR power/ground balls may share a via. (11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself. (12) For more information, see Section 7.3, Power Distribution Network Implementation Guidance. 7.1.2.9.1 Return Current Bypass Capacitors Use additional bypass capacitors if the return current reference plane changes due to DDR3L signals hopping from one signal layer to another. The bypass capacitor here provides a path for the return current to hop planes along with the signal. As many of these return current bypass capacitors should be used as possible. Because these are returns for signal current, the signal via size may be used for these capacitors. Table 7-9 lists the clock net classes for the DDR EMIF. Table 7-10 lists the signal net classes, and associated clock net classes, for signals in the DDR EMIF. These net classes are used for the termination and routing rules that follow. Table 7-9. Clock Net Class Definitions CLOCK NET CLASS CK PROCESSOR PIN NAMES DDR3_CLKOUT_N* / DDR3_CLKOUT_P* DQS0 DDR3_DQS0_P / ddrx_dqsn0 DQS1 DDR3_DQS0_P / DDR3_DQS0_N DQS2(1) DDR3_DQS1_P / DDR3_DQS1_N (1) DDR3_DQS2_P / DDR3_DQS2_N DQS3 (1) Only used on 32-bit wide DDR3L memory systems. Table 7-10. Signal Net Class Definitions SIGNAL NET CLASS ASSOCIATED CLOCK NET CLASS ADDR_CTRL CK DQ0 DQS0 DDR3_D[7:0], DDR3_DQM0 PROCESSOR PIN NAMES DDR3_BA[2:0], DDR3_A[14:0], DDR3_CEn0, DDR3_CASn, DDR3_RASn, DDR3_WEn, DDR3_CKE0, DDR3_ODT0 DQ1 DQS1 DDR3_D[15:8], DDR3_DQM1 DQ2(1) DQS2 DDR3_D[23:16], DDR3_DQM2 DQ3(1) DQS3 DDR3_D[31:24], DDR3_DQM3 (1) Only used on 32-bit wide DDR3L memory systems. 7.1.2.11 DDR3L Signal Termination Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in the routing rules in the following sections. 7.1.2.12 VREF_DDR Routing DDR3_VREFSSTL (VREF) is used as a reference by the input buffers of the DDR3L memories as well as the processor. VREF is intended to be half the DDR3L power supply voltage and is typically generated with the DVDD_DDR and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing congestion. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 211 ADVANCE INFORMATION 7.1.2.10 Net Classes 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 7.1.2.13 VTT Like VREF, the nominal value of the VTT supply is half the DDR3L supply voltage. Unlike VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors. 7.1.2.14 CK and ADDR_CTRL Topologies and Routing Definition The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3L configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailed in Table 7-11. 7.1.2.14.1 Four DDR3L Devices 7.1.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3L Devices Figure 7-6 shows the topology of the CK net classes and Figure 7-7 shows the topology for the corresponding ADDR_CTRL net classes. + – + – + – + – AS+ AS- AS+ AS- AS+ AS- DDR Differential CK Input Buffers AS+ AS- ADVANCE INFORMATION Four DDR3L devices are supported on the DDR EMIF consisting of four x8 DDR3L devices arranged as one bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB. Clock Parallel Terminator DVDD_DDR Rcp A1 Processor Differential Clock Output Buffer A2 A3 A4 A3 AT Cac + – Rcp A1 A2 A3 A4 A3 0.1 µF AT Routed as Differential Pair Figure 7-6. CK Topology for Four x8 DDR3L Devices 212 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Processor Address and Control Output Buffer A1 A3 A2 AS AS AS AS DDR Address and Control Input Buffers A3 A4 Address and Control Terminator Rtt VTT AT Figure 7-7. ADDR_CTRL Topology for Four x8 DDR3L Devices 7.1.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3L Devices ADVANCE INFORMATION A1 A1 Figure 7-8 shows the CK routing for four DDR3L devices placed on the same side of the PCB. Figure 7-9 shows the corresponding ADDR_CTRL routing. DVDD_DDR A3 A3 = A4 A4 A3 A3 Rcp Cac Rcp 0.1 µF AT AT AS+ AS- A2 A2 Figure 7-8. CK Routing for Four Single-Side DDR3L Devices Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 213 66AK2G02, 66AK2G01 www.ti.com A1 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Rtt A3 = A3 A4 AT VTT AS A2 ADVANCE INFORMATION Figure 7-9. ADDR_CTRL Routing for Four Single-Side DDR3L Devices A1 A1 To save PCB space, the four DDR3L memories may be mounted as two mirrored pairs at a cost of increased routing and assembly complexity. Figure 7-10 and Figure 7-11 show the routing for CK and ADDR_CTRL, respectively, for four DDR3L devices mirrored in a two-pair configuration. DVDD_DDR = A4 A4 A3 A3 Rcp Cac Rcp 0.1 µF AT AT AS+ AS- A3 A3 A2 A2 Figure 7-10. CK Routing for Four Mirrored DDR3L Devices 214 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 A1 www.ti.com Rtt A3 A3 AT VTT Figure 7-11. ADDR_CTRL Routing for Four Mirrored DDR3L Devices 7.1.2.14.2 One DDR3L Device A single DDR3L device is supported on the DDR EMIF consisting of one x16 DDR3L device arranged as one bank (CS), 16 bits wide. 7.1.2.14.2.1 CK and ADDR_CTRL Topologies, One DDR3L Device Figure 7-12 shows the topology of the CK net classes and Figure 7-13 shows the topology for the corresponding ADDR_CTRL net classes. DDR Differential CK Input Buffer AS+ AS- + – Clock Parallel Terminator DVDD_DDR Rcp A1 Processor Differential Clock Output Buffer A2 AT Cac + – Rcp A1 A2 0.1 µF AT Routed as Differential Pair Figure 7-12. CK Topology for One DDR3L Device Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 215 ADVANCE INFORMATION = A4 AS A2 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com AS DDR Address and Control Input Buffers Processor Address and Control Output Buffer A1 Address and Control Terminator Rtt AT VTT A2 Figure 7-13. ADDR_CTRL Topology for One DDR3L Device 7.1.2.14.2.2 CK and ADDR/CTRL Routing, One DDR3L Device Figure 7-14 shows the CK routing for one DDR3L device placed on the same side of the PCB. Figure 7-15 shows the corresponding ADDR_CTRL routing. A1 A1 ADVANCE INFORMATION DVDD_DDR Rcp Cac Rcp 0.1 µF AT AT = AS+ AS- A2 A2 Figure 7-14. CK Routing for One DDR3L Device 216 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 A1 www.ti.com Rtt AT Figure 7-15. ADDR_CTRL Routing for One DDR3L Device 7.1.2.15 Data Topologies and Routing Definition No matter the number of DDR3L devices used, the data line topology is always point to point, so its definition is simple. Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby ground vias to allow the return currents to transition between reference planes if both reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes if one of the reference planes is ground. The goal is to minimize the size of the return current loops. 7.1.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 7-16 and Figure 7-17 show these topologies. Processor DQS IO Buffer DQSn+ DQSn- DDR DQS IO Buffer Routed Differentially n = 0, 1, 2, 3 Figure 7-16. DQS Topology Processor DQ and DM IO Buffer Dn DDR DQ and DM IO Buffer n = 0, 1, 2, 3 Figure 7-17. DQ/DM Topology 7.1.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices Figure 7-18 and Figure 7-19 show the DQS and DQ/DM routing. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 217 ADVANCE INFORMATION = VTT AS A2 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com DQSn+ DQSn- DQS Routed Differentially n = 0, 1, 2, 3 Figure 7-18. DQS Routing With Any Number of Allowed DDR3L Devices ADVANCE INFORMATION Dn DQ and DM n = 0, 1, 2, 3 Figure 7-19. DQ/DM Routing With Any Number of Allowed DDR3L Devices 7.1.2.16 Routing Specification 7.1.2.16.1 CK and ADDR_CTRL Routing Specification Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance. Given the clock and address pin locations on the processor and the DDR3L memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-20 and Figure 7-21 show this distance for four loads and two loads, respectively. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 7-11. 218 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 (A) A1 A8 A8 (A) A8 (A) A8 (A) A8 (A) Rtt A3 AT VTT ADVANCE INFORMATION = A3 A4 AS A2 Figure 7-20. Four Address Loads on One Side of PCB (A) A1 A8 A8 (A) A8 (A) Rtt A3 = AT VTT AS A2 Figure 7-21. Two Address Loads on One Side of PCB Table 7-11. CK and ADDR_CTRL Routing Specification(2)(3) NO. PARAMETER CARS31 A1+A2 length CARS32 A1+A2 skew CARS33 A3 length CARS34 MIN TYP MAX UNIT 500(1) ps 29 ps 125 ps A3 skew(4) 6 ps CARS35 A3 skew(5) 6 ps CARS36 A4 length 125 ps CARS37 A4 skew 6 ps CARS38 AS length 5(1) 17 ps (1) 14 ps CARS39 AS skew 1.3 Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 219 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 7-11. CK and ADDR_CTRL Routing Specification(2)(3) (continued) NO. PARAMETER MIN TYP MAX 5 12 UNIT ps 1 ps CARS310 AS+/AS- length CARS311 AS+/AS- skew CARS312 AT length(6) 75 ps CARS313 AT skew(7) 14 ps CARS314 (8) AT skew CARS315 CK/ADDR_CTRL trace length CARS316 Vias per trace CARS317 Via count difference 1 1020 (9) CARS318 Center-to-center CK to other DDR3L trace spacing CARS319 Center-to-center ADDR_CTRL to other DDR3L trace spacing(9)(10) 4w CARS320 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(9) 3w CARS321 CK center-to-center spacing CARS322 ps ps 3(1) vias 1(15) vias 4w (11)(12) (9) CK spacing to other net 4w (13) ADVANCE INFORMATION CARS323 Rcp Zo-1 Zo Zo+1 Ω CARS324 Rtt(13)(14) Zo-5 Zo Zo+5 Ω (1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation. (2) The use of vias should be minimized. (3) Additional bypass capacitors are required when using the DVDD_DDR plane as the reference plane to allow the return current to jump between the DVDD_DDR plane and the ground plane when the net class switches layers at a via. (4) Non-mirrored configuration (all DDR3L memories on same side of PCB). (5) Mirrored configuration (one DDR3L device on top of the board and one DDR3L device on the bottom). (6) While this length can be increased for convenience, its length should be minimized. (7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required. (8) CK net class only. (9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length. (10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3L trace spacing. (11) CK spacing set to ensure proper differential impedance. (12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo. (13) Source termination (series resistor at driver) is specifically not allowed. (14) Termination values should be uniform across the net class. (15) Via count difference may increase by 1 only if accurate 3D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded. 7.1.2.16.2 DQS and DQ Routing Specification Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL, a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1. Given the DQS and DQ/DM pin locations on the processor and the DDR3L memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-22 shows this distance for four loads. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 7-12. 220 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 DQ[0:7]/DM0/DQS0 DB0 DB1 DB2 DB3 DQ[8:15]/DM1/DQS1 DQ[16:23]/DM2/DQS2 DQ[24:31]/DM3/DQS3 3 2 1 0 DB0 - DB3 represent data bytes 0 - 3. ADVANCE INFORMATION Figure 7-22. Any Number of Allowed DDR3L Devices Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 221 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table 7-12. Data Routing Specification(2)(11) MAX UNIT DRS31 NO. DB0 length 340 ps DRS32 DB1 length 340 ps DRS33 DB2 length 340 ps DRS34 DB3 length 340 ps DRS35 DBn skew(3) 5 ps DRS36 DQSn+ to DQSn- skew 1 ps DRS37 (3)(4) DQSn to DBn skew 5 DRS38 Vias per trace 2(1) vias DRS39 Via count difference 0(10) vias DRS310 DRS311 PARAMETER MIN Center-to-center DBn to other DDR3L trace spacing Center-to-center DBn to other DBn trace spacing (6) (7) TYP (10) ps 4 w(5) 3 w(5) 4 w(5) (8) (9) DRS312 DQSn center-to-center spacing DRS313 DQSn center-to-center spacing to other net ADVANCE INFORMATION (1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation. (2) External termination disallowed. Data termination should use built-in ODT functionality. (3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended. (4) Each DQS pair is length matched to its associated byte. (5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length. (6) Other DDR3L trace spacing means other DDR3L net classes not within the byte. (7) This applies to spacing within the net classes of a byte. (8) DQS pair spacing is set to ensure proper differential impedance. (9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo. (10) Via count difference may increase by 1 only if accurate 3D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded. (11) It is not required to match lengths across all bytes. Length matching is only required within the data bits of a given byte. 7.2 High Speed Differential Signal Routing Guidance The High-Speed Interface Layout Guidelines Application Report (SPRAAR7) available from http://www.ti.com/lit/pdf/spraar7 provides guidance for successful routing of the high speed differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing limits. TI supports only designs that follow the board design guidelines contained in the application report. 7.3 Power Distribution Network Implementation Guidance The Power Delivery Network Analysis Application Report (SPRAC38) available from http://www.ti.com/lit/pdf/sprac38 provides guidance for successful implementation of the power distribution network. This includes PCB stackup guidance as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that follow the board design guidelines contained in the application report. 222 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 7.4 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Single-Ended Interfaces 7.4.1 General Routing Guidelines The following paragraphs detail the routing guidelines that must be observed when routing the various functional LVCMOS interfaces. • Line spacing: – For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the crosstalk between switching signals between the different lines. On the PCB, this is not achievable everywhere (for example, when breaking signals out from the device package), but it is recommended to follow this rule as much as possible. When violating this guideline, minimize the length of the traces running parallel to each other (see Figure 7-23). D+ S = 2 W = 200 µm • • • 7.5 7.5.1 SWPS040-185 Figure 7-23. Ground Guard Illustration Length matching (unless otherwise specified): – For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 25 mm. – For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 2.5 mm. Characteristic impedance – Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35-Ω and 65-Ω. Multiple peripheral support – For interfaces where multiple peripherals have to be supported in the star topology, the length of each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify signal integrity based on simulations including actual PCB extraction. Clock Routing Guidelines Oscillator Routing When designing the printed-circuit board: • Place the crystal circuit on the same side of the PCB as the 66AK2G0x device and as close as possible to the respective device pins SYSOSC_IN / SYSOSC_OUT, or AUDOSC_IN / AUDOSC_OUT. • The crystal circuit traces should be placed on the outer layer of the PCB when possible, with the lengths being as short as possible to reduce parasitic capacitance and minimize crosstalk from other signals. • Do not route any other signals under the crystal circuit traces if there is an adjacent signal layer on the PCB. • Route all crystal circuit component ground connections to one common ground via. This via must directly connect to the ground plane. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 223 ADVANCE INFORMATION W 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 • www.ti.com Treat VSS_OSC_AUDIO and VSS_OSC_SYS pins the same way as other device VSS pins: connect them to board ground as near to the ball as possible. Device Cap Crystal Cap SYSOSC_IN / AUDOSC_IN SYSOSC_OUT / AUDOSC_OUT Via to GND SWPS040-196 ADVANCE INFORMATION Figure 7-24. SYSOSC and AUDOSC PCB requirements 7.5.2 Oscillator Ground Connection Device SYSOSC_IN / AUDOSC_IN SYSOSC_OUT / AUDOSC_OUT VSS_OSC_SYS / VSS_OSC_AUDIO Rd (Optional) Crystal Cf2 Cf1 SPRS85v_PCB_CLK_OSC_2 Figure 7-25. Grounding Scheme for internal oscillators 224 Applications, Implementation, and Layout Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 8 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 8.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, 66AK2G02). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZBB), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, 60 is 600 MHz). Figure 8-1 provides a legend for reading the complete device name for any 66AK2G0x device. For orderable part numbers of 66AK2G0x devices in the ZBB package type, see the Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the Silicon Errata (SPRZ435). Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Device and Documentation Support 225 ADVANCE INFORMATION Device development evolutionary flow: 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 a www.ti.com BBBBBBbb r PPP T Zzz C Y SECURITY IDENTIFIER Blank = General purpose device (TMS) D = HS device with TI developmental keys S = HS device with production keys DEVICE EVOLUTION STAGE X = Prototype (TMX) P = Preproduction (TMP - production test flow, no reliability data) BLANK = Production (TMS) IP SUPPORT DESIGNATOR E = Ethercat OTHER = Alternate IP support BASE PRODUCTION PART NUMBER 66AK2G0x = DSP + ARM KeyStone II G SoC DEVICE SPEED 60 = Nominal speed grade (see Speed Grade Maximum Frequency) OTHER = Alternate speed grade SILICON REVISION Blank = Revision 1.0 (1) TEMPERATURE Blank = Commercial (see Recommended Operating Conditions) Q = Automotive (see Recommended Operating Conditions) A = Extended (see Recommended Operating Conditions) PACKAGE DESIGNATOR ZBB = NFBGA-N625 Package (see Mechanical Packaging and Orderable Information) Figure 8-1. Device Nomenclature ADVANCE INFORMATION (1) Applies to device max junction temperature. 8.2 Tools and Software The following products support development for 66AK2G platforms: Development Tools 66AK2G Clock Tree Tool is an interactive clock tree configuration software that allows the user to visualize the device clock tree, interact with clock tree elements and view the effect on PRCM registers, interact with the PRCM registers and view the effect on the device clock tree, and view a trace of all the device registers affected by the user interaction with the clock tree. 66AK2G Pin Mux Utility is an interactive application that helps a system designer select the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pinmultiplexing configuration selected for a design only uses valid IO Sets supported by the device. 8.3 Documentation Support The following documents describe the 66AK2G devices: TRM 66AK2G0x, 66AK2G1x DSP+ARM KeyStone II System-on-Chip (SoC) Technical Reference Manual Details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the 66AK2G family of devices. Errata 66AK2G0x Silicon Errata Describes known advisories, limitations, and cautions on silicon and provides workarounds. 8.4 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1. Related Links 226 PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY 66AK2G02 Click here Click here Click here Click here Click here 66AK2G01 Click here Click here Click here Click here Click here Device and Documentation Support Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 www.ti.com 8.5 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 Receiving Notification of Documentation Updates To receive notification of documentation updates — including silicon errata — go to the product folder for your device on ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. 8.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Trademarks NEON, CoreSight are trademarks of ARM Limited. ARM, Cortex are registered trademarks of ARM Limited. EtherCAT is a trademark of Beckhoff Automation GmbH. QSPI is a trademark of Cadence Design Systems, Inc. MediaLB is a registered trademark of Microchip Technology Inc. MIPI is a registered trademark of Mobile Industry Processor Interface (MIPI) Alliance. PCI Express, PCIe are registered trademarks of PCI-SIG. PROFIBUS is a registered trademark of PROFIBUS and PROFINET International. All other trademarks are the property of their respective owners. 8.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.9 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Device and Documentation Support 227 ADVANCE INFORMATION 8.7 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 9 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. ADVANCE INFORMATION 228 Mechanical Packaging and Orderable Information Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 66AK2G02, 66AK2G01 SPRS932E – DECEMBER 2015 – REVISED JUNE 2017 ADVANCE INFORMATION www.ti.com Figure 9-1. Mechanical Package Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Links: 66AK2G02 66AK2G01 Copyright © 2015–2017, Texas Instruments Incorporated 229 PACKAGE OPTION ADDENDUM www.ti.com 17-Jan-2018 PACKAGING INFORMATION Orderable Device Status (1) X66AK2G02ZBB60 ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZBB 625 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD Call TI Call TI Op Temp (°C) Device Marking (4/5) 0 to 90 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of