Application Report
SCPU027C - June 2007
XIO2000A Implementation Guide
Interface Business Unit
ABSTRACT
This document is provided to assist platform designers using the XIO2000A PCI Express to
PCI Translation Bridge. Detailed information can be found in the XIO2000A Data Manual.
However, this document provides board design suggestions for the various device features
when designing in the XIO2000A.
Contents
1
XIO2000A Typical System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 1.5-V and 3.3-V Digital Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 1.5-V and 3.3-V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 VCCP Clamping Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Combined Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Auxiliary Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 VSS and VSSA Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Capacitor Selection Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Power Supply Filtering Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
PCI Express Interface Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 2.5-Gb/s Transmit and Receive Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 PCI Express Transmitter Reference Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 PCI-Express Reference Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 PCI Express Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 PCI Express Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
PCI Bus Interface Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Miscellaneous Terminal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 GPIO Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 GRST Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Reserved Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Interrupt Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Serial EEPROM Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 BIOS Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Classic PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
4
4
4
5
5
5
5
6
15
15
15
16
17
17
18
19
Trademarks are the property of their respective owners.
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8
Power Management Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 D3/L2 Power Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Active State Power Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 PCI Bus Power Override Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 CLKRUN Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 PCI Bus Clock Power and EMI Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
21
21
22
9
Reference Schematics GZZ/ZZZ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Reference Schematics ZHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Typical System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External PCI Bus Clock Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Arbiter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Tables
Table 1. Interrupt Bindings for Option Cards Using PCI-to-PCI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . 17
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1
XIO2000A Typical System Implementation
Figure 1 represents a typical implementation of the XIO2000A PCI Express to PCI translation
bridge. The device serves as a bridge between an upstream PCI Express device and up to six
downstream PCI bus devices. The XIO2000A operates only with the PCI Express interface as
the primary bus and the PCI bus interface as the secondary bus. The PCI bus interface is 32 bits
wide and operates at either 33 MHz or 66 MHz.
Figure 1. Typical System Integration
PCI Express
reference
clock
Upstream PCI
Express
device
PCI Express link
Auxiliary
power
(VAUX)
System-side
XIO2000A-side
Serial
EEPROM
GPIO
interface
XIO2000A
Miscellaneous
PCI bus functions
CLK_RUN, PWR_OVRD,
LOCK, M66EN, PME,
SERIRQ, and
EXTERNAL ARBITER
PCI bus
Either a common differential 100-MHz PCI Express reference clock or an asynchronous
single-ended 125-MHz reference clock is supported. Figure 1 illustrates the common 100-MHz
reference clock option.
If VAUX power states are a system requirement, the XIO2000A maintains system configuration
information in “sticky” register bits.
The EEPROM can set various configuration registers but is not necessary if those registers are
settable via software/BIOS for the system.
The serial IRQ bus passes ISA-style legacy interrupts upstream to the system host controller.
Some PCI devices require ISA-style legacy interrupts to function properly. The XIO2000A
converts serial bus IRQs into PCI Express upstream MSI messages.
Up to eight general-purpose inputs/outputs (GPIOs) exist for further system customization.
Options exist for the clock run, LOCK, PME, M66 enable, external arbiter, and power override
features, if any of the PCI bus devices require these features.
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2
Power Considerations
2.1
1.5-V and 3.3-V Digital Supplies
The XIO2000A requires both 1.5-V and 3.3-V digital power.
The 1.5-V terminals are named VDD_15. These terminals supply power to the digital core. The
1.5-V core allows for a significant reduction in both power consumption and logic switching
noise.
The 3.3-V terminals are named VDD_33 and supply power to most of the input and output cells.
Both the VDD_15 and VDD_33 supplies must have 0.1-µF bypass capacitors to VSS (ground) for
proper operation. The recommendation is one capacitor for each power terminal.
The via associated with the H14 terminal pad must connect to a 1000-pF bypass capacitor. The
other side of the capacitor must connect to VSS (ground) for proper operation. When placing and
connecting all bypass capacitors, high-speed board design rules must be followed.
2.2
1.5-V and 3.3-V Analog Supplies
Both 1.5-V and 3.3-V analog power is required by the XIO2000A. Because circuit noise on the
analog power terminals must be minimized, a Pi filter is recommended. All VDDA_15 terminals
must be connected together and share one Pi filter. All VDDA_33 terminals must be connected
together and share a second Pi filter.
Both the 1.5-V and 3.3-V analog supplies must have 0.1-µF bypass capacitors connected to
VSSA (ground) in order for proper operation. The recommendation is one capacitor for each
power terminal. In addition, one 1000-pF capacitor per Pi filter is recommended. This 1000-pF
capacitor is attached to the device side of the Pi filter and to VSSA (ground). High-speed board
design rules must be followed when connecting bypass capacitors to VDDA and VSSA.
2.3
VCCP Clamping Rail
The XIO2000A has a PCI bus I/O clamp rail (VCCP) which can be either 3.3 V or 5 V depending
on the system implementation. For 33-MHz PCI bus implementations, VCCP may be connected
to either 3.3 V or 5.0 V. For 66-MHz PCI bus implementations, a 3.3-V connection is the only approved configuration. The power source for this clamp rail is a standard digital supply. Other
than digital supply bypass capacitors, one 0.1-µF capacitor per terminal, no additional components are required.
If VCCP is attached to a 5.0-V supply, the XIO2000A will only output 3.3-V amplitude signals on
the PCI bus. The received PCI bus signal amplitudes may be either 3.3 V or 5.0 V. The PCI bus
I/O cells are 5.0-V tolerant and the XIO2000A device is not damaged by 5.0-V input signal amplitudes.
2.4
Combined Power Outputs
To support VAUX system requirements, the XIO2000A internally combines main power with VAUX
power. There are three combined power rails in the XIO2000A. These three power rails are
distributed to the analog circuits, digital logic, and I/O cells that must operate during the VAUX
state. Each of the three power rails has an output terminal for the external attachment of bypass
capacitors to minimize circuit switching noise. These terminals are named VDD_15_COMB,
VDD_33_COMB, and VDD_33_COMBIO.
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The recommended bypass capacitors for each combined output terminal are 1000 pF, 0.01 µF,
and 1.0 µF. When placing these capacitors on the bottom side of the circuit board, the smallest
capacitor is positioned next to the via associated with the combined output terminal and the
largest capacitor is the most distant from the via. The circuit board trace width connecting the
combined output terminal via to the capacitors must be at least 12 to 15 mils wide with the trace
length as short as possible.
Other than the three recommended capacitors, no external components or devices must be
attached to these combined output terminals.
2.5
Auxiliary Power
If VAUX power is available in the system, the XIO2000A has the VDD_33_AUX terminal to support
this feature. Without fully understanding a system’s VAUX power distribution design,
recommending external components for the XIO2000A is difficult. At a minimum, a 0.1−µF
bypass capacitor is placed near the XIO2000A and attached to the system’s VAUX power supply.
A robust design may include a Pi filter with bulk capacitors (5 µF to 100 µF) to minimize voltage
fluctuations. When the system is cycling main power or is in the VAUX state, the VDD_33_AUX
terminal requirements are that the input voltage cannot exceed 3.6 V or drop below 3.0 V for
proper operation of the bridge.
If VAUX power is not present within the system, this terminal is connected to VSS thru a resistor
with a value greater than 3.0 kΩ.
2.6
VSS and VSSA Terminals
For proper operation of the XIO2000A, we recommend a unified VSS and VSSA ground plane.
The circuit board stack-up recommendation is to implement a layer 2 ground plane directly
under the XIO2000A device. Both the circuit board vias and ground trace widths that connect the
VSS and VSSA ball pads to this ground plane must be oversized to provide a low impedance
connection.
2.7
Capacitor Selection Recommendations
When selecting bypass capacitors for the XIO2000A device, X7R-type capacitors are
recommended. The frequency versus impedance curves, quality, stability, and cost of these
capacitors make them a logical choice for most computer systems.
The selection of bulk capacitors with low-ESR specifications is recommended to minimize
low-frequency power supply noise. Today, the best low-ESR bulk capacitors are radial leaded
aluminum electrolytic capacitors. These capacitors typically have ESR specifications that are
less than 0.01 Ω at 100 kHz. Also, several manufacturers sell D size surface mount specialty
polymer solid aluminum electrolytic capacitors with ESR specifications slightly higher than
0.01 Ω at 100 kHz. Both of these bulk capacitor options significantly reduce low-frequency
power supply noise and ripple.
2.8
Power-Up/Down Sequencing
NOTE: The power sequencing recommendations in this section exclude the VDD_33_AUX
terminal.
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All XIO2000A analog and digital power terminals must be controlled during the power-up and
power-down sequence. Absolute maximum power terminal ratings must not be exceeded to
prevent damaging the device. All power terminals must remain within 3.6 V to prevent damaging
the XIO2000A.
2.9
Power Supply Filtering Recommendations
To meet the PCI-Express jitter specifications, low-noise power supplies are required on several
of the XIO2000A voltage terminals. The power terminals that require low-noise power include
VDDA_15 and VDDA_33. This section provides guidelines for the filter design to create low-noise
power sources.
The least expensive solution for low-noise power sources is to filter existing 3.3-V and 1.5-V
power supplies. This solution requires analysis of the noise frequencies present on the power
supplies. The XIO2000A has external interfaces operating at clock rates of 33 MHz, 66 MHz,
100 MHz, 125 MHz, and 2.5 GHz. Other devices near the XIO2000A may produce switching
noise at different frequencies. Also, the power supplies that generate the 3.3-V and 1.5-V power
rails may add low frequency ripple noise. Linear regulators have feedback loops that typically
operate in the 100-kHz range. Switching power supplies typically have operating frequencies in
the 500-kHz range. When analyzing power supply noise frequencies, the first, third, and fifth
harmonic of every clock source should be considered.
Critical analog circuits within the XIO2000A must be shielded from this power supply noise. The
fundamental requirement for a filter design is to reduce power supply noise to a peak-to-peak
amplitude of less than 25 millivolts. This maximum noise amplitude must apply to all frequencies
from 0 Hz to 12.5 GHz.
The following information should be considered when designing a power supply filter:
6
•
Ideally, the series resonance frequency for each filter component should be greater than the
fifth harmonic of the maximum clock frequency. With a maximum clock frequency of
1.25 GHz, the third harmonic is 3.75 GHz and the fifth harmonic is 6.25 GHz. Finding
inductors and capacitors with a series resonance frequency above 6.25 GHz is both difficult
and expensive. Components with a series resonance frequency in the 4- to 6-GHz range are
a good compromise.
•
The inductor(s) associated with the filter must have a dc resistance low enough to pass the
required current for the connected power terminals. The voltage drop across the inductor
must be low enough to meet the minus 10 percent voltage margin requirement associated
with each XIO2000A power terminal. Power supply output voltage variation must be
considered as well as voltage drops associated with any connector pins and circuit board
power distribution geometries.
•
The Q versus frequency curve associated with the inductor must be appropriate to reduce
power terminal noise to less than the maximum peak-to-peak amplitude requirement for the
XIO2000A. Recommending a specific inductor is difficult because every system design is
different; therefore, the noise frequencies and noise amplitudes are different. Many factors
will influence the inductor selection for the filter design. Power supplies must have adequate
input and output filtering. A sufficient number of bulk and bypass capacitors are required to
minimize switching noise. Assuming that board level power is properly filtered and minimal
low frequency noise is present, frequencies less than 10 MHz, an inductor with a Q greater
than 20 from approximately 10 MHz to 3 GHz should be adequate for most system
applications.
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•
The series component(s) in the filter may either be an inductor or a ferrite bead. Testing has
been performed on both component types. When measuring PCI-Express link jitter, the
inductor or ferrite bead solutions produce equal results. When measuring circuit board EMI,
the ferrite bead is a superior solution.
NOTE: The XIO2200A reference schematics include ferrite beads in the analog power supply
filters.
•
When designing filters associated with power distribution, the power supply is a lowimpedance source and the device power terminals are a low impedance load. The best filter
for this application is a T filter. Please see Figure 2 for a T filter circuit. Some system may
require this type of filter design if the power supplies or nearby components are exceptionally
noisy. This type of filter design is recommended if a significant amount of low frequency
noise, frequencies less than 10 MHz, is present in a system.
•
For most applications a Pi filter will be adequate. See Figure 2 for a Pi filter circuit. When
implementing a Pi filter, the two capacitors and the inductor must be next to each other on
the circuit board and must be connected together with wide low impedance traces. Capacitor
ground connections must be short and low impedance.
•
If a significant amount of high frequency noise, frequencies greater than 300 MHz, is present
in a system, creating an internal circuit board capacitor will help reduce this noise. This is
accomplished by locating power and ground planes next to each other in the circuit board
stack-up. A gap of 0.003 mils between the power and ground planes will significantly reduce
this high frequency noise.
•
Another option for filtering high−frequency logic noise is to create an internal board capacitor
using signal layer copper plates. When a component requires a low-noise power supply,
usually the Pi filter is located near the component. Directly under the Pi filter, a plate
capacitor may be created. In the circuit board stack-up, select a signal layer that is physically
next to a ground plane. Then, generate an internal 0.25 inch by 0.25 inch plate on that signal
layer. Assuming a 0.006-mil gap between the signal layer plate and the internal ground
plane, this generates a 12-pF capacitor. By connecting this plate capacitor to the trace
between the Pi filter and the component’s power terminals, an internal circuit board high
frequency bypass capacitor is created. This solution is extremely effective for switching
frequencies above 300 MHz.
Figure 2 illustrates two different filter designs that may be used with the XIO2000A to provide
low-noise power to critical power terminals.
Figure 2. Filter Design
Power supply side
Component side
T filter design
Component side
Power supply side
Pi filter design
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3
PCI Express Interface Considerations
The XIO2000A has an x1 PCI Express interface that is fully compliant to the PCI Express Base
Specification, Revision 1.0a. The remainder of this section describes implementation
considerations for the XIO2000A primary PCI Express interface.
3.1
2.5-Gb/s Transmit and Receive Links
The XIO2000A TX and RX terminals attach to the upstream PCI Express device over a 2.5-Gb/s
high-speed differential transmit and receive PCI Express x1 Link. The connection details are
provided in the following table.
XIO2000A Terminal Name
TXP (H17)
Upstream PCI Express
Device Terminal Name
RXP
TXN (H16)
RXN
RXP (E17)
TXP
RXN (E16)
TXN
Comments
XIO2000A transmit positive differential terminal connects to the
upstream device receive positive differential terminal.
XIO2000A transmit negative differential terminal connects to the
upstream device receive negative differential terminal.
XIO2000A receive positive differential terminal connects to the
upstream device transmit positive differential terminal.
XIO2000A receive negative differential terminal connects to the
upstream device transmit negative differential terminal.
The XIO2000A TXP and TXN terminals comprise a low-voltage, 100-Ω differentially driven
signal pair. The RXP and RXN terminals for the XIO2000A receive a low-voltage, 100-Ω
differentially driven signal pair. The XIO2000A has integrated 50-Ω termination resistors to VSS
on both the RXP and RXN terminals eliminating the need for external components.
Each lane of the differential signal pair must be ac-coupled. The recommended value for the
series capacitor is 0.1 µF. To minimize stray capacitance associated with the series capacitor
circuit board solder pads, 0402-sized capacitors are recommended.
When routing a 2.5-Gb/s low-voltage, 100-Ω differentially driven signal pair, the following circuit
board design guidelines must be considered:
1. The PCI-Express drivers and receivers are designed to operate with adequate bit error
rate margins over a 20-inch maximum length signal pair routed through FR4 circuit board
material.
2. Each differential signal pair must be 100-Ω differential impedance with each single-ended
lane measuring in the range of 50-Ω to 55-Ω impedance to ground.
3. The differential signal trace lengths associated with a PCI Express high-speed link must
be length-matched to minimize signal jitter. This length-matching requirement applies only
to the P and N signals within a differential pair. It is not necesary to lenght match the
transmitter differential to the receiver differential pair. The absolute maximum trace length
difference between the TXP signal and TXN signal must be less than 5 mils. This also
applies to the RXP and RXN signal pair.
4. If a differential signal pair is broken into segments by vias, series capacitors, or
connectors, the length of the positive signal trace must be length matched to the negative
signal trace for each segment. Trace length differences over all segments are additive and
must be less than 5 mils.
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3.2
•
The location of the series capacitors is critical. For add-in cards, the series capacitors are
located between the TXP/TXN terminals and the PCI-Express connector. In addition, the
capacitors are placed near the PCI Express connector. This translates to two capacitors on
the motherboard for the downstream link and two capacitors on the add-in card for the
upstream link. If both the upstream device and the downstream device reside on the same
circuit board, the capacitors are near the TXP/TXN terminals for each link.
•
The number of vias must be minimized. Each signal trace via reduces the maximum trace
length by approximately 2 inches. For example, if 6 vias are needed, the maximum trace
length is 8 inches.
•
When routing a differential signal pair, 45-degree angles are preferred over 90-degree
angles. Signal trace length matching is easier with 45-degree angles and overall signal trace
length is reduced.
•
The differential signal pairs must not be routed over gaps in the power planes or ground
planes. This causes impedance mismatches.
•
If vias are used to change from one signal layer to another signal layer, it is important to
maintain the same 50-Ω impedance reference to the ground plane. Changing reference
planes causes signal trace impedance mismatches. If changing reference planes cannot be
prevented, bypass capacitors connecting the two reference planes next to the signal trace
vias helps reduce the impedance mismatch.
•
If possible, the differential signal pairs must be routed on the top and bottom layers of a
circuit board. Signal propagation speeds are faster on external signal layers.
PCI Express Transmitter Reference Resistor
The REF0_PCIE (L16) and REF1_PCIE (L17) terminals connect to an external resistor to set
the drive current for the PCI Express TX driver. The recommended resistor value is 14,532 Ω
with 1 percent tolerance.
A 14,532-Ω resistor is a custom value. To eliminate the need for a custom resistor, two series
resistors are recommended: a 14,300-Ω, 1% resistor and a 232-Ω, 1% resistor. Trace lengths
must be kept short to minimize noise coupling into the reference resistor terminals.
3.3
PCI-Express Reference Clock Inputs
The XIO2000A requires an external reference clock for the PCI-Express interface. The PCI
Express Base Specification and PCI Express Card Electromechanical Specification provide
information concerning the requirements for this reference clock. The XIO2000A is designed to
meet all stated specifications when the reference clock input is within all PCI Express operating
parameters. This includes both standard clock oscillator sources or spread spectrum clock
oscillator sources.
The XIO2000A supports two options for the PCI Express reference clock: a 100-MHz common
differential reference clock or a 125-MHz asynchronous single-ended reference clock. Both
implementations are described in the following paragraphs.
The first option is a system-wide, 100-MHz differential reference clock. A single clock source
with multiple differential clock outputs is connected to all PCI Express devices in the system.
The differential connection between the clock source and each PCI Express device is
point-to-point. This system implementation is referred to as a common clock design.
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The XIO2000A is optimized for this type of system clock design. The REFCLK+ (C17) and
REFCLK− (C16) terminals provide differential reference clock inputs to the XIO2000A. The
circuit board routing rules associated with the 100-MHz differential reference clock are the same
as the 2.5-Gb/s TX and RX link routing rules itemized in Section 3.1. The only difference is that
the differential reference clock does not require series capacitors. The requirement is a dc
connection from the clock driver output to the XIO2000A receiver input. Electrical specifications
for these differential inputs are included in the XIO2000A Data Manual.
Terminating the differential clock signal is circuit board design specific. However, the XIO2000A
design has no internal 50-Ω-to-ground termination resistors. Both REFCLK inputs, at
approximately 20 kΩ to ground, are high-impedance inputs.
The second option is a 125-MHz asynchronous single-ended reference clock. In this case, the
devices at each end of the PCI Express link have different clock sources. The XIO2000A has a
125-MHz single-ended reference clock option for asynchronous clocking designs. When the
REFCLK_SEL input terminal (A16) is tied to VDD_33, this clocking mode is enabled.
The single-ended reference clock is attached to the REFCLK+ (C17) terminal. The REFCLK+
input, at approximately 20 kΩ, is a high−impedance input. Any clock termination design must
account for a high-impedance input. The REFCLK− (C16) terminal is attached to a 0.1−µF
capacitor. The capacitor’s second terminal is connected to VSSA. Electrical specifications for this
single-ended input are included in the XIO2000A Data Manual.
When using a single-ended reference clock, care must be taken to ensure interoperability from a
system jitter standpoint. The PCI Express Base Specification does not ensure interoperability
when using a differential reference clock commonly used in PC applications along with a
single-ended clock in a noncommon clock architecture. System jitter budgets must be verified to
ensure interoperability. See the PCI Express Jitter and BER White Paper from the PCI-SIG.
3.4
PCI Express Reset
The XIO2000A PCI Express reset (PERST) terminal (J17) connects to the upstream PCI
Express device’s PERST output. The J17 input cell has hysteresis and is operational during both
the main power state and VAUX power state. No external components are required.
See the XIO2000A Data Manual and the PCI-Express Card Electromechanical Specification to
fully understand the PERST electrical requirements and timing requirements associated with
power-up and power-down sequencing. Also, the Data Manual identifies all configuration and
memory-mapped register bits that are reset by PERST.
3.5
PCI Express Wake
WAKE is an open-drain output from the XIO2000A that is driven low to re-activate the PCI
Express link hierarchy’s main power rails and reference clocks. This PCI Express side-band
signal is connected to the WAKE input on the upstream PCI Express device. WAKE is
operational during both the main power state and VAUX power state.
Because WAKE is an open-drain output, a system side pullup resistor is required to prevent the
signal from floating. The drive capability of this open-drain output is 4 mA. Therefore, the value
of the selected pullup resistor must be large enough to assure a logic low signal level at the
receiver. A robust system design will select a pullup resistor value that de-rates the output driver
current capability by a minimum of 50%. At 3.3 V with a de-rated drive current equal to 2 mA, the
minimum resistor value is 1.65 kΩ. Larger resistor values are recommended to reduce the
current drain on the VAUX supply.
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4
PCI Bus Interface Considerations
The XIO2000A has a 32-bit PCI interface that can operate at either 33 MHz or 66 MHz. This
interface is compliant with the PCI Local Bus Specification, Revision 2.3. The remainder of this
section describes implementation considerations for the XIO2000A secondary PCI bus interface.
•
AD31:0, C/BE[3:0], PAR, DEVSEL, FRAME, STOP, TRDY, PERR, SERR, and IRDY are
required signals and must be connected to each PCI bus device. The maximum signal
loading specification for a 66-MHz bus is 30 pF and for a 33-MHz bus is 50 pF. All of these
signals are bused and synchronous to the PCI clock. All synchronous PCI bus signals must
be length matched to meet clock setup and hold requirements. PCI bus approved pullup
resistors connected to VCCP are needed on the following terminals: IRDY, TRDY, FRAME,
STOP, PERR, SERR, and DEVSEL.
•
The XIO2000A supports up to six external PCI bus devices with individual CLKOUT, REQ
and GNT signals. An internal PCI bus clock generator function provides six low-skew clock
outputs. Plus, there are six REQ inputs and six GNT outputs from the internal PCI bus
arbiter. Each PCI bus device connects to one CLKOUT signal, one REQ signal, and one
GNT signal. All three signals are point-to-point connections. The REQ and GNT signals are
synchronous and must be length matched to meet clock setup and hold requirements.
Unused CLKOUT signals can be disabled by asserting the appropriate CLOCK_DISABLE bit
in the clock control register at offset D8h. Unused REQ signals can be disabled using a weak
pullup resistor to VCCP. Unused GNT signals are no connects.
•
An external clock feedback feature is provided to de-skew PCI bus clocks. Connecting the
CLKOUT[6] terminal (B14) to the CLK terminal (P03) is required if any of the other six
CLKOUT[5:0] terminals are used to clock PCI bus devices. All connected CLKOUT[6:0]
signals must be length matched within 10 mils to minimize clock skew and satisfy PCI bus
setup and hold requirements for synchronous signals. The CLKOUT signals should be
slightly longer than the longest synchronous PCI bus signal trace. Figure 3 illustrates the
external PCI bus clock feedback feature. The use of series resistors on the 7 PCI bus clocks
should be considered to reduce circuit board EMI.
NOTE: There is one exception to this length-matching rule associated with connecting a
CLKOUT signal to PCI socket: For this case, the CLKOUT signal connected to a PCI socket
should be 2.5 inches shorter than the other CLKOUT signals.
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Figure 3. External PCI Bus Clock Feedback
VCCP
XIO2000A
M66EN
(R01)
Pullup
selects 66 MHz
PCI bus clock
Outputs
disabled
CLK (P03)
CLKOUT6
(B14)
CLKOUT5:1
Equal length
to minimize
clock skew
CLKOUT0
(C08)
CLK_IN
PCI bus
PCI bus device
Longest synchronous
bus signal trace
slightly shorter than
clock traces
12
•
The M66EN terminal (R01) determines the operating frequency for the secondary PCI bus.
When PERST is deasserted and if a pullup resistor to VCCP is detected on terminal R01, the
XIO2000A CLKOUT terminals operate at 66 MHz. A pulldown resistor to VSS switches the
CLKOUT terminals to 33-MHz operation. If the PCI bus is desired to run at 66 MHz, but
there may be 33-MHz add-in cards connected to the bus, the M66EN terminal is connected
to VCCP through a 5-kΩ resistor and bused to all PCI bus slots which may require the lower
speed clock. For this system configuration, add-in cards are required to short the M33EN
signal to ground if they only operate at 33-MHz.
•
IDSEL for each PCI bus device must be resistively coupled (100 Ω) to one of the address
lines between AD31 and AD16. See the XIO2000A Data Manual for the configuration
register transaction device number to AD bit translation chart.
•
PCI interrupts can be routed to the INT[D:A] inputs on the XIO2000A. These four inputs are
asynchronous to the PCI bus clock and detect state changes even if the PCI bus clock is
stopped. For each INT[D:A] input, an approved PCI bus pullup resistor to VCCP is required to
keep each interrupt signal from floating.
•
PRST is a required PCI bus signal and must be connected to all devices. This output signal
is asynchronous to the PCI bus clock. Because the output driver is always enabled and
either driving high or low, no pullup resistor is needed.
•
LOCK is an optional PCI bus signal. If LOCK is present in a system, it is connected to each
PCI bus device that supports the feature and must meet PCI bus loading requirements for
the selected clock frequency. An approved PCI bus pullup resistor to VCCP is required to
keep this signal from floating. LOCK is a bused signal and synchronous to the PCI bus clock.
All synchronous PCI bus signals must be length matched to meet clock setup and hold
requirements.
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•
SERIRQ is an optional PCI bus signal. When PERST is deasserted, if a pullup resistor to
VCCP is detected on terminal T04, the serial IRQ interface is enabled. A pulldown resistor to
VSS disables this feature. If SERIRQ is present in a system, it is connected to each PCI bus
device that supports the feature and must meet PCI bus loading requirements for the
selected clock frequency. An approved PCI bus pullup resistor to VCCP is required to keep
this signal from floating. SERIRQ is a bused signal and synchronous to the PCI bus clock. All
synchronous PCI bus signals must be length matched to meet clock setup and hold
requirements.
•
CLKRUN is an optional PCI bus signal that is shared with the GPIO0 terminal (T05). When
PERST is de-asserted and if a pullup resistor to VDD_33 is detected on terminal B15
(CLKRUN_EN), the clock run feature is enabled. A no connect on the B15 terminal disables
the CLKRUN feature. If CLKRUN is required in a system, this terminal is connected to each
PCI bus device and must meet PCI bus loading requirements for the selected clock
frequency. An approved PCI bus pullup resistor to VDD_33 is required per the PCI Mobile
Design Guide. CLKRUN is a bused signal and synchronous to the PCI bus clock. All
synchronous PCI bus signals must be length matched to meet clock setup and hold
requirements.
•
PWR_OVRD is an optional PCI bus signal that is shared with the GPIO1 terminal (U05). In
PWR_OVRD mode, this terminal is always an output and is asynchronous to the PCI bus
clock. When the power override control bits in the general control register at offset D4h are
set to 001b or 011b, the U05 terminal operates as the PWR_OVRD signal. Prior to setting
the power override control bits, the GPIO1 // PWR_OVRD terminal defaults to a standard
GPIO terminal.
•
PME is an optional PCI bus input terminal to detect power management events from
downstream devices. The PME terminal (M15) is operational during both main power states
and VAUX states. The PME receiver has hysteresis and expects an asynchronous input
signal. The board design requirements associated with this PME terminal are the same
whether or not the terminal is connected to a downstream device. If the system includes a
VAUX supply, the PME terminal requires a weak pullup resistor connected to VAUX to keep
the terminal from floating. If no VAUX supply is present, the pullup resistor is connected to
VDD_33.
•
The bridge supports external PCI bus clock sources. If an external clock is a system
requirement, the external clock source is connected to the CLK terminal (P03). The trace
length relationship between the synchronous bus signals and the external clock signals that
is previously described is still required to meet PCI bus setup and hold. For external clock
mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control register at
offset D8h. Plus, the XIO2000A clock run feature must be disabled with external PCI bus
clocks because there is no method of turning off external clocks.
•
The XIO2000A supports an external PCI bus arbiter. When PERST is deasserted, the logic
state of the EXT_ARB_EN terminal (A15) is checked. If an external arbiter is required,
terminal A15 is connected to VDD_33. When connecting the XIO2000A to an external arbiter,
the bus REQ signal to the external arbiter is the bridge’s GNT0 output terminal (A08).
Likewise, the bus GNT signal from the external arbiter is connected to the bridge’s REQ0
input terminal (B08). When in external arbiter mode, all internal XIO2000A port arbitration
features are disabled. Figure 4 illustrates the connectivity of an external arbiter.
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Figure 4. External Arbiter Connections
VCCP
VDD_33
XIO2000A
EXT_ARB_EN
(A15)
REQ [5:1]
External
arbiter
GNT 0
REQ 0
REQ 0
GNT 0
GNT 1
REQ 1
GNT
PCI bus
4.1
REQ
PCI bus device
Bus Parking
Because of the shared bus nature of PCI, if the bus is idle at any given time, some device on the
bus must drive floating signals to stable states. These signals are the address/data lines, the
command/byte enables, and a valid parity. If no devices are requesting use of the bus, it is the
responsibility of the arbiter to assign ownership of the bus so that the bus signals are never
floating while in idle states.
If the XIO2000A internal arbiter is enabled then there are two modes supported for bus parking.
The default mode for bus parking is for the arbiter to continue to assert GNT for the last bus
master. In this mode when all devices have deasserted their REQ signals, the arbiter will
continue to assert the GNT for the last bus master and that device is required to drive a stable
pattern onto the required signals. This will continue until another device requests use of the bus
resulting in the arbiter removing GNT from the current bus owner and granting it to the new
requestor.
Alternatively, the XIO2000A can be configured to self-park. In this mode any time no devices
have their REQ asserted, the XIO2000A removes GNT from the current bus owner and drives a
stable pattern onto the required lines.
It is suggested that implementations use the default mode of bus parking. The PCI Specification
recommends leaving the current GNT signal asserted if no devices are asserting REQ. Some
PCI bus masters release their REQ signals after having begun a transaction, even if that
transaction requires the use of the bus for an extended time. If the XIO2000A self-parks the
bus, then these bus masters have their transaction lengths limited to the latency timer setting.
This may result in increased arbitration for the bus, higher overhead for transactions, and
decreased bus performance.
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5
Miscellaneous Terminal Considerations
5.1
GPIO Terminals
There are eight General Purpose Input/Output (GPIO) terminals in the XIO2000A. All eight GPIO
terminals are 3.3 V tolerant. Four of the GPIO terminals are shared with other miscellaneous
functions. The remaining four terminals are always general purpose inputs or outputs.
One Classic PCI configuration register defines the GPIO terminal direction as either an input or
an output. A second register either defines the GPIO output state or reports the GPIO input
state. The power-up default is GPIO input mode. The power-up default signal level for each
GPIO terminal is determined by either an internal active pullup transistor or any externally
attached components. Internal active pullup transistors are present on GPIO terminals 0, 1, 2, 3,
4, 6, and 7. When a GPIO terminal is configured as an input, the internal active pullup transistor
is enabled. If a GPIO terminal is configured as an output, the internal active pullup transistor is
disabled.
The following list of GPIO terminals have special requirements that must be considered when
interfacing to the GPIO terminals:
5.2
•
GPIO0: If CLK_RUN mode is selected, this terminal (T05) requires a pullup resistor to
VDD_33 per the PCI Mobile Design Guide. Otherwise, this terminal operates as a standard
GPIO bit.
•
GPIO1: If the power override control bits in the general control register are set to 001b or
011b, this terminal is the PCI bus PWR_OVRD output. Otherwise, this terminal operates as
a standard GPIO bit.
•
GPIO2: This terminal must be a logic one at the de-assertion of PERST to enable PCI
Express 1.0a compatibility mode. After the de-assertion of PERST, this terminal operates as
a standard GPIO bit.
•
GPIO4//SCL and GPIO5//SDA: These terminals share the SCL and SDA signals for the
external EEPROM. If the GPIO5//SDA terminal is a 1b at the de−assertion of PERST, the
serial EEPROM interface is enabled. A 0b disables the serial EEPROM interface. If the serial
EEPROM interface is enabled, external pullup resistors to VDD_33 are required on both
terminals per the serial EEPROM specification. Otherwise, these terminals operate as
standard GPIO bits.
•
GPIO3, GPIO6, and GPIO7: These terminals always operate as standard GPIO bits.
GRST Terminal
GRST is a global reset terminal that is provided for custom reset requirements. When this input
is asserted low, all registers, state machines, digital logic, and analog circuits are returned to
their power−up default state. This reset is asynchronous to all external reference clock and
internal clock domains. The GRST input buffer has hysteresis and an internal active pullup
resistor. This input is powered either by main power or by VAUX power. Therefore, global resets
may be initiated during either power state.
During an XIO2000A device power-up from the D3cold power state, there is no requirement to
assert this terminal low. An internal power-up reset function performs an equivalent reset to
GRST. Because this input is powered during VAUX states, it is imperative that any external
circuits connected to GRST do not erroneously drive this input low when main power is lost. This
results in the reset of sticky control bits and power management state-machines.
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If the system designer has no need for a custom reset, the GRST terminal can simply be left
floating. An internal active pullup resistor will guarantee a non-reset state.
5.3
Reserved Terminals
The XIO2000A has multiple reserved input and output terminals. The recommendation for all
output terminals is a no connect state. Do not connect these output terminals to other signals or
external components. Doing so may increase power consumption or cause output driver signal
conflicts.
The input terminals must be connected to either VDD_33 or VSS. The reserved terminal table in
the XIO2000A Data Manual provides the connection requirements. The connection may either
be a direct short to the recommended supply/ground plane or through a pullup/down resistor.
Leakage currents associated with each input must be considered when selecting the resistor
option. The minimum leakage current is +/− 1 µA and the maximum is +/− 100 µA. Because the
leakage current varies from input to input, the safest resistor option is to assume +/− 100 µA.
6
Interrupt Configurations
The XIO2000A provides system designers with two options when configuring interrupts.
Standard parallel PCI bus interrupts may be connected to XIO2000A terminals INTA, INTB,
INTC, and INTD. When a PCI bus device asserts or de-asserts one of these inputs, the
XIO2000A asynchronously detects the state change and generates upstream PCI Express
interrupt messages. This interrupt conversion logic is always enabled and operates even when
PCI bus clocks are stopped. The PCI Express interface must be link trained and in the L0 Link
Active State for interrupt messages to be sent upstream. The XIO2000A Data Manual illustrates
the PCI Express message format for assert and deassert INTx messages.
Interrupts can also be signaled through the serial IRQ interface (terminal T04, SERIRQ). The
SERIRQ interface detects ISA style IRQ interrupts associated with bus frame IRQ0 to IRQ15.
These interrupts are necessary for some 16-bit PC Cards to function properly. Both edge mode
and level mode serial IRQ interrupts are supported. When a serial IRQ interrupt is detected and
the XIO2000A is properly configured, an MSI message is generated and sent upstream on the
PCI Express interface. The XIO2000A Data Manual includes a section that includes additional
detail associated with the serial IRQ and MSI message functionality.
When the XIO2000A is used in an option card, an interrupt binding is required by the PCI-to-PCI
Bridge Architecture Specification, Revision 1.0. This binding is between the PCI bus device
number (as given in the Type 1 configuration address and, therefore, the IDSEL line) and the
INTx# line it uses when requesting an interrupt.
The PCI bus connector has only four interrupt lines assigned to it: INTA, INTB, INTC, and INTD.
Multiple PCI bus devices might have to share these four interrupts. The XIO2000A fully supports
the conversion of all four PCI bus INTx lines to upstream PCI-Express assert and deassert INTx
messages. But, the XIO2000A only supports 16 IDSEL lines. Therefore, only device numbers 0
to 15 are listed in the Table 1 binding table.
Because only the BIOS knows how the PCI INTx# lines are routed, a mechanism is required to
inform the device driver which IRQ its device will request an interrupt on. The interrupt line
register in each PCI bus device stores this information. Behind a PCI-to-PCI bridge, the BIOS
code assumes the binding is as listed and writes the IRQ number into each device. The interrupt
binding defined in Table 1 is mandatory for option cards using PCI-to-PCI bridges.
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Table 1. Interrupt Bindings for Option Cards Using PCI-to-PCI Bridges
7
Device Number on Secondary Bus
Interrupt Pin on PCI
Bus Device/Connector
Interrupt Pin on
XIO2000A
0, 4, 8, 12
INTA#
INTB#
INTC#
INTD#
INTA#
INTB#
INTC#
INTD#
1, 5, 9, 13
INTA#
INTB#
INTC#
INTD#
INTB#
INTC#
INTD#
INTA#
2, 6, 10, 14
INTA#
INTB#
INTC#
INTD#
INTC#
INTD#
INTA#
INTB#
3, 7, 11, 15
INTA#
INTB#
INTC#
INTD#
INTD#
INTA#
INTB#
INTC#
Software Considerations
The XIO2000A PCI Express to PCI translation bridge is natively supported by either BIOS
software and/or operating system software that recognizes the classic PCI-to-PCI bridge
programming model. XIO2000A classic PCI configuration register space uses a type 1 PCI
bridge header. All other XIO2000A advanced features default to a disabled state and do not
require configuration register initialization for basic operation.
However, to fully use advanced features within the XIO2000A, custom device drivers are
required. The best example of an advanced feature is the PCI Express Extended Virtual
Channel Configuration Register space. Software for this feature is not presently supported by
either today’s operating systems or by Texas Instruments. Designers should plan to develop
custom device drivers if this advanced feature is required in a system.
7.1
Serial EEPROM Interface Configuration
An external serial EEPROM port is provided on the XIO2000A for power-up configuration
support. Typically, the system BIOS initializes the configuration registers associated with the
serial EEPROM feature. But for custom systems or PCI-Express add-in cards, this feature is
provided to automate basic XIO2000A configuration register initialization.
The registers loaded by the serial EEPROM feature are located in the classic PCI configuration
space. The names of these registers include the subsystem ID and subsystem vendor ID,
general control, clock control and mask, arbiter control and mask, and serial IRQ control
registers.
NOTE: The serial EEPROM also loads TI proprietary registers. The data loaded into these
12 bytes must not be changed from the values specified in the EEPROM register loading map.
Otherwise, the operational state of the bridge is indeterminate.
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Terminal T07, named GPIO5 // SDA, provides a basic EEPROM enable or disable option. When
PERST is deasserted, the logic state of this terminal is checked. If a 1b is detected, the serial
EEPROM interface is enabled. A 0b disables the interface. An external pullup or pulldown
resistor is required to generate the appropriate logic state.
Immediately after the detection of a 1b on terminal T07, the XIO2000A performs the following
actions:
1. Bit 3 (SBDETECT) in the serial-bus control and status register is set.
2. Bit 4 (ROMBUSY) in the serial-bus control and status register is set and a serial EEPROM
download is initiated to device address 1010000b and word address 00h.
3. The EEPROM data byte in word address 00h is checked. If bit 7 is asserted, this indicates
an End-of-List Indicator and the serial-bus state-machine aborts the download. A 00h
value indicates a valid PCI Express-to-PCI Bus Bridge function header. EEPROM word
address 00h must only be loaded with either 00h, 80h or FFh. Other byte values must not
be used because they may cause configuration register download errors and leave the
XIO2000A in an indeterminate state.
4. After a valid function header is detected, the EEPROM data byte in word address 01h is
read. This location determines the number of bytes that are downloaded into the bridge
configuration registers and must equal 1Eh.
5. The starting EEPROM word address is 02h and the ending address is 1Fh. While
downloading the 1Eh data bytes, each byte is loaded into the specified bridge
configuration register. The XIO2000A Data Manual includes an EEPROM register loading
map.
6. The last data byte at word address 20h is checked for a valid end−of−list indicator byte.
This data byte must equal 80h.
7. When the serial EEPROM interface state machine is finished, the ROMBUSY status bit is
deasserted. If any errors are detected during the download procedure, bit 0 (ROM_ERR)
in the serial-bus control and status register is set. If ROM_ERR status is asserted, the
state of any configuration register targeted by the EEPROM download is unknown.
Additional detail is provided in the XIO2000A Data Manual related to the serial EEPROM
function and configuration register download map.
7.2
BIOS Considerations
This section provides a high-level overview of the registers which must programmed by the
BIOS upon initialization of the XIO2000A. In general, the only registers which must be
programmed for proper operation within a Windows operating system are those registers which
are EEPROM loadable. Other registers may must changed according to system implementation.
Microsoft provides the following reference documents concerning architecture and driver support
for PCI and PCI Express devices in Windows:
http://www.microsoft.com/whdc/system/bus/pci/default.mspx
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7.2.1
Classic PCI Configuration Registers
Primary Bus Number Register (PCI offset 18h) – This register indicates the bus number of the
PCI bus segment that the primary PCI Express interface is connected to. The bridge uses this
information to determine how to respond to a type 0 configuration transaction. The register
default is 00h.
Secondary Bus Number Register (PCI offset 19h) – This register indicates the bus number of
the PCI bus segment that the secondary PCI interface is connected to. The bridge uses this
information to determine how to respond to a type 1 configuration transaction. The register
default is 00h.
Subordinate Bus Number Register (PCI offset 1Ah) – This register indicates the bus number
of the highest number PCI bus segment that is downstream of the bridge. The bridge uses this
information to determine how to respond to a type 1 configuration transaction. The register
default is 00h.
Subsystem Vendor ID and Subsystem ID Registers (PCI offsets 84h and 86h) – These
registers are used for subsystem and option card identification purposes. Typically, these
registers contain the OEM vendor ID and an OEM identified designator. These fields can be
programmed using the EEPROM or BIOS. If using BIOS, the subsystem access register at
offset D0h is written to update the subsystem vendor ID and subsystem ID registers.
GPIO Control and Data Registers (PCI offsets B4h and B6h) – These registers determine the
direction of the GPIO terminals and set the default state for all GPIO outputs. The initialization
state for these registers is system architecture dependent. The control register default is GPIO
input mode.
General Control Register (PCI offset D4h) – This register controls various bridge power
management and interface operation specific functions that are fully described in the XIO2000A
Data Manual. This register can be programmed using the EEPROM or BIOS.
Clock Control and Mask Registers (PCI offsets D8h and D9h) – These registers control
enabling or disabling the seven secondary PCI bus clock outputs during both normal power
states and power override states. This register can be programmed using the EEPROM or
BIOS. The exact number of required PCI bus clocks is system implementation specific. Unused
clock outputs must be disabled.
Arbiter Control and Request Mask Registers (PCI offsets DCh and DDh) – These registers
control the internal classic PCI bus arbiter function. Register options include PCI bus high/low
priority tier selection, bus parking, request masking, arbitration timeout, and automatic request
masking. This register can be programmed using the EEPROM or BIOS.
Serial IRQ Mode and Edge Control Registers (PCI offsets E0h, E2h and E3h) – These
registers control the operating characteristics of the serial IRQ interface. Register options
include internal classic PCI bus arbiter function. Register options include start frame pulse width,
continuous versus quiet mode, interface drive mode, and level versus edge mode interrupt
detection. This register can be programmed using the EEPROM or BIOS.
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8
Power Management Considerations
8.1
D3/L2 Power Management Information
The PCI Express Card Electromechanical Specification contains a section that specifies the
operation of a PCI Express device when transitioning from D0/L0 to D3/L2 and back to D0/L0
power management states. Because the primary interface on the XIO2000A is PCI Express, the
bridge supports this specification for both D3hot and D3cold power management states. System
software has the option to place the bridge into the D3/L2 power management state. This
process is started in the bridge by setting the PWR_STATE field in the power management
control and status register to 11b. By following the procedure outlined in the PCI Express Card
Electromechanical Specification, the bridge may be transitioned to either the D3hot or D3cold
states to reduce system power.
A downstream PCI bus device may assert PME to initiate the power management state
transition from D3/L2 back to D0/L0. As a PCI Express to PCI bus translation bridge, the
XIO2000A contains the functionality to detect a secondary bus PME event and to generate an
upstream PCI Express WAKE or beacon signal. After the bridge enters the D3/L2 power
management state and PERST is asserted, the detection of a PME event is forwarded to the
PCI Express interface by asserting WAKE or generating a beacon signal. WAKE is always
asserted by the bridge. For a beacon signal to be generated, bit 10 (BEACON_ENABLE) in the
general control register must be asserted. WAKE and beacon remain active until PERST is
deasserted.
A VDD_33_AUX power terminal, coupled with internal circuits that combine main power and VAUX
power, supplies power to the logic that controls power management state transitions from D3cold
back to D0/L0. Internal “sticky” logic maintains not only the content of specific bridge PCI
register bits, but also information about the operational states of the bridge including state
machine context and other internal mechanisms. PERST has no effect on the internal “sticky”
logic.
8.2
Active State Power Management Information
The PCI Express interface on the XIO2000A can automatically reduce power when there is no
queued bus activity. Once this feature is enabled by software, the XIO2000A device
automatically transitions into and out of a low power state. The bridge supports both the L0’s
and L1 active state power management (ASPM) requirements.
In the PCI Express link capabilities registers, two 3-bit exit latency fields specify the latency time
required for the Bridge to transition from either the L0 or L1 state back to the L0 state. In the PCI
Express device capabilities register, two 3-bit acceptable latency fields specify the maximum
latency time that the Bridge will tolerate for the attached upstream PCI Express device to
transition from either the L0’s or L1 state back to the L0 state. The acceptable latency fields are
an indirect measure of the Bridge’s internal buffering.
Power management software uses the reported acceptable latency number to compare against
the exit latencies reported by all components physically located on the PCI-Express link between
the Bridge and the Root Complex to determine whether ASPM entry can be used with no
significant impact to system performance.
20
XIO2000A Implementation Guide
SCPU027C
8.3
PCI Bus Power Override Information
System software has the ability to manually reduce power on the secondary PCI bus using the
bridge’s power override feature. During system initialization, XIO2000A configuration registers
must be loaded with system specific power information and power override instructions. After
this initial setup, the PCI Express set slot power limit message may be used to either enable or
disable the power override feature.
During system initialization the following configuration register fields are loaded. These fields are
loaded by either the BIOS or serial EEPROM.
1. The general control register contains MIN_POWER_SCALE and MIN_POWER_VALUE
fields that are loaded with the power information associated with the bridge and all
downstream PCI bus devices.
2. The general control register contains a POWER_OVRD field that is loaded with the
secondary PCI bus power override option.
3. If the power override option associated with disabling secondary clocks is selected, the
clock mask register should be initialized.
After the previously described initialization procedure, the PCI Express set slot power limit
message may be used to either enable or disable the power override feature. If the scale and
value power information in the PCI Express message is less than the general control register
SCALE and VALUE fields, then the power override feature is enabled. If the scale and value
power information in the PCI Express message is equal to or greater than the SCALE and
VALUE fields, then the power override feature is disabled.
8.4
CLKRUN Information
By implementing the CLKRUN feature, when the PCI bus is inactive, the bridge automatically
stops the PCI clocks to reduce system power. The bridge supports the clock run protocol as
specified in the PCI Mobile Design Guide and assumes the role of the central resource master.
When PERST is deasserted, the logic state of terminal B15 (CLKRUN_EN) is checked. If B15 is
connected to VDD_33, the clock run feature is enabled. Terminal T05 (GPIO0) becomes the
CLKRUN signal.
An external pullup resistor to VDD_33 is required on terminal T05 (GPIO0) to keep the CLKRUN
signal from floating. The value of this pullup resistor must be large enough to assure a logic low
when the weakest driver attached to the CLKRUN signal is active. The CLKRUN driver in the
bridge is 4 mA. The minimum recommended pullup resistor value is 1.65 kΩ. This resistor value
de-rates the CLKRUN driver maximum current sinking requirement by 50 percent to reduce
system power.
Additional detail related to the CLKRUN feature is provided in the XIO2000A Data Manual.
XIO2000A Implementation Guide
21
SCPU027C
8.5
PCI Bus Clock Power and EMI Considerations
After an XIO2000A power-up sequence, all PCI bus clocks are enabled and toggling. The
system designer should consider both the power and EMI implications associated with this
power-up default mode.
This clock default mode was chosen to ensure that all PCI devices attached to the secondary
bus are reset according to PCI bus specification requirements. Immediately after a system
power-up, there are several options for disabling unused PCI bus clocks, thus reducing both
system power and EMI.
In the Classic PCI Configuration Register Space at offset D8h is the Clock Control Register. Bits
6:0 in this register control enabling or disabling the CLKOUT[6:0] terminals on the XIO2000A
device. These bits may be written from either the serial EEPROM or through the BIOS. Disabling
all unused PCI bus clocks is highly recommended.
NOTE: The CLKOUT[6] terminal is normally used as the PCI bus feedback clock for the
XIO2000A. Disabling this clock is not recommended because this stops the operation of the
XIO2000A’s PCI bus interface logic.
If the system contains multiple PCI bus add-in card slots, the decision to enable or disable each
clock should be controlled by the BIOS. If the BIOS queries each add-in slot behind the
XIO2000A, a device ID and vendor ID response indicates the presence of an add-in card. An
FFFF FFFFh response indicates that no device is present and the PCI bus clock associated with
that add−in slot should be disabled.
22
XIO2000A Implementation Guide
SCPU027C
9
Reference Schematics GZZ/ZZZ Package
The following schematics show the most basic implementation of the XIO2000A possible. These
schematics provide minimum bridge functionality.
XIO2000A Implementation Guide
23
5
4
DVCC_3.3V
C2
R1 COM2
R2
R8
R3
R7
R4
R6
COM1 R5
10
9
8
7
6
GPIO4
GPIO5
GPIO6
GPIO7
1uF
CTS 10Kx8 Bus Res - 746 series
J1
1
3
5
7
9
11
2
4
6
8
10
12
GPIO1
GPIO3
GPIO5
GPIO7
PCI_PME#
HDR6X2 M .1X.1
DVCC_3.3V
U2
C
1
2
3
4
A0
A1
A2
VSS
VCC
WP
SCL
SDA
WP
0 GPIO4
0 GPIO5
R28
R29
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
C39
.1uF
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
T5
U5
T6
U6
R7
T7
U7
U8
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
REFCLK_SEL
J17
M16
PERST#
WAKE#
L16
L17
REF0
REF1
C16
C17
CLKCLK+
RXn
RXp
E16
E17
RXn
RXp
TXn
TXp
H16
H17
TXn
TXp
G7
G8
G9
G10
G11
H7
H8
H9
H10
H11
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
14.3K
232
J1
A4
K14
VCCP
VCCP
VDD_33_AUX
D15
K15
VDDA_33
VDDA_33
F17
J15
J14
G15
J4
P7
D9
P15
H14
VDD_15
VDD_15
VDD_15
VDD_15
VDDA_15
VDDA_15
VDDA_15
VDDA_15
VDDA_15
Analog
Misc
1.5V 3.3V
XIO2000
EXPRESS
A16
1.5V
Power
Misc
REFCLK_SEL
ClkClk+
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PERR#
SERR#
PRST#
M66EN
LOCK#
P3
G1
G2
G3
F1
F2
E2
F3
E1
U3
R1
U4
INTA#
INTB#
INTC#
INTD#
R2
T1
U2
T3
R26
Thermal
Digital
C5
.1uF
1000pF
C8
.1uF
.1uF
DVCC_3.3V
FB2
C9
DVcc_3.3V
.1uF
C18
.1uF
C19
C17
.1uF
1000pF
PCI_PME#
PCI_REQ#4
PCI_REQ#5
WP
SERIRQ
REFCLK_SEL
.1uF
D
R10 R21 R22 R25
10K 10K 10K 10K
P1_REQ64#
P2_REQ64#
P3_REQ64#
PCI_ACK64#
C20
.1uF
Vaux
PCI_VIO
Vaux
220 @ 100MHZ
VDDA_3.3V
C16
R19 R61 R20
10K 10K 10K
DVcc_3.3V
C21
C22
.1uF
C23
.1uF
.1uF
C24
.1uF
C25
C26
.1uF
.1uF
C27
.1uF
C29
.1uF
C30
C31
.1uF
PCI_VIO
.1uF
PCI_C/BE#[3..0]
R27
PCI_FBCLK
1
2
3
4
5
PCI_LOCK#
DVcc_1.5V
PCI_VIO
R1 COM2
R2
R8
R3
R7
R4
R6
COM1 R5
10
9
8
7
6
PCI_M66EN
PCI_REQ#3
PCI_PRST#
CTS 10Kx8 Bus Res - 746 series
C34
.1uF
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
R6
C8
R7
B9
R8
B10
A11
A12
A13
B14 PCI_FBCLK
C7
R2 R3 R4 R5
10K 10K 10K 10K
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_PRST#
PCI_M66EN
PCI_LOCK#
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
FBCLK
C6
.1uF
49.9
C35
.1uF
C36
.1uF
C37
C38
.1uF
1000pF
C32
.1uF
C
C33
.1uF
R30
PCI_REQ#0
PCI_INTC#
PCI_INTA#
PCI_INTB#
1
2
3
4
5
R1 COM2
R2
R8
R3
R7
R4
R6
COM1 R5
10
9
8
7
6
PCI_REQ#1
PCI_INTD#
PCI_REQ#2
CTS 10Kx8 Bus Res - 746 series
47PCI_PCLK0
47PCI_PCLK1
47PCI_PCLK2
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_REQ#[2..0]
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
REQ#5
B8
C9
C10
B11
B12
B13
A8 PCI_GNT#0
A9 PCI_GNT#1
A10 PCI_GNT#2
C11
C12
A14
PCI_GNT#[2..0]
GNT#0
GNT#1
GNT#2
GNT#3
GNT#4
GNT#5
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
GROUND
J7
J8
J9
J10
J11
K7
K8
K9
K10
K11
L7
L8
L9
L10
L11
B
N15
N16
P16
R8
T8
T10
T11
T12
T14
T15
T17
U9
U11
U12
U13
U14
U15
U16
PME#
GRST#
SERIRQ
CLKRUN_EN
EXTARB_EN
R32
R33
TXn
TXp
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CLKRUN_EN
EXTARB_EN
GRST#
PERST#
WAKE#
RXn
RXp
D17
D16
P17
R9
T9
U10
M15
N17
T4
B15
A15
PCI_PME#
SERIRQ
RSVD
GPIO
24LC08B-I/ST
8
7
6
5
R16
RESERVED
DVCC_3.3V
GPIO0
GPIO2
GPIO4
GPIO6
GRST#
E3
H4
M3
R5
P9
C13
D10
C6
P10
P11
T13
R14
3.3V
.01uF 1000pF
C4
PCI
1
2
3
4
5
C15
VDDA_1.5V
PCI_AD[31..0]
XIO2000_176_GGW
PCI_AD0
AD0 A7 PCI_AD1
AD1 B7 PCI_AD2
C7
AD2
PCI_AD3
AD3 D7 PCI_AD4
AD4 A6 PCI_AD5
AD5 B6 PCI_AD6
AD6 A5 PCI_AD7
AD7 B5 PCI_AD8
AD8 C4 PCI_AD9
AD9 A3 PCI_AD10
AD10 B3 PCI_AD11
AD11 A2 PCI_AD12
AD12 B1 PCI_AD13
AD13 C2 PCI_AD14
AD14 C1 PCI_AD15
AD15 D2 PCI_AD16
AD16 H3 PCI_AD17
AD17 H2 PCI_AD18
AD18 J3 PCI_AD19
AD19 J2 PCI_AD20
AD20 K1 PCI_AD21
AD21 K2 PCI_AD22
AD22 K3 PCI_AD23
AD23 L1 PCI_AD24
AD24 L3 PCI_AD25
AD25 L4 PCI_AD26
AD26 M1 PCI_AD27
AD27 M2 PCI_AD28
AD28 N1 PCI_AD29
AD29 N2 PCI_AD30
AD30 P1 PCI_AD31
AD31 P2
PCI_C/BE#0
C/BE#0 B4 PCI_C/BE#1
C/BE#1 D1 PCI_C/BE#2
H1
C/BE#2
PCI_C/BE#3
C/BE#3 L2
Clocks/Arbiter
R1
GPIO0
GPIO1
GPIO2
GPIO3
Pull Ups/Pull Downs
DVCC_1.5V
FB1 220 @ 100MHZ
Analog
DVCC_3.3V
C14
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DVcc_3.3V
C13
Bridge Power
Filtering/Decoupling
PCI_PCLK[2..0]
R31
NOTE: C38 should go
directly under the
pin H14 on U1
PCI_IRDY#
PCI_DEVSEL#
1
2
3
4
5
PCI_PERR#
R1 COM2
R2
R8
R3
R7
R4
R6
COM1 R5
10
9
8
7
6
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
CTS 10Kx8 Bus Res - 746 series
NOTE: In actual EVM FB1 and
FB2 are L1 and L2. Inductors
have been replaced with
ferrites. Ferrites have
minimal impact on jitter but
dramatically improve EMI
characteristics.
B
G16
E15
F16
F15
H15
J16
L15
B17
G14
D3
G4
K4
N3
R4
R6
P8
K17
C14
D11
D8
C5
G17
R10
R11
R12
R13
R17
.01uF 1000pF
VDD_33_COMBIO
VDD_33_COMB
VDD_15_COMB
1uF
C12
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
D
1
PCI_VIO
.01uF 1000pF
C11
2
VDDA_3.3V
Vaux
U1
C10
VDDA_1.5V
C3
L14
K16
M17
1uF
DVCC_1.5V
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
VDD_33
C1
3
A
A
Title
Size
C
Date:
5
4
3
2
Document Number
Rev
Tuesday, February 01, 2005
1
Sheet
2
of
4
5
4
Vaux
3
PCI_12V
2
PCI_3.3V
-12V Inverting Regulator
P1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
D
WAKE#
PRSNT1#
12V
12V
GND
J_TCK
J_TDI
J_TDO
J_TMS
3.3V
3.3V
PERST#
12V
12V
RSVD
GND
SMCLK
SMDAT
GND
3.3V
J_TRST#
3.3 Vaux
WAKE#
(for PCI Slots)
PRESENT#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DVcc_5.0V
D
lms_folly
F4
C99
PERST#
10uF
Key
RXp
RXn
PRESENT#
B12
B13
B14
B15
B16
B17
B18
1
RSVD
GND
RXp0
RXn0
GND
PRSNT2#
GND
Side B
Component Side
GND
REFCLK+
REFCLKGND
TXp0
TXn0
GND
A12
A13
A14
A15
A16
A17
A18
Clk+
ClkCTXp C40
CTXn
.1uF
C41
.1uF
TXp
TXn
-12V_in
U5 PT5024
1
5V_in
2
GND
3
-12V_out
TXn
Side A
Solder
Side
C100
PCI Express x1 Card Edge
C101
100uF
4.7uF
C
C
LEDs
Power
DVCC_5.0V
DVCC_1.5V
2 D1 R34
1
330
2 D2
1
LED Red 0805
49.9
LED Red 0805
DVCC_3.3V
1
R35
EVM_12V
2 D3 R36
330
2 D4 R37
1
5V Step-Up Regulator
1K
1.5V Regulator
(for PCI Slots)
B
LED Red 0805
PCI_3.3V
LED Red 0805
PCI_12V
B
DVCC_5.0V
DVCC_1.5V
DVCC_3.3V
EVM_12V
F1
DVCC_3.3V
F2
F3
SMD250
SMD250
R38
U3
C42
10K
DVCC_3.3V
DVCC_3.3V
D7
A
1
2 R46
330
WAKE#
LED Yellow 0805
C45
DVCC_3.3V
C46
C47
.047uF
D8
1
2 R48
10uH Diode - Schottky
2
1
2
4
3
D6
18.7K 0805 1% 6.19K 0805 1%
LED Green 0805
L3
1
330
.047uF
22uF
PCI_PME#
LED Yellow 0805
R49
C44
1
100uF
10uF
4
A
C48
R47
22uF
C49
22uF
C50
Title
10uF
Size
B
2K
3
TPS72615DCQ
R45
Date:
5
6
2
330 PERST#
U4 LT1370CR
Vin 7
NFB 6
Vsw 5
GND 4
S/S 3
FB 2
VC 1
ENABLE
IN
GND GND
OUT
RESET
1
2 R44
1
C43
2
D5
10uF
1
2
3
4
5
2
Document Number
Tuesday, February 01, 2005
Rev
Sheet
1
3
of
4
5
4
DVCC_5.0V
EVM_12V
PCI_INTA#
PCI_INTC#
R50
PCI_VIO
0
D
PCI_PRST#
PCI_GNT#0
R55
PCI_AD30
PCI_AD28
PCI_AD26
0
PCI_AD24
IDSEL0
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
C
1
DVCC_3.3V
DVCC_5.0V
EVM_12V
P2
Vaux
2
DVCC_5.0V
C51
.1uF
PCI_PME#
3
DVCC_3.3V
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
P1_REQ64#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+V I/O
RESERVED
GND
GND
RESERVED
RST#
+V I/O
GNT#
GND
RESERVED
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O
REQ64#
+5V
+5V
Solder Side
PCI Connector
C54
.1uF
C55
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED
PRSNT2#
GND
GND
RESERVED
GND
CLK
GND
REQ#
+V I/O
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O
ACK64#
+5V
+5V
Component Side
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
-12V_in
C52
-12V_in
.1uF
Vaux
PCI_INTB#
PCI_INTD#
PCI_INTB#
PCI_INTD#
R51
PCI_VIO
0
PCI_PCLK0
PCI_PRST#
PCI_REQ#0
PCI_VIO
PCI_AD31
PCI_AD29
PCI_GNT#1
PCI_PME#
R53
0
PCI_AD30
PCI_AD27
PCI_AD25
PCI_AD28
PCI_AD26
PCI_C/BE#3
PCI_AD23
PCI_AD24
IDSEL1
PCI_AD21
PCI_AD19
PCI_AD22
PCI_AD20
PCI_AD17
PCI_C/BE#2
PCI_AD18
PCI_AD16
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_TRDY#
PCI_LOCK#
PCI_PERR#
PCI_STOP#
PCI_SERR#
PCI_C/BE#1
PCI_AD14
PCI_PAR
PCI_AD15
PCI_AD12
PCI_AD10
PCI_M66EN
PCI_AD13
PCI_AD11
PCI_AD9
PCI_AD8
PCI_AD7
PCI_C/BE#0
PCI_AD5
PCI_AD3
PCI_AD6
PCI_AD4
PCI_AD1
PCI_AD2
PCI_AD0
PCI_ACK64#
P2_REQ64#
C56
.1uF
EVM_12V
P3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+V I/O
RESERVED
GND
GND
RESERVED
RST#
+V I/O
GNT#
GND
RESERVED
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O
REQ64#
+5V
+5V
Solder Side
PCI Connector
C57
.1uF
.1uF
C63
.1uF
C81
.1uF
C64
C65
.1uF
C66
.1uF
C82
.1uF
C83
.1uF
C84
.1uF
C67
.1uF
.1uF
C85
.1uF
C68
C69
.1uF
.1uF
C86
C87
.1uF
.1uF
C58
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED
PRSNT2#
GND
GND
RESERVED
GND
CLK
GND
REQ#
+V I/O
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O
ACK64#
+5V
+5V
Component Side
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
P4
-12V_in
.1uF
Vaux
PCI_INTC#
PCI_INTA#
PCI_INTC#
PCI_INTA#
R52
PCI_VIO
0
PCI_PRST#
PCI_PCLK1
PCI_REQ#1
PCI_VIO
PCI_AD31
PCI_AD29
PCI_GNT#2
PCI_PME#
R54
C70
C71
.1uF
C88
C89
.1uF
.1uF
PCI_AD30
PCI_AD24
IDSEL2
PCI_C/BE#3
PCI_AD23
PCI_AD22
PCI_AD20
PCI_AD21
PCI_AD19
PCI_AD18
PCI_AD16
PCI_AD17
PCI_C/BE#2
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_LOCK#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD15
PCI_C/BE#1
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
PCI_M66EN
PCI_AD9
PCI_AD8
PCI_AD7
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1
PCI_ACK64#
P3_REQ64#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+V I/O
RESERVED
GND
GND
RESERVED
RST#
+V I/O
GNT#
GND
RESERVED
AD[30]
+3.3V
AD[28]
AD[26]
GND
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
GND
AD[18]
AD[16]
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD[15]
+3.3V
AD[13]
AD[11]
GND
AD[09]
C/BE[0]#
+3.3V
AD[06]
AD[04]
GND
AD[02]
AD[00]
+V I/O
REQ64#
+5V
+5V
Solder Side
PCI Connector
C60
.1uF
.1uF
0
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
C59
.1uF
DVCC_3.3V
C53
.1uF
C72
.1uF
C90
.1uF
C73
.1uF
C91
.1uF
C74
C61
.1uF
C75
.1uF
.1uF
C92
C93
.1uF
.1uF
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
GND
AD[01]
+V I/O
ACK64#
+5V
+5V
Component Side
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
-12V_in
PCI_INTD#
PCI_INTB#
D
PCI_PCLK2
PCI_REQ#2
PCI_VIO
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2
PCI_IRDY#
PCI_DEVSEL#
PCI_LOCK#
PCI_PERR#
PCI_SERR#
PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_M66EN
C
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
PCI_ACK64#
C62
C77
.1uF
C94
.1uF
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
.1uF
C76
.1uF
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED
PRSNT2#
GND
GND
RESERVED
GND
CLK
GND
REQ#
+V I/O
AD[31]
AD[29]
GND
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
GND
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE[1]#
AD[14]
GND
AD[12]
AD[10]
M66EN
C78
.1uF
C95
.1uF
C79
.1uF
C96
.1uF
C97
.1uF
C80
.1uF
C98
.1uF
B
B
PCI_AD[31..0]
PCI_C/BE#[3..0]
PCI_REQ#[2..0]
PCI_GNT#[2..0]
PCI_PCLK[2..0]
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_PRST#
PCI_M66EN
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
DVCC_5.0V
R56
0
DVCC_3.3V
R57
0_NF
PCI_VIO
PCI_LOCK#
PCI_PME#
PCI_AD16
R58
100
PCI_AD17
R59
100
IDSEL0
IDSEL1
PCI_AD18
R60
100
IDSEL2
A
A
Title
Size
C
Date:
5
4
3
2
Document Number
Rev
Tuesday, February 01, 2005
1
Sheet
4
of
4
SCPU027C
10
Reference Schematics ZHH Package
27
XIO2000A Implementation Guide
5
4
3
2
1
Bridge Power
Filtering/Decoupling
D VC C _3.3V
C1
C2
D VC C _1.5V
VD D A_1.5V
Pull Ups/Pull Downs
D Vcc_3.3V
VD D A_3.3V
PC I_VIO
PC I_VIO
C3
R 2 R 3 R 4 R 5 R 10
10K 10K 10K 10K 10K
Vaux
D VC C _1.5V
J11
C 12
G1
A4
J12
H 13
H 11
F12
E11
D8
N 12
L5
G4
F14
1.5V
Analog
Misc
1.5V 3.3V
D VC C _3.3V
3.3V
C 15
1uF
10
9
8
7
6
.01uF 1000pF
G PIO 4
G PIO 5
G PIO 6
G PIO 7
C TS 10Kx8 Bus R es -746 series
M 12
L14
M 13
P6
M6
L7
P8
P9
P10
P11
P14
N6
N8
N9
L10
N 10
N 11
P12
D VC C _3.3V
J1
G PIO 0
G PIO 2
G PIO 4
G PIO 6
G R ST#
1
3
5
7
9
11
2
4
6
8
10
12
G PIO 1
G PIO 3
G PIO 5
G PIO 7
PC I_PM E#
H D R 6X2 M .1X.1
D VC C _3.3V
U2
C
1
2
3
4
A0
A1
A2
VSS
VC C
W P
SC L
SD A
8
7
6
5
W P
R 28
R 29
0
0
G PIO 4
G PIO 5
C 39
24LC 08B-I/ST
.1uF
R EFC LK_SEL
A14
G R ST#
SER IR Q
H 12
K14
PER ST#
W AKE#
14.3K
232
C 14
C 13
C lkC lk+
TXn
TXp
J14
J13
R Xn
R Xp
E13
E14
TXn
TXp
G 13
G 14
XIO2000A
G PIO 0
G PIO 1
G PIO 2
G PIO 3
G PIO 4
G PIO 5
G PIO 6
G PIO 7
PM E#
G R ST#
SER IR Q
C LKR U N _EN
EXTAR B_EN
R EFC LK_SEL
PER ST#
W AKE#
R EF0
R EF1
C LKC LK+
R Xn
R Xp
C LK
FR AM E#
IR D Y#
TR D Y#
D EVSEL#
STO P#
PAR
PER R #
SER R #
PR ST#
M 66EN
LO C K#
IN TA#
IN TB#
IN TC #
IN TD #
EXPRESS
R 32
R 33
C /BE#0
C /BE#1
C /BE#2
C /BE#3
Misc
C LKR U N _EN
EXTAR B_EN
L12
L13
N3
B13
B12
PC I_PM E#
R Xn
R Xp
P3
P4
N4
M4
P5
N5
M5
L6
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
GPIO
G PIO 0
G PIO 1
G PIO 2
G PIO 3
G PIO 4
G PIO 5
G PIO 6
G PIO 7
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
RESERVED
D 13
D 14
M 14
P7
M7
N7
TXn
TXp
C LKO 0
C LKO 1
C LKO 2
C LKO 3
C LKO 4
C LKO 5
C LKO 6
R EQ #0
R EQ #1
R EQ #2
R EQ #3
R EQ #4
R EQ #5
G N T#0
G N T#1
G N T#2
G N T#3
G N T#4
G N T#5
C8
.1uF
.1uF
P1_R EQ 64#
P2_R EQ 64#
P3_R EQ 64#
PC I_AC K64#
C9
.1uF
R EFC LK_SEL
R 19
10K
D
W P
D Vcc_3.3V
D VC C _3.3V
Vaux
1L2
2
8.2 nH 0.12ohm 0805
C 16
R 20
10K
VD D A_3.3V
C 18
C 19
C 17
.1uF
1000pF
.1uF
C 20
.1uF
R 21 R 22 R 23 R 24
10K 10K 10K 10K
.1uF
C LKR U N _EN
EXTAR B_EN
PC I_R EQ #4
PC I_R EQ #5
Vaux
SER IR Q
D Vcc_3.3V
R 61
R 25 PC I_PM E#
10K
10K
C 21
C 22
.1uF
B4
C1
F2
J2
PC I_C /BE#0
PC I_C /BE#1
PC I_C /BE#2
PC I_C /BE#3
L3
F1
E4
E1
E2
E3
D2
D3
D1
P1
M1
P2
R 26
M2
N1
N2
M3
C7
PC I_R EQ #0
PC I_R EQ #1
PC I_R EQ #2
PC I_R EQ #3
PC I_R EQ #4
PC I_R EQ #5
.1uF
C 26
.1uF
.1uF
C 27
.1uF
C 29
.1uF
C 30
C 31
.1uF
.1uF
R 27
PC I_FBC LK
PC I_IN TA#
PC I_IN TB#
PC I_IN TC #
PC I_IN TD #
B7
A8
C9
A10
A11
C 11
.1uF
C 25
PC I_VIO
49.9
PC I_PC LK0
PC I_PC LK1
PC I_PC LK2
.1uF
C 24
PC I_C /BE#[3..0]
PC I_FR AM E#
PC I_IR D Y#
PC I_TR D Y#
PC I_D EVSEL#
PC I_STO P#
PC I_PAR
PC I_PER R #
PC I_SER R #
PC I_PR ST#
PC I_M 66EN
PC I_LO C K#
D7
B8
A9
D 10
B10
B11
A13
C 23
PC I_PC LK[2..0]
D Vcc_1.5V
PC I_VIO
C 32
C 34
C 35
C 36
C 37
.1uF
.1uF
C 33
.1uF
R1 CO M 2
R2
R8
R3
R7
R4
R6
CO M 1 R5
10
9
8
7
6
PC I_M 66EN
PC I_R EQ #3
PC I_PR ST#
C
C TS 10Kx8 Bus R es -746 series
.1uF
1000pF
R 30
PC I_R EQ #0
PC I_IN TC #
PC I_IN TA#
PC I_IN TB#
1
2
3
4
5
R1 CO M 2
R2
R8
R3
R7
R4
R6
CO M 1 R5
10
9
8
7
6
PC I_R EQ #1
PC I_IN TD #
PC I_R EQ #2
C TS 10Kx8 Bus R es -746 series
NOTE: C38 should go
directly under the
pin H14 on U1
R 31
PC I_IR D Y#
PC I_D EVSEL#
PC I_FBC LK
C 7 PC I_G N T#0
C 8 PC I_G N T#1
PC I_G N T#2
B9
C 10
D 11
A12
1
2
3
4
5
C 38
.1uF
.1uF
PC I_LO C K#
PC I_PER R #
PC I_R EQ #[2..0]
1
2
3
4
5
R1 CO M 2
R2
R8
R3
R7
R4
R6
CO M 1 R5
10
9
8
7
6
PC I_FR AM E#
PC I_TR D Y#
PC I_STO P#
PC I_SER R #
C TS 10Kx8 Bus R es -746 series
PC I_G N T#[2..0]
GROUND
B
F6
G7
G6
G8
H7
H8
J9
J8
G9
H9
F8
F7
N 13
L11
L9
M8
F13
H6
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Digital
B
Analog
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
Vssa
R1 CO M 2
R2
R8
R3
R7
R4
R6
CO M 1 R5
Power
R SVD
C6
C5
.1uF
1000pF
.1uF
PCI
N 14
VD D A_1.5V
1L1
2
8.2 nH 0.12ohm 0805
C4
F11
K11
G 11
G 12
E12
D 12
B14
P13
1
2
3
4
5
C 14
Clocks/Arbiter
C 13
R1
G PIO 0
G PIO 1
G PIO 2
G PIO 3
PC I_AD [31..0]
XIO 2000_176_G G W
PC I_AD 0
AD 0 A7
PC I_AD 1
AD 1 D 6 PC I_AD 2
AD 2 A6
PC I_AD 3
C
6
AD 3
PC I_AD 4
B6
AD 4
PC I_AD 5
AD 5 A5
PC I_AD 6
AD 6 B5
PC I_AD 7
AD 7 C 5 PC I_AD 8
AD 8 C 4 PC I_AD 9
AD 9 A3
PC I_AD 10
AD 10 B3
PC I_AD 11
AD 11 A2
PC I_AD 12
AD 12 B2
PC I_AD 13
AD 13 B1
PC I_AD 14
C
3
AD 14
PC I_AD 15
C
2
AD 15
PC I_AD 16
F3
AD 16
PC I_AD 17
G
2
AD 17
PC I_AD 18
G
3
AD 18
PC I_AD 19
H
1
AD 19
PC I_AD 20
H
3
AD 20
PC I_AD 21
AD 21 H 2 PC I_AD 22
AD 22 H 4 PC I_AD 23
AD 23 J1
PC I_AD 24
AD 24 J3
PC I_AD 25
AD 25 J4
PC I_AD 26
AD 26 K1
PC I_AD 27
AD 27 K2
PC I_AD 28
AD 28 K3
PC I_AD 29
AD 29 L4
PC I_AD 30
L2
AD 30
PC I_AD 31
L1
AD 31
VC C P
VC C P
VD D _33_AU X
.01uF 1000pF
D Vcc_3.3V
VD D A_33
VD D A_33
1uF
C 12
VD D A_15
VD D A_15
VD D A_15
VD D A_15
D
C 11
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
VD D _33
C 10
VD D _33_C O M BIO
VD D _33_C O M B
VD D _15_C O M B
U1
VD D _15
VD D _15
VD D _15
VD D _15
VD D A_15
F9
D9
D5
J6
J7
L8
M9
M 10
M 11
F4
K4
D4
.01uF 1000pF
K12
H 14
K13
1uF
A
A
Title
Size
C
D ate:
5
4
3
2
D ocum entN um ber
R ev
W ednesday,June 20,2007
1
Sheet
2
of
4
5
4
Vaux
3
PC I_12V
2
1
PC I_3.3V
P1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
D
W AKE#
12V
12V
R SVD
G ND
SM C LK
SM D AT
G ND
3.3V
J_TR ST#
3.3 Vaux
W AKE#
PR SN T1#
12V
12V
G ND
J_TC K
J_TD I
J_TD O
J_TM S
3.3V
3.3V
PW R G D
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
G ND
R EFC LK+
R EFC LKG ND
TXp0
TXn0
R SVD
A12
A13
A14
A15
A16
A17
A18
PR ESEN T#
D
lm s_folly
PER ST#
Key
R Xp
R Xn
PR ESEN T#
B12
B13
B14
B15
B16
B17
B18
D Vcc_5.0V
R SVD
G ND
R Xp0
R Xn0
G ND
PR SN T2#
G ND
Side B
Component Side
C lk+
C lkC TXp C 40
C TXn
.1uF
C 41
.1uF
F4
TXp
TXn
TXn
Side A
Solder Side
C 99
PC IExpress x1 C ard Edge
10uF
U 5 PT5024
C
LEDs
Power
D VC C _5.0V
-12V_in
D VC C _1.5V
C 100
2 D 1 R 34
330
2 D2
1
LED R ed 0805
330
-12V_out
100uF
D VC C _5.0V
2 D 4 R 37
1
3
C
PC I_3.3V
D VC C _3.3V
EVM _12V
2 D 3 R 36
G ND
49.9
LED R ed 0805
D VC C _3.3V
1
R 35
5V_in
2
C 101
4.7uF
1
1
1K
F1
B
LED R ed 0805
SM D 250
LED R ed 0805
B
F2
EVM _12V
PC I_12V
F3
SM D 250
C 43
D VC C _1.5V
D VC C _3.3V
100uF
R 38
U3
C 42
D VC C _3.3V
10K
D5
2 R 46
1
330
W AKE#
C 45
LED Yellow 0805
C 46
C 47
22uF
.047uF
D8
2 R 48
330
.047uF
PC I_PM E#
6.19K 0805 1%
D VC C _3.3V
1
C 44
1
10uH D iode -Schottky
2
1
2
4
3
D6
18.7K 0805 1%
D7
A
L3
1
10uF
A
C 48
C 49
C 50
Title
22uF
22uF
10uF
R 47
Size
B
4
D ocum entN um ber
R ev
2K
D ate:
5
TPS72615D C Q
R 45
LED Yellow 0805
R 49
6
2
LED G reen 0805
D VC C _3.3V
U 4 LT1370C R
Vin 7
N FB 6
Vsw 5
G ND 4
S/S 3
FB 2
VC 1
EN ABLE
IN
G ND G ND
O UT
R ESET
1
330 PER ST#
1
2
3
4
5
2
2 R 44
1
10uF
3
2
W ednesday,June 20,2007
Sheet
1
3
of
4
5
4
D VC C _5.0V
3
D VC C _5.0V
EVM _12V
C 51
.1uF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
Vaux
PC I_IN TA#
PC I_IN TC #
R 50
PC I_VIO
0
D
PC I_PR ST#
PC I_G N T#0
R 55
1
D VC C _3.3V
D VC C _5.0V
EVM _12V
EVM _12V
P2
PC I_AD 30
PC I_AD 28
PC I_AD 26
PC I_PM E#
0
2
D VC C _3.3V
PC I_AD 24
ID SEL0
PC I_AD 22
PC I_AD 20
PC I_AD 18
PC I_AD 16
PC I_FR AM E#
PC I_TR D Y#
PC I_STO P#
PC I_PAR
PC I_AD 15
PC I_AD 13
PC I_AD 11
PC I_AD 9
TR ST#
+12V
TM S
TD I
+5V
IN TA#
IN TC #
+5V
R ESER VED
+V I/O
R ESER VED
G ND
G ND
R ESER VED
R ST#
+V I/O
G N T#
G ND
R ESER VED
AD [30]
+3.3V
AD [28]
AD [26]
G ND
AD [24]
ID SEL
+3.3V
AD [22]
AD [20]
G ND
AD [18]
AD [16]
+3.3V
FR AM E#
G ND
TR D Y#
G ND
STO P#
+3.3V
SD O N E
SBO #
G ND
PAR
AD [15]
+3.3V
AD [13]
AD [11]
G ND
AD [09]
-12V
TC K
G ND
TD O
+5V
+5V
IN TB#
IN TD #
PR SN T1#
R ESER VED
PR SN T2#
G ND
G ND
R ESER VED
G ND
C LK
G ND
R EQ #
+V I/O
AD [31]
AD [29]
G ND
AD [27]
AD [25]
+3.3V
C /BE[3]#
AD [23]
G ND
AD [21]
AD [19]
+3.3V
AD [17]
C /BE[2]#
G ND
IR D Y#
+3.3V
D EVSEL#
G ND
LO C K#
PER R #
+3.3V
SER R #
+3.3V
C /BE[1]#
AD [14]
G ND
AD [12]
AD [10]
M 66EN
-12V_in
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
P3
-12V_in
.1uF
Vaux
PC I_IN TB#
PC I_IN TD #
PC I_IN TB#
PC I_IN TD #
R 51
PC I_VIO
0
PC I_PC LK0
PC I_PR ST#
PC I_G N T#1
PC I_R EQ #0
PC I_VIO
PC I_AD 31
PC I_AD 29
PC I_PM E#
R 53
0
PC I_AD 30
PC I_AD 27
PC I_AD 25
PC I_AD 28
PC I_AD 26
PC I_C /BE#3
PC I_AD 23
PC I_AD 24
ID SEL1
PC I_AD 21
PC I_AD 19
PC I_AD 22
PC I_AD 20
PC I_AD 17
PC I_C /BE#2
PC I_AD 18
PC I_AD 16
PC I_IR D Y#
PC I_FR AM E#
PC I_D EVSEL#
PC I_TR D Y#
PC I_LO C K#
PC I_PER R #
PC I_STO P#
PC I_SER R #
PC I_C /BE#1
PC I_AD 14
PC I_PAR
PC I_AD 15
PC I_AD 12
PC I_AD 10
PC I_M 66EN
PC I_AD 13
PC I_AD 11
PC I_AD 9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
TR ST#
+12V
TM S
TD I
+5V
IN TA#
IN TC #
+5V
R ESER VED
+V I/O
R ESER VED
G ND
G ND
R ESER VED
R ST#
+V I/O
G N T#
G ND
R ESER VED
AD [30]
+3.3V
AD [28]
AD [26]
G ND
AD [24]
ID SEL
+3.3V
AD [22]
AD [20]
G ND
AD [18]
AD [16]
+3.3V
FR AM E#
G ND
TR D Y#
G ND
STO P#
+3.3V
SD O N E
SBO #
G ND
PAR
AD [15]
+3.3V
AD [13]
AD [11]
G ND
AD [09]
C
PC I_C /BE#0
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PC I_AD 6
PC I_AD 4
PC I_AD 2
PC I_AD 0
P1_R EQ 64#
C /BE[0]#
+3.3V
AD [06]
AD [04]
G ND
AD [02]
AD [00]
+V I/O
R EQ 64#
+5V
+5V
SolderSide
PC IC onnector
C 54
AD [08]
AD [07]
+3.3V
AD [05]
AD [03]
G ND
AD [01]
+V I/O
AC K64#
+5V
+5V
C om ponentSide
C 55
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PC I_AD 8
PC I_AD 7
PC I_C /BE#0
PC I_AD 5
PC I_AD 3
PC I_AD 6
PC I_AD 4
PC I_AD 1
PC I_AD 2
PC I_AD 0
PC I_AC K64#
P2_R EQ 64#
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
C 63
C 64
C 65
C 66
C 67
Vaux
PC I_IN TC #
PC I_IN TA#
PC I_IN TC #
PC I_IN TA#
R 52
PC I_VIO
0
PC I_PR ST#
PC I_PC LK1
PC I_G N T#2
PC I_R EQ #1
PC I_VIO
PC I_AD 31
PC I_AD 29
PC I_PM E#
R 54
0
PC I_AD 30
PC I_AD 28
PC I_AD 26
PC I_AD 27
PC I_AD 25
PC I_AD 24
ID SEL2
PC I_C /BE#3
PC I_AD 23
PC I_AD 22
PC I_AD 20
PC I_AD 21
PC I_AD 19
PC I_AD 18
PC I_AD 16
PC I_AD 17
PC I_C /BE#2
PC I_FR AM E#
PC I_IR D Y#
PC I_TR D Y#
PC I_D EVSEL#
PC I_STO P#
PC I_LO C K#
PC I_PER R #
PC I_SER R #
PC I_PAR
PC I_AD 15
PC I_C /BE#1
PC I_AD 14
PC I_AD 13
PC I_AD 11
PC I_AD 12
PC I_AD 10
PC I_M 66EN
PC I_AD 9
PC I_AD 8
PC I_AD 7
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PC I_C /BE#0
PC I_AD 6
PC I_AD 4
PC I_AD 5
PC I_AD 3
PC I_AD 2
PC I_AD 0
PC I_AD 1
PC I_AC K64#
P3_R EQ 64#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TR ST#
+12V
TM S
TD I
+5V
IN TA#
IN TC #
+5V
R ESER VED
+V I/O
R ESER VED
G ND
G ND
R ESER VED
R ST#
+V I/O
G N T#
G ND
R ESER VED
AD [30]
+3.3V
AD [28]
AD [26]
G ND
AD [24]
ID SEL
+3.3V
AD [22]
AD [20]
G ND
AD [18]
AD [16]
+3.3V
FR AM E#
G ND
TR D Y#
G ND
STO P#
+3.3V
SD O N E
SBO #
G ND
PAR
AD [15]
+3.3V
AD [13]
AD [11]
G ND
AD [09]
-12V
TC K
G ND
TD O
+5V
+5V
IN TB#
IN TD #
PR SN T1#
R ESER VED
PR SN T2#
G ND
G ND
R ESER VED
G ND
C LK
G ND
R EQ #
+V I/O
AD [31]
AD [29]
G ND
AD [27]
AD [25]
+3.3V
C /BE[3]#
AD [23]
G ND
AD [21]
AD [19]
+3.3V
AD [17]
C /BE[2]#
G ND
IR D Y#
+3.3V
D EVSEL#
G ND
LO C K#
PER R #
+3.3V
SER R #
+3.3V
C /BE[1]#
AD [14]
G ND
AD [12]
AD [10]
M 66EN
C /BE[0]#
+3.3V
AD [06]
AD [04]
G ND
AD [02]
AD [00]
+V I/O
R EQ 64#
+5V
+5V
SolderSide
PC IC onnector
AD [08]
AD [07]
+3.3V
AD [05]
AD [03]
G ND
AD [01]
+V I/O
AC K64#
+5V
+5V
C om ponentSide
-12V_in
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PC I_IN TD #
PC I_IN TB#
D
PC I_PC LK2
PC I_R EQ #2
PC I_VIO
PC I_AD 31
PC I_AD 29
PC I_AD 27
PC I_AD 25
PC I_C /BE#3
PC I_AD 23
PC I_AD 21
PC I_AD 19
PC I_AD 17
PC I_C /BE#2
PC I_IR D Y#
PC I_D EVSEL#
PC I_LO C K#
PC I_PER R #
PC I_SER R #
PC I_C /BE#1
PC I_AD 14
PC I_AD 12
PC I_AD 10
PC I_M 66EN
C
PC I_AD 8
PC I_AD 7
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PC I_AD 5
PC I_AD 3
PC I_AD 1
PC I_AC K64#
C 58
C 59
.1uF
.1uF
.1uF
.1uF
C 82
C 83
C 60
C 84
.1uF
.1uF
C 85
.1uF
.1uF
.1uF
C 61
.1uF
C 62
.1uF
C 70
C 71
C 72
C 73
C 74
C 75
C 76
C 77
C 78
C 79
C 80
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
C 86
C 87
.1uF
.1uF
C 68
C 69
C 81
.1uF
.1uF
.1uF
.1uF
AD [08]
AD [07]
+3.3V
AD [05]
AD [03]
G ND
AD [01]
+V I/O
AC K64#
+5V
+5V
C om ponentSide
P4
-12V_in
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
C 56
.1uF
.1uF
.1uF
-12V
TC K
G ND
TD O
+5V
+5V
IN TB#
IN TD #
PR SN T1#
R ESER VED
PR SN T2#
G ND
G ND
R ESER VED
G ND
C LK
G ND
R EQ #
+V I/O
AD [31]
AD [29]
G ND
AD [27]
AD [25]
+3.3V
C /BE[3]#
AD [23]
G ND
AD [21]
AD [19]
+3.3V
AD [17]
C /BE[2]#
G ND
IR D Y#
+3.3V
D EVSEL#
G ND
LO C K#
PER R #
+3.3V
SER R #
+3.3V
C /BE[1]#
AD [14]
G ND
AD [12]
AD [10]
M 66EN
C /BE[0]#
+3.3V
AD [06]
AD [04]
G ND
AD [02]
AD [00]
+V I/O
R EQ 64#
+5V
+5V
SolderSide
PC IC onnector
C 57
.1uF
D VC C _3.3V
C 53
C 52
C 88
C 89
C 90
C 91
C 92
C 93
C 94
C 95
C 96
C 97
C 98
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
B
B
PC I_AD [31..0]
PC I_C /BE#[3..0]
PC I_R EQ #[2..0]
PC I_G N T#[2..0]
PC I_PC LK[2..0]
PC I_FR AM E#
PC I_IR D Y#
PC I_TR D Y#
PC I_D EVSEL#
PC I_STO P#
PC I_PAR
PC I_PER R #
PC I_SER R #
PC I_PR ST#
PC I_M 66EN
PC I_IN TA#
PC I_IN TB#
PC I_IN TC #
PC I_IN TD #
D VC C _5.0V
R 56
D VC C _3.3V
R 57
0
0_N F
PC I_VIO
PC I_LO C K#
PC I_PM E#
PC I_AD 16
R 58
100
ID SEL0
PC I_AD 17
R 59
100
ID SEL1
PC I_AD 18
R 60
100
ID SEL2
A
A
Title
Size
C
D ate:
5
4
3
2
D ocum entN um ber
R ev
W ednesday,June 20,2007
1
Sheet
4
of
4
SCPU027C
11
Reference Documents
1.
2.
3.
4.
5.
6.
7.
8.
9.
PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
PCI Express Base Specification, Revision 1.0a
PCI Express Card Electromechanical Specification, Revision 1.0a
PCI Local Bus Specification, Revision 2.3
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PCI Bus Power Management Interface Specification, Revision 1.1 or 1.2
PCI Mobile Design Guide, Revision 1.1
Serialized IRQ Support for PCI Systems, Revision 6.0
Express Card Standard, Release 1.0
XIO2000A Implementation Guide
31
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