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1 OMAP3515/03 Applications Processor
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OMAP3515/03 Applications Processor:
– OMAP™ 3 Architecture
– MPU Subsystem
• 600-MHz ARM Cortex™-A8 Core
• NEON™ SIMD Coprocessor
– POWERVR SGX™ 2D/3D Graphics
Accelerator (OMAP3515 Device Only)
• Tile Based Architecture Delivering up to
10 MPoly/sec
• Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating
Pixel and Vertex Shader Functionality
• Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
• Fine Grained Task Switching, Load
Balancing, and Power Management
• Programmable High Quality Image
Anti-Aliasing
– Fully Software-Compatible With ARM9™
– Commercial and Extended Temperature
Grades
ARM Cortex™-A8 Core
– ARMv7 Architecture
• Trust Zone®
• Thumb®-2
• MMU Enhancements
– In-Order, Dual-Issue, Superscalar
Microprocessor Core
– NEON™ Multimedia Architecture
– Over 2x Performance of ARMv6 SIMD
– Supports Both Integer and Floating Point
SIMD
– Jazelle® RCT Execution Environment
Architecture
– Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
– Embedded Trace Macrocell (ETM) Support
for Non-Invasive Debug
ARM Cortex™-A8 Memory Architecture:
– 16K-Byte Instruction Cache (4-Way
Set-Associative)
– 16K-Byte Data Cache (4-Way
Set-Associative)
– 256K-Byte L2 Cache
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112K-Byte ROM
64K-Byte Shared SRAM
Endianess:
– ARM Instructions - Little Endian
– ARM Data – Configurable
External Memory Interfaces:
– SDRAM Controller (SDRC)
• 16, 32-bit Memory Controller With
1G-Byte Total Address Space
• Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
• SDRAM Memory Scheduler (SMS) and
Rotation Engine
– General Purpose Memory Controller
(GPMC)
• 16-bit Wide Multiplexed Address/Data
Bus
• Up to 8 Chip Select Pins With 128M-Byte
Address Space per Chip Select Pin
• Glueless Interface to NOR Flash, NAND
Flash (With ECC Hamming Code
Calculation), SRAM and Pseudo-SRAM
• Flexible Asynchronous Protocol Control
for Interface to Custom Logic (FPGA,
CPLD, ASICs, etc.)
• Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
System Direct Memory Access (sDMA)
Controller (32 Logical Channels With
Configurable Priority)
Camera Image Signal Processing (ISP)
– CCD and CMOS Imager Interface
– Memory Data Input
– RAW Data Interface
– BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
– A-Law Compression and Decompression
– Preview Engine for Real-Time Image
Processing
– Glueless Interface to Common Video
Decoders
– Histogram Module/Auto-Exposure,
Auto-White Balance, and Auto-Focus
Engine
– Resize Engine
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
POWERVR SGX is a trademark of Imagination Technologies Ltd.
OMAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008–2009, Texas Instruments Incorporated
PRODUCT PREVIEW
1.1 Features
OMAP3515/03 Applications Processor
SPRS505C – FEBRUARY 2008 – REVISED FEBRUARY 2009
•
PRODUCT PREVIEW
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2
• Resize Images From 1/4x to 4x
• Separate Horizontal/Vertical Control
Display Subsystem
– Parallel Digital Output
• Up to 24-Bit RGB
• HD Maximum Resolution
• Supports Up to 2 LCD Panels
• Support for Remote Frame Buffer
Interface (RFBI) LCD Panels
– 2 10-Bit Digital-to-Analog Converters
(DACs) Supporting:
• Composite NTSC/PAL Video
• Luma/Chroma Separate Video (S-Video)
– Rotation 90-, 180-, and 270-degrees
– Resize Images From 1/4x to 8x
– Color Space Converter
– 8-bit Alpha Blending
Serial Communication
– 5 Multichannel Buffered Serial Ports
(McBSPs)
• 512 Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
• 5K-Byte Transmit/Receive Buffer
(McBSP2)
• SIDETONE Core Support (McBSP2 and 3
Only) For Filter, Gain, and Mix
Operations
• Direct Interface to I2S and PCM Device
and TDM Buses
• 128 Channel Transmit/Receive Mode
– Four Master/Slave Multichannel Serial Port
Interface (McSPI) Ports
– High-Speed/Full-Speed/Low-Speed USB
OTG Subsystem (12-/8-Pin ULPI Interface)
– High-Speed/Full-Speed/Low-Speed
Multiport USB Host Subsystem
• 12-/8-Pin ULPI Interface or 6-/4-/3-Pin
Serial Interface
• Supports Transceiverless Link Logic
(TLL)
– One HDQ/1-Wire Interface
– Three UARTs (One with Infrared Data
Association [IrDA] and Consumer Infrared
[CIR] Modes)
– Three Master/Slave High-Speed
Inter-Integrated Circuit (I2C) Controllers
Removable Media Interfaces:
– Three Multimedia Card (MMC)/ Secure
Digital (SD) With Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock
Management
OMAP3515/03 Applications Processor
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– SmartReflex™ Technology
– Dynamic Voltage and Frequency Scaling
(DVFS)
Test Interfaces
– IEEE-1149.1 (JTAG) Boundary-Scan
Compatible
– Embedded Trace Macro Interface (ETM)
– Serial Data Transport Interface (SDTI)
12 32-bit General Purpose Timers
2 32-bit Watchdog Timers
1 32-bit 32-kHz Sync Timer
Up to 188 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
65-nm CMOS Technology
Package-On-Package (POP) Implementation
for Memory Stacking (Not Available in CUS
Package)
Discrete Memory Interface (Not Available in
CBC Package)
Packages:
– 515-pin s-PBGA package (CBB Suffix),
.5mm Ball Pitch (Top), .4mm Ball Pitch
(Bottom)
– 515-pin s-PBGA package (CBC Suffix),
.65mm Ball Pitch (Top), .5mm Ball Pitch
(Bottom)
– 423-pin s-PBGA package (CUS Suffix),
.65mm Ball Pitch
1.8-V I/O and 3.0-V (MMC1 only),
0.975-V to 1.35-V Adaptive Processor Core
Voltage,
0.975-V to 1.35-V Adaptive Core Logic Voltage
Note: These are default Operating
Performance Point (OPP) voltages and could
be optimized to lower values using
SmartReflex™ AVS.
Applications:
– Portable Navigation Devices
– Portable Media Player
– Advanced Portable Consumer Electronics
– Digital TV
– Digital Video Camera
– Portable Data Collection
– Point-of-Sale Devices
– Gaming
– Web Tablet
– Smart White Goods
– Smart Home Controllers
– Ultra Mobile Devices
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1.2 Description
OMAP3515 and OMAP3503 high-performance, applications processors are based on the enhanced
OMAP™ 3 architecture.
The device supports high-level operating systems (OSs), such as:
• Linux
• Windows CE
• Symbian OS
• Palm OS
This OMAP device includes state-of-the-art power-management techniques required for high-performance
mobile products.
The following subsystems are part of the device:
• Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
• POWERVR SGX™ subsystem for 2D and 3D graphics acceleration to support display and gaming
effects (3515only)
• Camera image signal processor (ISP) that supports multiple formats and interfacing options connected
to a wide variety of image sensors
• Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
• Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple
initiators to the internal and external memory controllers and to on-chip peripherals
The device also offers:
• A comprehensive power and clock-management scheme that enables high-performance, low-power
operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative
voltage control. This power management technique for automatic control of the operating voltage of a
module reduces the active power consumption.
• Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC
packages only)
OMAP15/03 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package
(CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages
are not available in the CUS package.
Table 1-1 lists the differences between the CBB, CBC, and CUS packages.
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The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing
sufficient to support the following:
• Streaming video
• 2D/3D mobile gaming
• Video conferencing
• High-resolution still image
OMAP3515/03 Applications Processor
SPRS505C – FEBRUARY 2008 – REVISED FEBRUARY 2009
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Table 1-1. Differences Between CBB, CBC, and CUS Packages
FEATURE
CBB PACKAGE
CBC PACKAGE
For CBC package pin
assignments see Table 2-2, Ball
Characteristics (CBC Pkg.)
For CUS package pin
assignments see Table 2-3, Ball
Characteristics (CUS Pkg.)
POP interface supported
POP interface supported
POP interface not available
Discrete Memory Interface
supported
Discrete Memory Interface not
supported
Discrete Memory Interface
supported
Eight chip select pins available
Eight chip select pins available
Chip select pins gpmc_ncs1 and
gpmc_ncs2 are not available
Four wait pins available
Four wait pins available
Wait pins gpmc_wait1 and
gpmc_wait2 are not available
UART1
CTS signal is available on 3 pins
(triple muxed): uart1_cts (AG22 /
W8 / T21), uart1_rts (AH22 /
AA9), uart1_tx (F28 / Y8 / AE7),
uart1_rx (E26 / AA8)
The following signals are either
available on two (double muxed)
or three pins (triple muxed):
uart1_cts (AE21 / T19 / W2),
uart1_rts (AE22 / R2), uart1_rx
(H3 / H25 / AE4), uart1_tx (L4 /
G26)
CTS signal is available on 3 pins
(triple muxed): uart1_cts (AC19 /
AC2 / AA18), uart1_rts (W6 /
AB19), uart1_tx (E23 / V7 / AC3),
uart1_rx (D24 / W7)
UART2
The following signals are
available on two pins (double
muxed): uart2_cts (AF6/AB26),
uart2_rts (AE6/AB25), uart2_tx
(AF5/AA25), uart2_rx
(AE5/AD25)
The following signals are
available on two pins (double
muxed): uart2_cts (Y24/P3),
uart2_rts (AA24/N3), uart2_tx
(AD22/U3), uart2_rx (AD21/W3)
The following signals are
available on one pin only:
uart2_cts (V6), uart2_rts (V5),
uart2_tx (W4), uart2_rx (V4)
McBSP3
The following signals are
available on three pins (triple
muxed): mcbsp3_dx (AF6 / AB26
/ V21), mcbsp3_dr (AE6 / AB25 /
U21), mcbsp3_clkx (AF5 / AA25 /
W21), and mcbsp3_fsx (AE5 /
AD25 / K26)
The following signals are
available on two pins (triple
muxed): mcbsp3_dx (U17/ Y24/
P3), mcbsp3_dr (T20/ AA24 /
N3), mcbsp3_clkx (T17/ AD22 /
U3), mcbsp3_fsx (P20/ AD21 /
W3)
The following signals are
available on two pins only
(double muxed): mcbsp3_dx
(V6/W18), mcbsp3_dr (V5/Y18),
mcbsp3_clkx (W4/V18), and
mcbsp3_fsx (V4/AA19)
GP Timer
The following signals are
available on three pins (triple
muxed): gpt8_pwm_evt (N8 /
AD25 / V3), gpt9_pwm_evt (T8 /
AB26 / Y2), gpt10_pwm_evt (R8
/ AB25 / Y3), and
gpt11_pwm_evt (P8 / AA25 / Y4)
The following signals are
available on three pins (triple
muxed): gpt8_pwm_evt
(C5/AD21/V9), gpt9_pwm_evt
(B4/W8/Y24),
gpt10_pwm_evt(C4/U8/AA24),
gpt11_pwm_evt(B5/V8/AD22)
The following signals are
available on two pins only
(double muxed): gpt8_pwm_evt
(G4/M4), gpt9_pwm_evt (F4/N4),
gpt10_pwm_evt (G5/N3), and
gpt11_pwm_evt (F3/M5)
McBSP4
The following signals are
available on two pins (double
muxed): mcbsp4_clkx (T8/AE1),
mcbsp4_dr (R8/AD1),
mcbsp4_dx (P8/AD2),
mcbsp4_fsx (N8/AC1)
The following signals are
available on two pins(double
muxed): mcbsp4_clkx (B4 / V3),
mcbsp4_dr (C4 / U4),
mcbsp4_dx (B5 / R3),
mcbsp4_fsx (C5 / T3)
The following signals are
available on one pin only:
mcbsp4_clkx (F4), mcbsp4_dr
(G5), mcbsp4_dx (F3),
mcbsp4_fsx (G4)
HSUSB3_TLL
Supported
Supported
Not supported
MM_FSUSB3
Supported
Supported
Not supported
McSPI1
Four chip select pins are
available
Four chip select pins are
available
Chip select pins mcspi1_cs1 and
mcspi_cs2 are not available
MMC3
The following signals are
available on two pins (double
muxed): mmc3_cmd (AC3 /
AE10), and mmc3_clk (AB1 /
AF10)
The following signals are
available on two pins (double
muxed): mmc3_cmd (R8 / AB3),
mmc3_clk (R9 / AB2)
The following signals are
available on one pin only:
mmc3_cmd (AD3), and
mmc3_clk (AC1)
Pin Assignments
Package-On-Package (POP)
Interface
Discrete Memory Interface
GPMC
PRODUCT PREVIEW
4
CUS PACKAGE
For CBB package pin
assignments seeTable 2-1, Ball
Characteristics (CBB Pkg.)
OMAP3515/03 Applications Processor
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Table 1-1. Differences Between CBB, CBC, and CUS Packages (continued)
FEATURE
CBB PACKAGE
CBC PACKAGE
CUS PACKAGE
A maximum of 170 GPIO pins
are supported.
A maximum of 188 GPIO pins
are supported.
A maximum of 188 GPIO pins
are supported.
Pin muxing restricts the total
number of GPIO pins available at
one time. For more details, see
Table 2-6, Multiplexing
Characteristics (CUS Pkg.).
This OMAP3515/03 Applications Processor data manual presents the electrical and mechanical
specifications for the OMAP3515/03 Applications Processor. The information contained in this data
manual applies to both the commercial and extended temperature versions of the OMAP3515/03
Applications Processor unless otherwise indicated. It consists of the following sections:
• A description of the OMAP3515/03 terminals: assignment, electrical characteristics, multiplexing, and
functional description (Section 2)
• A presentation of the electrical characteristics requirements: power domains, operating conditions,
power consumption, and dc characteristics (Section 3)
• The clock specifications: input and output clocks, DPLL and DLL (Section 4)
• The video DAC specification (Section 5)
• The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6)
• A description of thermal characteristics, device nomenclature, and mechanical data about the available
packaging (Section 7)
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GPIO
The following GPIO pins are not
available: gpio_112, gpio_113,
gpio_114, gpio_115, gpio_52,
gpio_53, gpio_63, gpio_64,
gpio_144, gpio_145, gpio_146,
gpio_147, gpio_152, gpio_153,
gpio_154, gpio_155, gpio_175,
and gpio_176.
OMAP3515/03 Applications Processor
SPRS505C – FEBRUARY 2008 – REVISED FEBRUARY 2009
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the OMAP3515/03 Applications Processor.
OMAP Applications Processor
LCD Panel
MPU
Subsystem
Camera
(Parallel)
Amp
Parallel
ARM CortexA8TM Core
16K/16K L1$
POWERVR
SGXTM
Graphics
Accelerator
(3515 Only)
PRODUCT PREVIEW
L2$
256K
64
64
CVBS
or
S-Video
32
32
32
Channel
System
DMA
32
32
TV
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
and
Preview
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV→QCIF Support
32
64
HS USB
Host
(with
USB
TTL)
HS
USB
OTG
32
Async
64
64
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
32
32
64K
On-Chip
RAM
2KB
Public/
62KB
Secure
112K
On-Chip
ROM
80KB
Secure/
32KB
BOOT
64
SMS:
SDRAM
Memory
Scheduler/
Rotation
SDRC:
SDRAM
Memory
Controller
32
32
32
L4 Interconnect
GPMC:
General
Purpose
Memory
Controller
NAND/
NOR
Flash,
SRAM
External and
Stacked Memories
Peripherals:
3xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 6xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
2xMailboxes
12xGPTimers, 2xWDT,
32K Sync Timer
System
Controls
PRCM
2xSmartReflexTM
Control
Module
External
Peripherals
Interfaces
Emulation
Debug: SDTI, ETM, JTAG,
CoresightTM DAP
Figure 1-1. OMAP3515/03 Functional Block Diagram
6
OMAP3515/03 Applications Processor
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Contents
OMAP3515/03 Applications Processor .............. 1
1.1
Features .............................................. 1
1.2
Description ............................................ 3
1.3
Functional Block Diagram ............................ 6
4.3
5
DPLL and DLL Specifications ...................... 141
VIDEO DAC SPECIFICATIONS ..................... 147
5.1
5.2
Revision History ............................................... 8
2 TERMINAL DESCRIPTION ............................ 10
Interface Description ............................... 147
Electrical Specifications Over Recommended
Operating Conditions .............................. 149
5.3
Analog Supply (vdda_dac) Noise Requirements
2.1
Terminal Assignment ................................ 10
5.4
External Component Value Choice ................ 152
2.2
Ball Characteristics .................................. 15
2.3
Multiplexing Characteristics ......................... 68
2.4
Signal Description ................................... 91
3
4
6
ELECTRICAL CHARACTERISTICS ................ 119
3.1
Power Domains .................................... 119
3.2
Absolute Maximum Ratings ........................ 121
3.3
Recommended Operating Conditions
3.4
DC Electrical Characteristics....................... 125
3.5
Core Voltage Decoupling .......................... 128
3.6
Power-up and Power-down ........................ 130
.............
123
CLOCK SPECIFICATIONS ........................... 133
4.1
4.2
.........................
Output Clock Specifications........................
Input Clock Specifications
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134
139
7
..
151
TIMING REQUIREMENTS AND SWITCHING
CHARACTERISTICS .................................. 153
............................
.....................
6.3
Timing Parameters .................................
6.4
External Memory Interfaces........................
6.5
Video Interfaces ....................................
6.6
Serial Communications Interfaces .................
6.7
Removable Media Interfaces ......................
6.8
Test Interfaces .....................................
PACKAGE CHARACTERISTICS ....................
7.1
Package Thermal Resistance ......................
7.2
Device Support.....................................
6.1
Timing Test Conditions
153
6.2
Interface Clock Specifications
153
Contents
154
155
184
201
234
249
255
255
255
7
PRODUCT PREVIEW
1
OMAP3515/03 Applications Processor
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history table highlights the technical changes made to the SPRS505B
device-specific data manual to make it an SPRS505C revision.
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
PRODUCT PREVIEW
Global
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•
Updated/Changed "industrial temperature" to 'extended temperature"
Updated/Changed "MMC1_VDDS" to "VDDS_MMC1"
Updated/Changed buffer strength for all MMC1 I/O from ".1 mA" to" 8 mA"
Updated several CBC package signals and descriptions
Added the following ball numbers and signals: AF4, AF12, AC16, AD18, L19, AC19
Removed all instances of "PGM" Ball Reset States in Ball Characteristics tables
Updated all package types to "s-PBGA" packages
Updated/Changed commercial operating temperature (Ta) range to "0 - 70°C"
Updated/Changed Operating Performance Point (OPP) voltages
Section 1.1
•
Updated/Changed "2D/3D Graphics Accelerator..." to "POWERVR SGX™ 2D/3D Graphics
Accelerator..."
Updated/Changed "Adaptive Processor Core Voltage"...bullet
Deleted "Direct3D Mobile" from "Industry Standard API Support" bullet
•
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Table 1-1
Section 1.2
•
•
Deleted "Video capture..." bullet
Updated/Changed "2D/3D Graphics Accelerator..." to "POWERVR SGX™ subsystem for 2D/3D
Graphics Accelerator..."
Table 1-1
Added "A maximum of 188 GPIO pins are supported." to the CBB and CBC package columns
Table 2-2
Updated/Changed Table 2-2, Ball Characteristics (CBC Pkg.)
Table 2-5
Deleted "sad2d_clk26mi" signal from Multiplexing Characteristics
Table 2-7
Updated/Changed Table 2-7, External Memory Interfaces – GPMC Signals Description
Section 2.4.8
Updated/Changed Table 2-28, Power Supplies Signals Description
Table 2-28
Deleted ball number H8 from "VDDS" column.
Table 3-3
Updated/Changed the following VDD1 (SmartReflex Disabled) parameter values:
• OPP2 Low-power "NOM" value from "1.00-V" to "1.05-V"
• OPP1 Ultra Low-power "NOM" value from "0.95-V" to "0.975-V"
• MIN and MAX values from "(Vdd1nom + 0.04 * Vdd1nom) & (Vdd1nom - 0.04 * Vdd1nom)" to
"(Vdd1nom + 0.05 * Vdd1nom) & (Vdd1nom - 0.05 * Vdd1nom)"
Table 3-3
Updated/Changed Table 3-3, Recommended Operating Conditions
Section 3.4
Updated/Changed Section 3.4, DC Electrical Characteristics
Table 3-1
Deleted "vdds_dsi..." row
Table 3-4
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•
Table 4-4
Updated/Changed Table 4-4, Base Oscillator Electrical Characteristics (in Bypass Mode)
Table 4-5
Updated/Changed the following: OCS3 and OCS4 MAX values from "2.5 ns" to "3.6 ns"
Section 4.1.3
8
Updated/Changed CBB, CUS, and CBC package column information throughout table
Updated/Changed Vid parameter from "140 200 400 mV" to "70 100 200 mV" .
Added "Corresponds to peak-to-peak values: minimum = 140 mVpp; nominal = 200 mVpp; maximum =
400 mVpp." table note
Added "Note: There is an internal pulldown resistor of 5k Ω (max.) on sys_xtalin when the oscillator is
disabled. "
Table 4-1
Updated/Changed the following:
• sys_xtalout and sys_xtalin SQUARE transition value from "
