XTR111AIDRCT

XR T111 XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com Precision Voltage-to-Current Converter/Transmitter Check for Samples: XTR111 FEATURES DESCRIPTION • The XTR111 is a precision voltage-to-current converter designed for the standard 0mA–20mA or 4mA–20mA analog signals, and can source up to 36mA. The ratio between input voltage and output current is set by the single resistor RSET. The circuit can also be modified for voltage output. 1 2 • • • • • • • • EASY-TO-DESIGN INPUT/OUTPUT RANGES: 0mA–20mA, 4mA–20mA, 5mA–25mA AND VOLTAGE OUTPUTS NONLINEARITY: 0.002% LOW OFFSET DRIFT: 1μV/°C ACCURACY: 0.015% SINGLE-SUPPLY OPERATION WIDE SUPPLY RANGE: 7V to 44V OUTPUT ERROR FLAG (EF) OUTPUT DISABLE (OD) ADJUSTABLE VOLTAGE REGULATOR: 3V to 15V APPLICATIONS • • • • UNIVERSAL VOLTAGE-CONTROLLED CURRENT SOURCE CURRENT OR VOLTAGE OUTPUT FOR 3-WIRE SENSOR SYSTEMS PLC OUTPUT PROGRAMMABLE DRIVER CURRENT-MODE SENSOR EXCITATION An external P-MOSFET transistor ensures high output resistance and a broad compliance voltage range that extends from 2V below the supply voltage, VVSP, to voltages well below GND. The adjustable 3V to 15V sub-regulator output provides the supply voltage for additional circuitry. The XTR111 is available in MSOP and DFN surface-mount packages. 24V 1 VSP XTR111 REGF Regulator Out I- Mirror 5 OD EF IS 9 8 Output Disable Output Failure 2 REGS 4 15W (1) S Q2 VG 3V 3 Q1 G D ISET Signal Input 15W 6 10nF VIN Load GND 10 0mA to 20mA 4mA to 20mA (± Load Ground) SET 7 RSET IOUT = 10 VIN (RVSET ) IOUT = 10 · ISET NOTE: (1) See Application Information, External Current Limit Circuits for other options. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT XTR111 (1) PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING DFN-10 DRC BSV MSOP-10 DGQ CCM For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range (unless otherwise noted) XTR111 UNIT +44 V –0.5 to +14 V (VVSP) – 5.5 to (VVSP) + 0.5 V Voltage at REGS, REGF, VIN, OD, EF –0.5 to (VVSP) + 0.5 V Voltage at REGF, VG –0.5 to (VVSP) + 0.5 V ±25 mA Power Supply Voltage, VVSP Voltage at SET (3) Voltage at IS (3) (4) Current into any pin (3) (4) (5) Output Short-Circuit Duration (6): VG Continous to common and VVSP REGF Continous to common and VVSP Operating Temperature –55 to +125 °C Storage Temperature –65 to +150 °C 2000 V Electrostatic Discharge Rating (HBM) (1) (2) (3) (4) (5) (6) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Refer to the Package Option Addendum at the end of this document for lead temperature ratings. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited. The IS pin current absolute maximum rating is +25mA and –50mA. See the following sections Explanation of Pin Functions, External MOSFET, and Voltage Regulator in Application Information regarding safe voltage ranges and currents. See text in Application Information regarding safe voltage ranges and currents. Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range: TA = –40°C to +85°C. All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ, REGF connected to REGS; OD = Low, External FET connected, unless otherwise noted. XTR111 PARAMETER CONDITIONS MIN Specified Performance (1) 0.1 TYP MAX UNIT TRANSMITTER IOUT = 10 × VVIN/RSET Transfer Function Specified Output Current IOUT Derated Performance (2) (2) (3) Offset Current IOS Span Error, IOUT/ISET vs Temperature (2) 0.002 0.1mA to 36mA 0.004 IOUT = 4mA (1) 0.002 0.02 % of Span Input Offset Voltage (2) 0.001 % of Span/°C 0.005 % of Span/V 0.1mA to 25mA 0.015 0.1 % of Span From Drain of QEXT (4) OD = high IB VOS VVIN = 20mV vs Temperature Input Voltage Range (5) 5 ppm/°C 0.0001 % of Span/V >1 GΩ 100nF) and eventually a damping inductor or a small resistor (5Ω) to decouple the XTR111 supply from the noise typically found on the 24V supplies. Copyright © 2006–2011, Texas Instruments Incorporated SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 EF : The active low error flag (logic output) is intended for use with an external pull-up to logic-high for reliable operation when this output is used. However, it has a weak internal pull-up to 5V and can be left unconnected if not used. OD: This control input has a 4μA internal pull-up disabling the output. A pull-down or short to GND is required to activate the output. Controlling OD reduces output glitches during power-on and power-off. This logic input controls the output. If not used, connect to GND. The regulator is not affected by OD. EXTERNAL CURRENT LIMIT The XTR111 does not provide internal current limit for the case of when the external FET is forced to low impedance. The internal current source controls the current, but a high current from IS to GND forces an internal voltage clamp between VSP and IS to turn on. This results in a low resistance path and the current is only limited by the load impedance and the current capability of the external FET. A high current can destroy the IC. With the current loop interrupted (the load disconnected) the external MOSFET is fully turned on with large gate to source voltage stored in the gate capacitance. In the moment the loop is closed (the load connected) current flows into the load. But for the first few micro-seconds the MOSFET is still turned on and destructive current can flow, depending on the load impedance. An external current limit is recommended to protect the XTR111 from this condition. Figure 37a shows an example of a current limit circuit. The current should be limited to 50mA. The 15Ω resistor (R6) limits the current to approximately 37mA (33mA when hot). The PNP transistor should allow a peak current of several hundred mA. An example device is the (KST)2907. Power dissipation is not normally critical because the peak current duration is only a few micro-seconds. However, observe the leakage current through the transistor from IS to VG. The addition of this current limiting transistor and R6 still require time to discharge the gate of the external MOSFET. R7 and C3 are added for this reason, as well as to limit the steepness of external distortion pulses. Additional EMI and over-voltage protection may be required according to the application. Figure 37b is a universal and basic current limiter circuit, using PNP or NPN transistors that can be connected in the source (IS to S) or in the drain output (in series with the current path). This circuit does not contribute to leakage currents. Consider adding an output filter like R7 and C3 in this limiter circuit. 13 XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com IS IS R6 15W R6 15W Q2 Q1 VG Q2 R7 15W R8 5kW IOUT C3 10nF Q3 Table 1 lists some example devices in SO-compatible packages, but other devices can be used as well. Avoid external capacitance from IS. This capacitance could be compensated by adding additional capacitance from VG to IS; however, this compensation may slow the output down. Q1 VG IOUT a) Gate-Controlled Current Limit the OD pin high disables the gate driver and closes a switch connecting an internal 3kΩ resistor from the VSP pin to the VG pin. This resistor discharges the gate of the external FET and closes the channel; see Figure 38. The drain-to-source breakdown voltage should be selected high enough for the application. Surge voltage protection might be required for negative over-voltages. For positive over-voltages, a clamp diode to the 24V supply is recommended, protecting the FET from reversing. b) Serial Current Limit Figure 37. External Current Limit Circuits EXTERNAL MOSFET The XTR111 delivers the precise output current to the IS pin. The voltage at this pin is normally 1.4V below VVSP. VSP 16V This output requires an external transistor (QEXT) that forms a cascode for the current output. The transistor must be rated for the maximum possible voltage on VOUT and must dissipate the power generated by the current and the voltage across it. The gate drive (VG) can drive from close to the positive supply rail to 16V below the positive supply voltage (VVSP). Most modern MOSFETs accept a maximum VGS of 20V. A protection clamp is only required if a large drain gate capacitance can pulse the gate beyond the rating of the MOSFET. Pulling OD Switch 3kW VG GND Figure 38. Equivalent Circuit for Gate Drive and Disable Switch Table 1. P-Channel MOSFET (Examples) (1) (1) 14 MANUFACTURER PART NO. BREAKDOWN VGS PACKAGE C-GATE Infineon BSP170P –60V SOT-223 328pF NEC 2SJ326-Z –60V Spec. 320pF ON Semiconductor NTF2955 –60V SOT-223 492pF Supertex Inc. TP2510 –100V TO-243AA 80pF Data from published product data sheet; not ensured. Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com DYNAMIC PERFORMANCE The rise time of the output current is dominated by the gate capacitance of the external FET. The accuracy of the current mirror relies on the dynamic matching of multiple individual current sources. Settling to full resolution may require a complete cycle lasting around 100μs. Figure 39 shows an example of the ripple generated from the individual current source values that average to the specified accuracy over the full cycle. The output glitch magnitude depends on the mismatch of the internal current sources. It is approximately proportional to the output current level and scales directly with the load resistor value. It will differ slightly from part to part. The effects of filtering the output are shown in Figure 40 and Figure 41. External FET 50mV/div No Filter 500W 20ms/div Figure 39. Output Noise without Filter into 500Ω External FET 50mV/div Load Capacitor CF 10nF 500W 20ms/div Figure 40. Output with 10nF Parallel to 500Ω Copyright © 2006–2011, Texas Instruments Incorporated 15 XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com External FET NOTE: Scale has been changed from Figure 38 and Figure 39. 5mV/div Typical Filter RF 10kW 500W CF 10nF 20ms/div Figure 41. Output with Additional Filter OUTPUT ERROR FLAG AND DISABLE INPUT INPUT VOLTAGE The XTR111 has additional internal circuitry to detect an error in the output current. In case the controlled output current cannot flow due to a wire break, high load resistance or the output voltage level approaching the positive supply, the error flag (EF), an open drain logic output, pulls low. When used, this digital output requires external pull-up to logic high (the internal pull-up current is 2μA). The input voltage range for a given output current span is set by RSET according to the transfer function. Select a precise and low drift resistor for best performance, because resistor drift directly converts into drift of the output current. Careful layout must also minimize any series resistance with RSET and the VIN reference point. The output disable (OD) is a logic input with approximately 4μA of internal pull-up to 5V. The XTR111 comes up with the output disabled until the OD pin is pulled low. Logic high disables the output to zero output current. It can be used for calibration, power-on and power-off glitch reduction, and for output multiplexing with other outputs connected to the same terminal pin. Power-on while the output is disabled (OD = high) cannot fully suppress output glitching. While the supply voltage passes through the range of 3V to 4V, internal circuits turn on. Additional capacitance between pins VG and IS can suppress the glitch. The smallest glitch energy appears with the OD pin left open; for practical use, however, this pin can be driven high through a 10kΩ resistor before the 24V supply is applied, if logic voltage is available earlier. Alternatively, an open drain driver can control this pin using the internal pull-up current. Pull-up to the internal regulator tends to increase the energy because of the delay of the regulator voltage increase, again depending on the supply voltage rise time for the first few volts. 16 The input voltage is referred to the grounding point of RSET. Therefore, this point should not be distorted from other currents. Assuming a 5V full-scale input signal for a 20mA output current, RSET is 2.5kΩ. A resistance uncertainty of just 2.5Ω already degrades the accuracy to below 0.1%. The linear input voltage range extends from 0V to 12V, or 2.3V below the positive supply voltage (whichever is smaller). The lowest rated supply voltage accomodates an input voltage range of up to 5V. Potential clipping is not detected by an error signal; therefore, safe design guard banding is recommended. Do not drive the input negative (referred to GND) more than 300mV. Higher negative voltages turn on the internal protection diodes. Insert a resistor in series with the input if negative signals can occur eventually during power-on or -off or during other transient conditions. Select a resistor value limiting the possible current to 0.3mA. Higher currents are non-destructive (see Absolute Maximum Ratings), but they can produce output current glitches unless in disable mode. Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com More protection against negative input signals is provided using a standard diode and a 2.2kΩ resistor, as shown in Figure 42. 2.2kW V-Signal VIN 1N4148 Figure 42. Enhanced Protection Against Negative Overload of VIN 4mA–20mA OUTPUT The XTR111 does not provide internal circuits to generate 4mA with 0V input signal. The most common way to shift the input signal is a two resistor network connected to a voltage reference and the signal source, as shown in Figure 43. This arrangement allows easy adjustment for over-and under-range. The example assumes a 5V reference (VREF) that equals the full-scale signal voltage and a signal span of 0V to 5V for 4mA to 20mA (IMIN to IMAX) output. LEVEL SHIFT OF 0V INPUT AND TRANSCONDUCTANCE TRIM The XTR111 offers low offset voltage error at the input, which normally does not require cancellation. If the signal source cannot deliver 0V in a single-supply circuit, an additional resistor from the SET pin to a positive reference voltage or the regulator output (Figure 44) can shift the zero level for the input (VIN) to a positive voltage. Therefore, the signal source can drive this value within a positive voltage range. The example shows a +100mV (102.04mV) offset generated to the signal input. The larger this offset, however, the more influence of its drift and inaccuracy is seen in the output signal. The voltage at SET should not be larger than 12V for linear operation. Transconductance (the input voltage to output current ratio) is set by RSET. The desired resistor value may be found by choosing a combination of two resistors. XTR111 I-V Amp VIN The voltage regulator output or a more precise reference can be used as VREF. Observe the potential drift added by the drift of the resistors and the voltage reference. Reference Voltage 5V Input Voltage 0V to 5V 5V Reference R1 40kW R2 10kW 120kW SET +100mV Offset RSET 2kW VIN 1V to 5V Figure 44. Input Voltage Level Shift for 0mA Output Current Figure 43. Resistive Divider for IMIN to IMAX Output (4mA to 20mA) with 0V to VFS Signal Source Copyright © 2006–2011, Texas Instruments Incorporated 17 XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com VOLTAGE REGULATOR The externally adjustable voltage regulator provides up to 5mA of current. It offers drive (REGF) and sense (REGS) to allow external setting of the output voltage as shown in Figure 45. The sense input (REGS) is referenced to 3.0V representing the lowest adjustable voltage level. An external resistor divider sets VREGF. VREGF = VREGS · (R1 + R2)/R2 Table 2 provides example values for the regulator adjustment resistors. Table 2. Examples for the Resistor Values Setting the Regulator Voltage VREGF (1) R1 R2 3V 0 — 3.3V 3.3kΩ 33kΩ 5V 5.6kΩ 8.2kΩ 12.4V 27kΩ 8.6kΩ (1) Values have been rounded. REGF 3V The voltage at REGF is limited by the supply voltage. If the supply voltage drops close to the set voltage, the driver output saturates and follows the supply with a voltage drop of less than 1V (depending on load current and temperature). For good stability and transient response, use a load capacitance of 470nF or larger. The bias current into the sense input (REGS) is typically less than 1μA. This current should be considered when selecting high resistance values for the voltage setting because it lowers the voltage and produces additional temperature dependence. The REGF output cannot sink current. In case of supply voltage loss, the output is protected against the discharge currents from load capacitors by internal protection diodes; the peak current should not exceed 25mA. If the voltage regulator output is not used, connect REGF to REGS (the 3V mode) loaded with a 2.2nF capacitor. Alternatively, overdrive the loop pulling REGS high (see Figure 45d). REGF VREG 470nF REGS R1 5.6kW REG REGS 470nF R2 8.2kW 3V 3V (a) (b) VSP 220W 1kW REGF REGF 1kW 5V Source VREG 470nF R3 47kW REGS R1 5.6kW REGS 3V R2 8.2kW 3V (c) (d) Figure 45. Basic Connections of the Voltage Regulator 18 Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com APPLICATION BLOCK DIAGRAMS 1 VSP 5 5V C2 470nF R1 2kW 4 Current Mirror REGF OD 9 EF 8 IS 2 REGS 15W (1) R2 3kW S Q2 VG Q1 G 3 D 3V 15W Digital I/O 12-Bit Digital-to-Analog Converter DAC7551 R3 2.5kW 6 10nF VIN GND SET 10 7 0mA to 20mA CLOAD RSET 2.5kW RLOAD Figure 46. Current Using 0V to 5V Input from a 12-Bit Digital-to-Analog Converter DAC7551 1 VSP 5V C2 470nF R1 2kW 5 REGF 4 REGS Current Mirror OD 9 EF 8 IS 2 15W (1) REF3040 4096mV Voltage Reference R2 3kW S Q2 VG 3 Q1 G D 3V 15W Digital I/O 16-Bit Digital-to-Analog Converter DAC8551 R3 2kW 6 10nF VIN SET R4 817.2kW 7 GND 10 Load CLOAD NOTE: Calculate RSET for R4 parallel to RSET. RLOAD 0mA to 20mA output for 10mV to 4096mV input or a code of 160b to 65536b RSET 2kW (1.995kW) Figure 47. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for Zero Adjustment Range Copyright © 2006–2011, Texas Instruments Incorporated 19 XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com 1 VSP 5 4 OD 9 EF 8 IS 2 Current Mirror REGF REGS 15W (1) S Q2 VG Q1 G 3 D 3V 15W 0V to 10V Signal Input 6 10nF VIN GND SET 10 7 Load SW1 RSET 5kW CLOAD RLOAD Current (open) or Voltage (close) Output When output disabled and SW1 is closed, pin 7 may generate an error signal. Figure 48. 0V to 10V or 0mA to 20mA Output Selected by Jumper (SW1) (1) (a) (b) R4 100W +24V Q2 NPN Q2 NPN R3 1kW R3 1kW REGF REGF R1 10kW REGS 3V C2 470nF REGS 6V C2 470nF R2 10kW NOTE: (1) Resistor R4 can be calculated to protect Q2 from over current in fault conditions. Figure 49. Voltage Regulator Current Boost Using a Standard NPN Transistor 20 Copyright © 2006–2011, Texas Instruments Incorporated XTR111 SBOS375C – NOVEMBER 2006 – REVISED JUNE 2011 www.ti.com PACKAGE AND HEAT SINKING The dominant portion of power dissipation for the current output is in the external FET. The XTR111 only generates heat from the supply voltage with the quiescent current, the internal signal current that is 1/10 of the output current, and the current and internal voltage drop of the regulator. The exposed thermal pad on the bottom of the XTR111 package allows excellent heat dissipation of the device into the printed circuit board (PCB). THERMAL PAD The thermal pad must be connected to the same voltage potential as the device GND pin. Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences overall heat dissipation. The thermal resistance from junction-to-ambient (TJA) is specified for the packages with the exposed thermal pad soldered to a normalized PCB, as described in Technical Brief SLMA002, PowerPAD Thermally-Enhanced Package. See also EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment (SLUA271), and Quad Flatpack No-Lead Logic Packages (SCBA017). These documents are available for download at www.ti.com. NOTE: All thermal models have an accuracy variation of 20%. Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below +125°C. LAYOUT GUIDELINES The leadframe die pad should be soldered to a thermal pad on the PCB. A mechanical data sheet showing an example layout is attached at the end of this data sheet. Refinements to this layout may be required based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability. space REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June, 2010) to Revision C • Corrected wiring error in Figure 46 ..................................................................................................................................... 19 Changes from Revision A (August, 2007) to Revision B • Page Page Corrected errors in Figure 37 .............................................................................................................................................. 14 Copyright © 2006–2011, Texas Instruments Incorporated 21 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) XTR111AIDGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM XTR111AIDGQRG4 ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM XTR111AIDGQT ACTIVE HVSSOP DGQ 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM XTR111AIDGQTG4 ACTIVE HVSSOP DGQ 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM XTR111AIDRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BSV XTR111AIDRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BSV (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of