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WL1807MOD, WL1837MOD
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
WL18x7MOD WiLink™ 8 Dual-Band Industrial Module –
Wi-Fi®, Bluetooth®, and Bluetooth Low Energy (LE)
1 Device Overview
1.1
Features
1
• General
– Integrates RF, Power Amplifiers (PAs), Clock,
RF Switches, Filters, Passives, and Power
Management
– Quick Hardware Design With TI Module
Collateral and Reference Designs
– Operating Temperature: –40°C to 85°C
Industrial Temperature Grade
– Small Form Factor: 13.3 × 13.4 × 2 mm
– 100-Pin MOC Package
– FCC, IC, ETSI/CE, and TELEC Certified With
Chip Antennas
• Wi-Fi
– WLAN Baseband Processor and RF Transceiver
Support of IEEE Std 802.11a, 802.11b, 802.11g,
and 802.11n
– 20- and 40-MHz SISO and 20-MHz 2 × 2 MIMO
at 2.4 GHz for High Throughput: 80 Mbps
(TCP), 100 Mbps (UDP)
– 2.4-GHz MRC Support for Extended Range and
5-GHz Diversity Capable
– Fully Calibrated: Production Calibration Not
Required
– 4-Bit SDIO Host Interface Support
– Wi-Fi Direct Concurrent Operation
(Multichannel, Multirole)
1.2
•
•
•
•
space
• Bluetooth and Bluetooth LE (WL1837MOD
Only)
– Bluetooth 4.1 Compliance and CSA2 Support
– Host Controller Interface (HCI) Transport for
Bluetooth Over UART
– Dedicated Audio Processor Support of SBC
Encoding + A2DP
– Dual-Mode Bluetooth and Bluetooth LE
– TI's Bluetooth- and Bluetooth LE-Certified Stack
• Key Benefits
– Reduces Design Overhead
– Differentiated Use-Cases by Configuring WiLink
8 Simultaneously in Two Roles (STA and AP) to
Connect Directly With Other Wi-Fi Devices on
Different RF Channel (Wi-Fi Networks)
– Best-in-Class Wi-Fi With High-Performance
Audio and Video Streaming Reference
Applications With Up to 1.4X the Range Versus
One Antenna
– Different Provisioning Methods for In-Home
Devices Connectivity to Wi-Fi in One Step
– Lowest Wi-Fi Power Consumption in Connected
Idle (< 800 µA)
– Configurable Wake on WLAN Filters to Only
Wake up the System
– Wi-Fi-Bluetooth Single Antenna Coexistence
Applications
Internet of Things (IoT)
Multimedia
Home Electronics
Home Appliances and White Goods
•
•
•
•
Industrial and Home Automation
Smart Gateway and Metering
Video Conferencing
Video Camera and Security
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
WL1807MOD, WL1837MOD
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
1.3
www.ti.com
Description
The certified WiLink 8 module from TI offers high throughput and extended range along with Wi-Fi and
Bluetooth coexistence (WL1837MOD only) in a power-optimized design. The WL18x7MOD is a Wi-Fi,
dual-band, 2.4- and 5-GHz module solution with two antennas supporting Industrial temperature grade.
The device is FCC, IC, ETSI/CE, and TELEC certified for AP (with DFS support) and client. TI offers
drivers for high-level operating systems, such as Linux® and Android™. Additional drivers, such as WinCE
and RTOS, which includes QNX, Nucleus, ThreadX, and FreeRTOS, are supported through third parties.
Device Information (1)
ORDER NUMBER
PACKAGE
BODY SIZE
WL1807MOD
MOC (100)
13.3 mm × 13.4 mm × 2 mm
WL1837MOD
MOC (100)
13.3 mm × 13.4 mm × 2 mm
(1)
For more information, see Section 9, Mechanical Packaging and Orderable Information.
space
1.4
Functional Block Diagram
Figure 1-1 shows a functional block diagram of the WL1837MOD variant.
BG1
RF_ANT2
WRF2
ZigBee
COEX I/F
Aband
5 GHz
DPDT
D
BT : UART
WRFA
MAC/PHY
WLAN : SDIO
BT EN
BG2
RF_ANT1
WRF1
WLAN EN
2.4 GHz
SPDT
D
BT
MAC/PHY
32 kHz
26M TCXO
BTRF
F
VIO
VBAT
PM
NOTE: Dashed lines indicate optional configurations and are not applied by default.
Figure 1-1. WL1837MOD Functional Block Diagram
space
2
Device Overview
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SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
Table of Contents
1
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 2
5.17
5.18
5.19
Bluetooth LE Performance: Receiver
Characteristics – In-Band Signals................... 18
Bluetooth LE Performance: Transmitter
Characteristics....................................... 19
Bluetooth LE Performance: Modulation
Characteristics....................................... 19
2
3
4
Revision History ......................................... 3
Device Comparison ..................................... 4
Terminal Configuration and Functions .............. 5
5
Specifications
6.1
WLAN Features ..................................... 29
5.1
6.2
Bluetooth Features .................................. 29
6.3
Bluetooth LE Features .............................. 29
6.4
WiLink 8 Module Markings .......................... 30
6.5
Test Grades ......................................... 30
....................................... 7
.......................................... 10
Absolute Maximum Ratings ......................... 10
ESD Ratings ........................................ 10
Power-On Hours (POH) ............................. 10
Recommended Operating Conditions ............... 11
External Digital Slow Clock Requirements .......... 11
4.1
Pin Description
5.2
5.3
5.4
5.5
6
5.20
Bluetooth BR and EDR Dynamic Currents.......... 19
5.21
Bluetooth LE Currents
5.22
Timing and Switching Characteristics ............... 20
..............................
20
Detailed Description ................................... 28
7
Applications and Implementation ................... 31
8
Device and Documentation Support ............... 37
Application Information .............................. 31
5.6
5.7
Thermal Characteristics for MOC 100-Pin Package 11
WLAN Performance: 2.4-GHz Receiver
Characteristics....................................... 12
5.8
5.9
WLAN Performance: 2.4-GHz Transmitter Power .. 13
WLAN Performance: 5-GHz Receiver
Characteristics....................................... 14
8.1
Device Support ...................................... 37
8.2
Related Links ........................................ 37
8.3
Community Resources .............................. 37
WLAN Performance: 5-GHz Transmitter Power .... 15
8.4
Trademarks.......................................... 37
WLAN Performance: Currents ...................... 16
Bluetooth Performance: BR, EDR Receiver
Characteristics—In-Band Signals ................... 16
8.5
Electrostatic Discharge Caution ..................... 38
8.6
Glossary ............................................. 38
5.10
5.11
5.12
5.13
5.14
5.15
5.16
...........
Bluetooth Performance: Transmitter, EDR ..........
Bluetooth Performance: Modulation, BR ............
Bluetooth Performance: Modulation, EDR ..........
Bluetooth Performance: Transmitter, BR
7.1
9
17
Mechanical Packaging and Orderable
Information .............................................. 39
17
9.1
TI Module Mechanical Outline
18
9.2
Tape and Reel Information .......................... 40
18
9.3
Packaging Information
......................
..............................
39
42
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2015) to Revision H
•
•
•
•
•
Page
Changed parameter headings from "2G4_ANT2_W + 2G4_ANT1_WB Pins" in Section 5.8, WLAN Performance:
2.4-GHz Transmitter Power ........................................................................................................
Added note 3 in Section 5.13, Bluetooth Transmitter, BR .....................................................................
Added note 3 in Section 5.14, Bluetooth Performance: Transmitter, EDR ..................................................
Changed note 3 from "Assumes VBAT ADC measurement accuracy of 5%" in Section 5.18, Bluetooth LE
Performance: Transmitter Characteristics .......................................................................................
Changed minimum cycle time from 81.266 MHz in Table 5-6 ................................................................
Copyright © 2014–2015, Texas Instruments Incorporated
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Revision History
13
17
17
19
27
3
WL1807MOD, WL1837MOD
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
www.ti.com
3 Device Comparison
The TI WiLink 8 module offers two footprint-compatible dual-band 2.4- and 5-GHz industrial temperature
grade variants providing stand-alone Wi-Fi and Bluetooth combo connectivity. Table 3-1 compares the
features of the module variants.
Table 3-1. TI WiLink 8 Module Variants
(1)
(2)
4
DEVICE
WLAN 2.4-GHZ
SISO (1)
WLAN 2.4-GHZ
MIMO (1)
WLAN 2.4-GHZ
MRC (2)
BLUETOOTH
WLAN 5-GHZ SISO (1)
WL1837MOD
√
√
√
√
√
WL1807MOD
√
√
√
√
SISO: single input, single output; MIMO: multiple input, multiple output.
MRC: maximum ratio combining; supported at 11 g,n only.
Device Comparison
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SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
4 Terminal Configuration and Functions
PIN 48 - GND
PIN 47 - VBAT_IN
PIN 45 - GND
PIN 46 - VBAT_IN
PIN 44 - GND
PIN 42 - WL_UART_DBG
PIN 43 - BT_UART_DBG
PIN 40 - WLAN_EN
PIN 41 - BT_EN
PIN 38 - VIO
PIN 39 - GND
PIN 37 - GND
PIN 36 - EXT_32K
PIN 35 - GND
PIN 34 - GND
PIN 33 - GND
Figure 4-1 shows the pin assignments for the 100-pin MOC package.
PIN 49 - GND
PIN 32 - RF_ANT1
PIN 50 - BT_HCI_RTS
PIN 31 - GND
GND
GND
GND
GND
GND
PIN 51 - BT_HCI_CTS
GND
PIN 30 - GND
PIN 52 - BT_HCI_TX
PIN 29 - GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN 53 - BT_HCI_RX
PIN 54 - GND
PIN 28 - GND
PIN 27 - GPIO1
GND
PIN 26 - GPIO2
GND
GND
GND
PIN 55 - GND
PIN 56 - BT_AUD_IN
PIN 25 - GPIO4
PIN 57 - BT_AUD_OUT
PIN 24 - GND
PIN 23 - GND
PIN 58 - BT_AUD_FSYNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN 59 - GND
PIN 22 - RESERVED2
PIN 60 - BT_AUD_CLK
PIN 21 - RESERVED1
PIN 61 - GND
PIN 62 - RESERVED3
PIN 20 - GND
PIN 19 - GND
PIN 63 - GND
PIN 64 - RESERVED
PIN 18 - RF_ANT2
PIN 17 - GND
PIN 1 - GND
PIN 2 - GPIO11
PIN 3 - GPIO9
PIN 5 - GPIO12
PIN 4 - GPIO10
PIN 6 - WL_SDIO_CMD
PIN 7 - GND
PIN 8 - WL_SDIO_CLK
PIN 9 - GND
PIN 10 - WL_SDIO_D0
PIN 11 - WL_SDIO_D1
PIN 13 - WL_SDIO_D3
PIN 12 - WL_SDIO_D2
PIN 15 - GND
PIN 14 - WLAN_IRQ
PIN 16 - GND
Pin 2 Indicator
Figure 4-1. 100-Pin MOC Package (Bottom View)
Terminal Configuration and Functions
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WL1807MOD, WL1837MOD
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
www.ti.com
Figure 4-2 shows the recommended PCB pattern of the 100-pin MOC package.
Surround each pad with a 0.03-mm-wide
solder mask.
Recommended PCB Pattern
12.05
9.80
7.70
2.10
1.40
7.70
9.80
1.40
1.00
11.95
1.00
A
1.00
0.03 All around
1.00
0.40
0.75
0.75
0.75
0.03 All around
0.03 All around
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
1. Module size: 13.4 mm × 13.3 mm
2. Signal pad size: 0.75 mm × 0.40 mm
3. 4 x corner ground size: 0.75 mm × 0.75 mm
4. Central ground pin size: 1.00 mm × 1.00 mm
5. Pitch: 0.7 mm
Figure 4-2. Recommended PCB Pattern of 100-Pin MOC Package
Figure 4-3 shows the recommended stencil outline of the 100-pin MOC package.
Recommended Stencil
12.05
9.80
7.70
2.10
0.7
0.70
7.70
2.10
9.80
11.95
A
0.525
R0.165
0.33
0.75
0.525
Figure 4-3. Recommended Stencil Outline of 100-Pin MOC Package
6
Terminal Configuration and Functions
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4.1
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
Pin Description
Table 4-1 describes the module pins.
Table 4-1. Pin Description
PIN NAME
PIN
TYPE/ SHUTDOWN
DIR
STATE(1)
AFTER
POWER
UP(1)
VOLTAGE CONNECTIVITY(2)
LEVEL
1807
1837
DESCRIPTION
Clocks and Reset Signals
WL_SDIO_CLK_1V8
8
I
Hi-Z
EXT_32K
36
ANA
WLAN_EN
40
I
PD
BT_EN
41
I
VIO_IN
38
POW
VBAT_IN
46
VBAT_IN
Hi-Z
1.8 V
v
v
WLAN SDIO clock.
Must be driven by the
host.
–
v
v
Input sleep clock:
32.768 kHz
PD
1.8 V
v
v
Mode setting: high =
enable
PD
PD
1.8 V
x
v
Mode setting: high =
enable. If Bluetooth is
not used, connect to
ground.
PD
PD
1.8 V
v
v
Connect to 1.8-V
external VIO
POW
VBAT
v
v
Power supply input, 2.9
to 4.8 V
47
POW
VBAT
v
v
Power supply input, 2.9
to 4.8 V
GPIO11
2
I/O
PD
PD
1.8 V
v
v
Reserved for future
use. NC if not used.
GPIO9
3
I/O
PD
PD
1.8 V
v
v
Reserved for future
use. NC if not used.
GPIO10
4
I/O
PU
PU
1.8 V
v
v
Reserved for future
use. NC if not used.
GPIO12
5
I/O
PU
PU
1.8 V
v
v
Reserved for future
use. NC if not used.
RESERVED1
21
I
PD
PD
1.8 V
x
x
Reserved for future
use. NC if not used.
RESERVED2
22
I
PD
PD
1.8 V
x
x
Reserved for future
use. NC if not used.
GPIO4
25
I/O
PD
PD
1.8 V
v
v
Reserved for future
use. NC if not used.
RESERVED3
62
O
PD
PD
1.8 V
x
x
Reserved for future
use. NC if not used.
Option: External TCXO.
RESERVED
64
GND
–
v
v
Reserved for future
use. Connect to ground
if not used.
Power-Management Signals
TI Reserved
Terminal Configuration and Functions
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WL1807MOD, WL1837MOD
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
www.ti.com
Table 4-1. Pin Description (continued)
PIN NAME
PIN
TYPE/ SHUTDOWN
DIR
STATE(1)
AFTER
POWER
UP(1)
VOLTAGE CONNECTIVITY(2)
LEVEL
1807
1837
DESCRIPTION
WLAN Functional Block: Int Signals
WL_SDIO_CMD_1V8
6
I/O
Hi-Z
Hi-Z
1.8 V
v
v
WLAN SDIO
command(3)
WL_SDIO_D0_1V8
10
I/O
Hi-Z
Hi-Z
1.8 V
v
v
WLAN SDIO data bit
0(3)
WL_SDIO_D1_1V8
11
I/O
Hi-Z
Hi-Z
1.8 V
v
v
WLAN SDIO data bit
1(3)
WL_SDIO_D2_1V8
12
I/O
Hi-Z
Hi-Z
1.8 V
v
v
WLAN SDIO data bit
2(3)
WL_SDIO_D3_1V8
13
I/O
Hi-Z
PU
1.8 V
v
v
WLAN SDIO data bit 3.
Changes state to PU at
WL_EN or BT_EN
assertion for card
detects. Later disabled
by software during
initialization.(3)
WL_IRQ_1V8
14
O
PD
0
1.8 V
v
v
SDIO available,
interrupt out. Active
high. (For
WL_RS232_TX/RX
pullup is at power up.)
Set to rising edge
(active high) on power
up. The Wi-Fi interrupt
line can be configured
by the driver according
to the IRQ
configuration
(polarity/level/edge).
RF_ANT2
18
ANA
–
v
v
5G ANT diversity
TX/RX , 2.4G
Secondary antenna
MRC/MIMO only
GPIO2
26
I/O
PD
PD
1.8 V
v
v
WL_RS232_RX (when
WLAN_IRQ = 1 at
power up)
GPIO1
27
I/O
PD
PD
1.8 V
v
v
WL_RS232_TX (when
WLAN_IRQ = 1 at
power up)
RF_ANT1
32
ANA
–
v
v
5G main ANT TX/RX,
2.4G WLAN main
antenna SISO,
Bluetooth
WL_UART_DBG
42
O
1.8 V
v
v
Option: WLAN logger
8
Terminal Configuration and Functions
PU
PU
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SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
Table 4-1. Pin Description (continued)
PIN NAME
PIN
TYPE/ SHUTDOWN
DIR
STATE(1)
AFTER
POWER
UP(1)
VOLTAGE CONNECTIVITY(2)
LEVEL
1807
1837
DESCRIPTION
Bluetooth Functional Block: Int Signals
BT_UART_DBG
43
O
PU
PU
1.8 V
x
v
Option: Bluetooth
logger
BT_HCI_RTS_1V8
50
O
PU
PU
1.8 V
x
v
UART RTS to host. NC
if not used.
BT_HCI_CTS_1V8
51
I
PU
PU
1.8 V
x
v
UART CTS from host.
NC if not used.
BT_HCI_TX_1V8
52
O
PU
PU
1.8 V
x
v
UART TX to host. NC if
not used.
BT_HCI_RX_1V8
53
I
PU
PU
1.8 V
x
v
UART RX from host.
NC if not used.
BT_AUD_IN
56
I
PD
PD
1.8 V
x
v
Bluetooth PCM/I2S
bus. Data in. NC if not
used.
BT_AUD_OUT
57
O
PD
PD
1.8 V
x
v
Bluetooth PCM/I2S
bus. Data out. NC if not
used.
BT_AUD_FSYNC
58
I/O
PD
PD
1.8 V
x
v
Bluetooth PCM/I2S
bus. Frame sync. NC if
not used.
BT_AUD_CLK
60
I/O
PD
PD
1.8 V
x
v
Bluetooth PCM/I2S
bus. NC if not used.
1, 7, 9, 15,
16, 17, 19,
20, 23, 24,
28, 29, 30,
31, 33, 34,
35, 37, 39,
44, 45, 48,
49, 54, 55,
59, 61, 63,
G1-G36
GND
–
v
v
Ground Pins
GND
(1) PU = pullup; PD = pulldown.
(2) v = connect; x = no connect.
(3) Host must provide PU using a 10-K resistor for all non-CLK SDIO signals.
Terminal Configuration and Functions
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www.ti.com
5 Specifications
All specifications are measured at the module pins using the TI WL1837MODCOM8I evaluation board. All
measurements are performed with VBAT = 3.7 V, VIO = 1.8 V, 25°C for typical values with matched RF
antennas, unless otherwise indicated.
NOTE
For level-shifting I/Os with the TI WL18x7MOD, see Level Shifting WL18xx I/Os Application
Report (SWRA448).
NOTE
This device as presently configured has been granted US Federal Communications
Commission (FCC) equipment authorization (reference number Z64-WL18DBMOD). Any
modifications to the device software or configuration, including but not limited to the init files,
can cause device performance to vary beyond the scope of the currently referenced FCC
authorization. Accordingly, if any user modifications are sought to be made to the device
software or configuration, the user may be required to independently seek fresh FCC and
other regulatory authorizations as relevant before distributing or marketing the devices or
products incorporating the same.
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VALUE
UNIT
4.8 (2)
V
VIO
–0.5 to 2.1
V
Input voltage to analog pins
–0.5 to 2.1
V
Input voltage limits (CLK_IN)
–0.5 to VDD_IO
V
Input voltage to all other pins
–0.5 to (VDD_IO + 0.5 V)
V
VBAT
Operating ambient temperature range
–40 to 85
(3)
°C
Storage temperature, Tstg
–40 to +85
°C
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.8 V cumulative to 2.33 years, including charging dips and peaks
Operating free-air temperature range at which the device can operate reliably for 15K cumulative active TX power-on hours (assuming a
maximum junction temperature of (Tj) of 125°C). Section 5.3, Power-On Hours (POH), describes the correlation between Tj and PoH. In
the WL18xx system, a control mechanism automatically ensures Tj < 125°C. Whenever Tj approaches the threshold, this mechanism
controls the transmitter patterns.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
(1)
10
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Power-On Hours (POH) (1)
OPERATING JUNCTION TEMPERATURE (°C)
POH
125
15,000
120
20,000
115
27,000
This information is provided solely to give the customer an estimation of the POH under certain specified conditions and does not extend
the warranty for the device under TI’s Standard Terms and Conditions.
Specifications
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Power-On Hours (POH)(1) (continued)
5.4
OPERATING JUNCTION TEMPERATURE (°C)
POH
110
37,000
105
50,000
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VBAT
(1)
MIN
TYP
2.9
3.7
4.8
V
1.62
1.8
1.95
V
0.65 x VDD_IO
VDD_IO
V
DC supply range for all modes
VIO
1.8-V I/O ring power supply voltage
VIH
I/O high-level input voltage
VIL
I/O low-level input voltage
VIH_EN
Enable inputs high-level input voltage
VIL_EN
Enable inputs low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Tr,Tf
Input transitions time Tr,Tf from 10%
to 90% (digital I/O) (2)
Tr
Output rise time from 10% to 90%
(digital pins) (2)
Tf
Output fall time from 10% to 90%
(digital pins) (2)
(1)
(2)
5.5
UNIT
0
0.35 × VDD_IO
V
1.365
VDD_IO
V
0
0.4
V
@ 4 mA
VDD_IO –0.45
VDD_IO
V
@ 4 mA
0
0.45
V
1
10
ns
CL < 25 pF
5.3
ns
CL < 25 pF
4.9
ns
Ambient operating temperature
Maximum power
dissipation
MAX
85
ºC
WLAN operation
–40
2.8
W
Bluetooth operation
0.2
4.8 V is applicable only for 2.33 years (30% of the time). Otherwise, maximum VBAT must not exceed 4.3 V.
Applies to all digital lines except SDIO, UART, I2C, PCM and slow clock lines
External Digital Slow Clock Requirements
The supported digital slow clock is 32.768 kHz digital (square wave). All core functions share a single input.
PARAMETER
CONDITION
SYMBOL
MIN
Input slow clock frequency
Input slow clock accuracy (Initial + temp +
aging)
WLAN, Bluetooth
Input transition time Tr,Tf (10% to 90%)
Tr,Tf
Frequency input duty cycle
Input voltage limits
TYP
MAX
UNIT
±250
ppm
200
ns
32768
15%
Square wave, DCcoupled
50%
Hz
85%
VIH
0.65 x VDD_IO
VDD_IO
VIL
0
0.35 x VDD_IO
Input impedance
1
MΩ
Input capacitance
5.6
Vpeak
5
pF
Thermal Characteristics for MOC 100-Pin Package
AIR FLOW
NAME
(1)
(2)
(3)
DESCRIPTION
(2)
(°C/W) (1)
θJA
Junction to free air
θJB
Junction to board
6.06
θJC
Junction to case (3)
5.13
16.6
°C/W = degrees Celsius per watt
According to the JEDEC EIA/JESD 51 document
Modeled using the JEDEC 2s2p thermal test board with 36 thermal vias
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5.7
www.ti.com
WLAN Performance: 2.4-GHz Receiver Characteristics
over operating free-air temperature range (unless otherwise noted). All RF and performance numbers are aligned to the
module pin.
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
2484
MHz
RF_ANT1 pin 2.4-GHz SISO
Operation frequency range
2412
Sensitivity: 20-MHz bandwidth. At < 10% PER limit
1 Mbps DSSS
–95.0
2 Mbps DSSS
–92.0
5.5 Mbps CCK
–89.2
11 Mbps CCK
–86.3
6 Mbps OFDM
–91.0
9 Mbps OFDM
–89.0
12 Mbps OFDM
–88.0
18 Mbps OFDM
–85.5
24 Mbps OFDM
–82.5
36 Mbps OFDM
–79.0
48 Mbps OFDM
–74.0
54 Mbps OFDM
–72.5
MCS0 MM 4K
–89.3
MCS1 MM 4K
–86.5
MCS2 MM 4K
–84.5
MCS3 MM 4K
–81.5
MCS4 MM 4K
–78.0
MCS5 MM 4K
–73.5
MCS6 MM 4K
–71.5
MCS7 MM 4K
–70.0
MCS0 MM 4K 40 MHz
–86.0
MCS7 MM 4K 40 MHz
–66.3
MCS0 MM 4K MRC
–91.0
MCS7 MM 4K MRC
–73.0
MCS13 MM 4K
–70.0
MCS14 MM 4K
–69.0
MCS15 MM 4K
Maximum input level
Adjacent channel rejection: Sensitivity level +3 dB for
OFDM; Sensitivity level +6 dB for 11b
–68.3
OFDM
–20.0
–10.0
CCK
–10.0
–6.0
–1.0
DSSS
–4.0
2 Mbps DSSS
42.0
11 Mbps CCK
38.0
54 Mbps OFDM
2.0
RX leakage
dB
dBm
1.0%
RSSI accuracy
Specifications
dBm
–70
PER floor
12
dBm
±3
dB
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5.8
SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
WLAN Performance: 2.4-GHz Transmitter Power
over operating free-air temperature range (unless otherwise noted). All RF and performance numbers are aligned to the
module pin.
CONDITION (1)
PARAMETER
MIN
TYP
MAX
UNIT
RF_ANT1 Pin 2.4-GHz SISO
Output Power: Maximum RMS output power measured
at 1 dB from IEEE spectral mask or EVM (2)
1 Mbps DSSS
17.3
2 Mbps DSSS
17.3
5.5 Mbps CCK
17.3
11 Mbps CCK
17.3
6 Mbps OFDM
17.1
9 Mbps OFDM
17.1
12 Mbps OFDM
17.1
18 Mbps OFDM
17.1
24 Mbps OFDM
16.2
36 Mbps OFDM
15.3
48 Mbps OFDM
14.6
54 Mbps OFDM
13.8
MCS0 MM
16.1
MCS1 MM
16.1
MCS2 MM
16.1
MCS3 MM
16.1
MCS4 MM
15.3
MCS5 MM
14.6
MCS6 MM
13.8
MCS7 MM (3)
12.6
MCS0 MM 40 MHz
14.8
MCS7 MM 40 MHz
dBm
11.3
RF_ANT1 + RF_ANT2 MIMO
MCS12 (WL18x5)
18.5
MCS13 (WL18x5)
17.4
MCS14 (WL18x5)
14.5
MCS15 (WL18x5)
13.4
dBm
RF_ANT1 + RF_ANT2
Operation frequency range
2412
Return loss
Reference input impedance
(1)
(2)
(3)
2484
MHz
–10.0
dB
50.0
Ω
Maximum transmitter power (TP) degradation of up to 30% is expected, starting from 80°C ambient temperature on MIMO operation
Regulatory constraints limit TI module output power to the following:
• Channel 14 is used only in Japan; to keep the channel spectral shaping requirement, the power is limited:14.5 dBm.
• Channels 1, 11 @ OFDM legacy and HT 20-MHz rates: 12 dBm
• Channels 1, 11 @ HT 40-MHz rates: 10 dBm
• Channel 7 @ HT 40-MHz lower rates: 10 dBm
• Channel 5 @ HT 40-MHz upper rates: 10 dBm
• All 11B rates are limited to 16 dBm to comply with the ETSI PSD 10 dBm/MHz limit.
• All OFDM rates are limited to 16.5 dBm to comply with the ETSI EIRP 20 dBm limit.
• For clarification regarding power limitation, see the WL18xx .INI File Application Report (SWRU422).
To ensure compliance with the EVM conditions specified in the PHY chapter of IEEE Std 802.11™ – 2012:
• MCS7 20 MHz channel 12 output power is 2 dB lower than the typical value.
• MCS7 20 MHz channel 8 output power is 1 dB lower than the typical value.
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5.9
www.ti.com
WLAN Performance: 5-GHz Receiver Characteristics
over operating free-air temperature range (unless otherwise noted). All RF and performance numbers are aligned to the
module pin.
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
5825.0
MHz
RF_ANT1 or RF_ANT2
Operation frequency range
Sensitivity: 20-MHz bandwidth. At < 10%
PER limit
4910.0
6 Mbps OFDM 1K
–92.5
9 Mbps OFDM 1K
–90.5
12 Mbps OFDM 1K
–90.0
18 Mbps OFDM 1K
–87.5
24 Mbps OFDM 1K
–84.5
36 Mbps OFDM 1K
–81.0
48 Mbps OFDM 1K
–76.5
54 Mbps OFDM 1K
–74.6
MCS0 MM 4K
–91.4
MCS1 MM 4K
–88.0
MCS2 MM 4K
–86.0
MCS3 MM 4K
–83.0
MCS4 MM 4K
–79.8
MCS5 MM 4K
–75.5
MCS6 MM 4K
–74.0
MCS7 MM 4K
–72.4
MCS0 MM 4K 40 MHz
–88.5
MCS7 MM 4K 40 MHz
Maximum input level
Adjacent channel rejection sensitivity +3 dB
OFDM
OFDM54
–69.3
–30.0
–15.0
dBm
–52.0
PER floor
1.0%
RSSI accuracy
Specifications
dBm
2.0
RX LO leakage
14
dBm
±3
dBm
2.0%
dB
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SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
5.10 WLAN Performance: 5-GHz Transmitter Power (1)
over operating free-air temperature range (unless otherwise noted)
CONDITION (2)
PARAMETER
MIN
TYP
MAX
UNIT
5825
MHz
RF_ANT1 or RF_ANT2
Operation frequency range
4920
RMS output power complies with IEEE mask
and EVM requirements (3)
6 Mbps OFDM
18.0
9 Mbps OFDM
18.0
12 Mbps OFDM
18.0
18 Mbps OFDM
18.0
24 Mbps OFDM
17.4
36 Mbps OFDM
16.5
48 Mbps OFDM
15.8
54 Mbps OFDM
14.5
MCS0 MM
18.0
MCS1 MM 4K
18.0
MCS2 MM 4K
18.0
MCS3 MM 4K
18.0
MCS4 MM 4K
16.5
MCS5 MM 4K
15.8
MCS6 MM 4K
14.5
MCS7 MM 4K
13.0
MCS0 MM 40 MHz
16.5
MCS7 MM 40 MHz
12.0
Output power resolution
0.125
dB
Return loss
–10.0
dB
50.0
Ω
Reference input impedance
(1)
(2)
(3)
All RF and performance numbers are aligned to the module pin.
Maximum TP degradation of up to 30% is expected, starting from 80°C ambient temperature on 5-GHz TX operation.
For further clarification regarding power limitation, see the INI Guide.
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5.11 WLAN Performance: Currents (1)
over operating free-air temperature range (unless otherwise noted)
SPECIFICATION ITEMS
TYP (AVG) – 25°C
Low-power mode (LPM) 2.4-GHz RX SISO20 single chain
49
2.4 GHz RX search SISO20
58
2.4-GHz RX search MIMO20
74
2.4-GHz RX search SISO40
63
Receiver
Transmitter (2)
(1)
(2)
2.4-GHz RX 20 M SISO 11 CCK
60
2.4-GHz RX 20 M SISO 6 OFDM
61
2.4-GHz RX 20 M SISO MCS7
69
2.4-GHz RX 20 M MRC 1 DSSS
74
2.4-GHz RX 20 M MRC 6 OFDM
81
2.4-GHz RX 20 M MRC 54 OFDM
85
2.4-GHz RX 40 MHz MCS7
81
5-GHz RX 20 MHz OFDM6
68
5-GHz RX 20 MHz MCS7
77
5-GHz RX 40 MHz MCS7
85
2.4-GHz TX 20 M SISO 6 OFDM
285
2.4-GHz TX 20 M SISO 11 CCK
283
2.4-GHz TX 20 M SISO 54 OFDM
247
2.4-GHz TX 20 M SISO MCS7
238
2.4-GHz TX 20 M MIMO MCS15
510
2.4-GHz TX 40 M SISO MCS7
243
5-GHz TX 20 M SISO 6 OFDM
366
5-GHz TX 20 M SISO 54 OFDM
329
5-GHz TX 20 M SISO MCS7
324
5-GHz TX 40 M SISO MCS7
332
UNITS
mA
mA
All RF and performance numbers are aligned to the module pin.
Numbers reflect the typical current consumption at maximum output power per rate.
5.12 Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
Bluetooth BR, EDR operation
frequency range
MIN
Bluetooth BR, EDR channel
spacing
Bluetooth BR, EDR input
impedance
Bluetooth BR, EDR
sensitivity (2)
dirty TX on
Bluetooth EDR BER floor at
sensitivity + 10 dB
Dirty TX off (for 1,600,000
bits)
MHz
50
Ω
–92.2
–91.7
dBm
–84.7
EDR2
1e-6
EDR3
1e-6
–15.0
Bluetooth BR intermodulation Level of interferers for n = 3, 4, and 5
–36.0
16
UNIT
2480
MHz
EDR2, BER = 0.01%
EDR3, BER = 0.01%
MAX
1
BR, BER = 0.1%
BR, BER = 0.1%
Bluetooth BR, EDR maximum
EDR2, BER = 0.1%
usable input power
EDR3, BER = 0.1%
(1)
(2)
TYP
2402
–5.0
dBm
–15.0
–30.0
dBm
All RF and performance numbers are aligned to the module pin.
Sensitivity degradation up to –3 dB may occur due to fast clock harmonics with dirty TX on.
Specifications
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SWRS170H – AUGUST 2014 – REVISED OCTOBER 2015
Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals(1) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN
TYP
MAX
BR, co-channel
EDR, co-channel
EDR2
12
EDR3
20
BR, adjacent ±1 MHz
Bluetooth BR, EDR C/I
performance
Numbers show wanted
signal-to-interfering-signal
ratio. Smaller numbers
indicate better C/I
performances (Image
frequency = –1 MHz)
UNIT
10
–3.0
EDR, adjacent ±1 MHz,
(image)
EDR2
–3.0
EDR3
2.0
BR, adjacent +2 MHz
–33.0
EDR, adjacent +2 MHz
EDR2
–33.0
EDR3
–28.0
BR, adjacent –2 MHz
dB
–20.0
EDR, adjacent –2 MHz
EDR2
–20.0
EDR3
–13.0
BR, adjacent ≥Ι±3Ι MHz
–42.0
EDR, adjacent ≥Ι±3Ι MHz
EDR2
–42.0
EDR3
–36.0
Bluetooth BR, EDR RF return
loss
–10.0
dB
5.13 Bluetooth Performance: Transmitter, BR (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
11.7
VBAT < 3 V (3)
7.2
VBAT ≥ 3 V
BR RF output power (2)
TYP
(3)
BR gain control range
MAX
dBm
30.0
BR power control step
UNIT
dB
5.0
dB
BR adjacent channel power |M-N| = 2
–43.0
dBm
BR adjacent channel power |M-N| > 2
–48.0
dBm
(1)
(2)
(3)
All RF and performance numbers are aligned to the module pin.
Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
VBAT is measured with an on-chip ADC that has an accuracy error of up to 5%.
5.14 Bluetooth Performance: Transmitter, EDR (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
EDR output power (2)
MIN
TYP
VBAT ≥ 3 V (3)
7.2
VBAT < 3 V (3)
5.2
MAX
UNIT
dBm
EDR gain control range
30
dB
EDR power control step
5
dB
EDR adjacent channel power |M-N| = 1
–36
dBc
EDR adjacent channel power |M-N| = 2
–30
dBm
EDR adjacent channel power |M-N| > 2
–42
dBm
(1)
(2)
(3)
All RF and performance numbers are aligned to the module pin.
Values reflect default maximum power. Maximum power can be changed using a VS command.
VBAT is measured with an on-chip ADC that has an accuracy error of up to 5%.
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5.15 Bluetooth Performance: Modulation, BR (1)
over operating free-air temperature range (unless otherwise noted)
CONDITION (2)
CHARACTERISTICS
MIN
BR –20 dB bandwidth
BR modulation characteristics
BR carrier frequency drift
MAX
UNIT
925
995
kHz
∆f1avg
Mod data = 4 1s, 4
0s:
111100001111...
145
160
170
kHz
∆f2max ≥ limit for
at least 99.9% of
all Δf2max
Mod data =
1010101...
120
130
∆f2avg, ∆f1avg
85%
88%
One-slot packet
–25
25
kHz
Three- and five-slot
packet
–35
35
kHz
15
kHz/50 µs
±75
kHz
BR drift rate
lfk+5 – fkl , k =
0 …. max
BR initial carrier frequency tolerance (3)
f0–fTX
(1)
(2)
(3)
TYP
±75
kHz
All RF and performance numbers are aligned to the module pin.
Performance values reflect maximum power.
Numbers include XTAL frequency drift over temperature and aging.
5.16 Bluetooth Performance: Modulation, EDR (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER (2)
CONDITION
EDR carrier frequency stability
EDR initial carrier frequency tolerance
TYP
–5
(3)
EDR RMS DEVM
EDR 99% DEVM
EDR peak DEVM
(1)
(2)
(3)
MIN
±75
MAX
UNIT
5
kHz
±75
kHz
EDR2
4%
15%
EDR3
4%
10%
EDR2
30%
EDR3
20%
EDR2
9%
25%
EDR3
9%
18%
All RF and performance numbers are aligned to the module pin.
Performance values reflect maximum power.
Numbers include XTAL frequency drift over temperature and aging.
5.17 Bluetooth LE Performance: Receiver Characteristics – In-Band Signals (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION (2)
Bluetooth LE operation frequency range
MIN
TYP
2402
MAX
UNIT
2480
MHz
Bluetooth LE channel spacing
2
MHz
Bluetooth LE input impedance
50
Ω
Bluetooth LE sensitivity (3)
Dirty TX on
–92.2
Bluetooth LE maximum usable input power
Bluetooth LE intermodulation characteristics
(1)
(2)
(3)
18
–5
Level of interferers.
For n = 3, 4, 5
–36
dBm
dBm
–30
dBm
All RF and performance numbers are aligned to the module pin.
BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to the Bluetooth LE test specification.
Sensitivity degradation of up to –3 dB can occur due to fast clock harmonics.
Specifications
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Bluetooth LE Performance: Receiver Characteristics – In-Band Signals(1) (continued)
over operating free-air temperature range (unless otherwise noted)
CONDITION (2)
PARAMETER
MIN
TYP
LE, co-channel
Bluetooth LE C/I performance.
Note: Numbers show wanted signal-tointerfering-signal ratio. Smaller numbers
indicate better C/I performance.
Image = –1 MHz
MAX
UNIT
12
LE, adjacent ±1 MHz
0
LE, adjacent +2 MHz
–38
LE, adjacent –2 MHz
–15
LE, adjacent ≥ |±3|MHz
–40
dB
5.18 Bluetooth LE Performance: Transmitter Characteristics (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
Bluetooth LE RF output power (2)
TYP
VBAT ≥ 3 V (3)
7.0
VBAT < 3 V (3)
7.0
MAX
UNIT
dBm
Bluetooth LE adjacent channel power |M-N| = 2
–51.0
dBm
Bluetooth LE adjacent channel power |M-N| > 2
–54.0
dBm
(1)
(2)
(3)
All RF and performance numbers are aligned to the module pin.
Bluetooth LE power is restricted to comply with the ETSI 10-dBm EIRP limit requirement.
VBAT is measured with an on-chip ADC that has an accuracy error of up to 5%.
5.19 Bluetooth LE Performance: Modulation Characteristics (1)
over operating free-air temperature range (unless otherwise noted)
CONDITION (2)
CHARACTERISTICS
Bluetooth LE modulation
characteristics
∆f1avg
Mod data = 4 1s, 4 0s:
111100001111...
∆f2max ≥ limit for at
least 99.9% of all
Δf2max
Mod data = 1010101...
∆f2avg, ∆f1avg
Bluetooth LE carrier frequency
drift
lf0 – fnl , n = 2,3 …. K
Bluetooth LE drift rate
lf1 – f0l and lfn – fn-5l , n = 6,7…. K
Bluetooth LE initial carrier
frequency tolerance (3)
fn – fTX
(1)
(2)
(3)
MIN
TYP
MAX
240
250
260
195
215
85%
90%
UNIT
kHz
–25
±75
25
kHz
15
kHz/50 µs
±75
kHz
All RF and performance numbers are aligned to the module pin.
Performance values reflect maximum power.
Numbers include XTAL frequency drift over temperature and aging.
5.20 Bluetooth BR and EDR Dynamic Currents
Current is measured at output power as follows: BR at 11.7 dBm; EDR at 7.2 dBm.
USE CASE (1)
(2)
TYP
UNIT
BR voice HV3 + sniff
11.6
mA
EDR voice 2-EV3 no retransmission + sniff
5.9
mA
Sniff 1 attempt 1.28 s
178.0
µA
EDR A2DP EDR2 (master). SBC high quality – 345 kbps
10.4
mA
EDR A2DP EDR2 (master). MP3 high quality – 192 kbps
7.5
mA
(3) (4)
18.0
mA
Full throughput BR ACL TX: TX-DH5 (4)
50.0
mA
Full throughput EDR ACL TX: TX-2DH5 (4)
33.0
mA
Full throughput ACL RX: RX-2DH5
(1)
(2)
(3)
(4)
The role of Bluetooth in all scenarios except A2DP is slave.
CL1P5 PA is connected to VBAT, 3.7 V.
ACL RX has the same current in all modulations.
Full throughput assumes data transfer in one direction.
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Bluetooth BR and EDR Dynamic Currents (continued)
Current is measured at output power as follows: BR at 11.7 dBm; EDR at 7.2 dBm.
USE CASE (1)
(2)
TYP
UNIT
Page scan or inquiry scan (scan interval is 1.28 s or 11.25 ms, respectively)
253.0
µA
Page scan and inquiry scan (scan interval is 1.28 s and 2.56 s, respectively)
332.0
µA
TYP
UNIT
131
µA
5.21 Bluetooth LE Currents
All current measured at output power of 6.5 dBm
USE CASE (1)
Advertising, not connectable
Advertising, discoverable
(2)
(2)
143
µA
Scanning (3)
266
µA
Connected, master role, 1.28-s connect interval (4)
124
µA
132
µA
Connected, slave role, 1.28-s connect interval
(1)
(2)
(3)
(4)
(4)
CL1p% PA is connected to VBAT, 3.7 V.
Advertising in all three channels, 1.28-s advertising interval, 15 bytes advertise data
Listening to a single frequency per window, 1.28-s scan interval, 11.25-ms scan window
Zero slave connection latency, empty TX and RX LL packets
5.22 Timing and Switching Characteristics
5.22.1 Power Management
5.22.1.1 Block Diagram – Internal DC2DCs
The device incorporates three internal DC2DCs (switched-mode power supplies) to provide efficient
internal supplies, derived from VBAT.
WL18xx Top Level
VIO_IN
VIO
VBAT
VBAT
VBAT_IN_MAIN_DC2DC
VBAT
VBAT_IN_PA_DC2DC
MAIN_DC2DC_OUT
LDO_IN_DIG
SW
FB
Main DC2DC
PA
DC2DC
VDD_DIG
PA_DC2DC_OUT
FB
FB_IN_PA_DC2DC
2.2 – 2.7 V
1.8 V
DIG_DC2DC_OUT
SW
SW
FB
Digital DC2DC
1V
Figure 5-1. Internal DC2DCs
5.22.2 Power-Up and Shut-Down States
The correct power-up and shut-down sequences must be followed to avoid damage to the device.
While VBAT or VIO or both are deasserted, no signals should be driven to the device. The only exception is
the slow clock that is a fail-safe I/O.
While VBAT, VIO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in
SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC2DCs, clocks, and LDOs are
disabled.
To perform the correct power-up sequence, assert (high) WL_EN. The internal DC2DCs, LDOs, and clock
start to ramp and stabilize. Stable slow clock, VIO, and VBAT are prerequisites to the assertion of one of the
enable signals.
20
Specifications
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To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device
(VBAT, VIO, and slow clock) are still stable and available. The supplies to the chip (VBAT and VIO) can be
deasserted only after both enable signals are deasserted (low).
Figure 5-2 shows the general power scheme for the module, including the power-down sequence.
VBAT
1
VIO
5
SCLK (32 KHz)
5
>10 µs
2
>10 µs
4
3
WL EN
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
> 60 µs
1. Either VBAT or VIO can come up first.
2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times
when the EN is active.
3. At least 60 µs is required between two successive device enables. The device is assumed to be in
shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.
4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered. (Order of supply turn off
after EN shutdown is immaterial)
5. SCLK - Fail safe I/O
Figure 5-2. Power-Up System
5.22.3 Chip Top-level Power-Up Sequence
Figure 5-3 shows the top-level power-up sequence for the chip.
VBAT / VIO
input
SLOWCLK
input
WL_EN
input
4.5 ms delay
Main 1V8 DC2DC
DIG DC2DC
SRAM LDO
Top RESETZ
TCXO_CLK_REQ
output
Internal power stable = 5 ms
Figure 5-3. Chip Top-Level Power-Up Sequence
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5.22.4 WLAN Power-Up Sequence
Figure 5-4 shows the WLAN power-up sequence.
VBAT / VIO
input
SLOWCLK
input
WL_EN
input
TCXO_CLK_REQ
output
TXCO_LDO
output
TCXO
input
SDIO_CLK
input
Indicates completion of firmware download
and internal initialization
NLCP: trigger at rising edge
WLAN_IRQ
output
NLCP
Wake-up time
WLAN_IRQ
output
Indicates completion of firmware download
and internal initialization
MCP
Wake-up time
MCP: trigger at low level
Host configures device to
reverse WLAN_IRQ polarity
Figure 5-4. WLAN Power-Up Sequence
5.22.5 Bluetooth-Bluetooth LE Power-Up Sequence
Figure 5-5 shows the Bluetooth-Bluetooth LE power-up sequence.
Completion of Bluetooth firmware initialztion.
100 ms maximum
Figure 5-5. Bluetooth-Bluetooth LE Power-Up Sequence
22
Specifications
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5.22.6 WLAN SDIO Transport Layer
The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses
an SDIO interface and supports a maximum clock rate of 50 MHz.
The device SDIO also supports the following features of the SDIO V3 specification:
• 4-bit data bus
• Synchronous and asynchronous in-band interrupt
• Default and high-speed (HS, 50 MHz) timing
• Sleep and wake commands
5.22.6.1 SDIO Timing Specifications
Figure 5-6 and Figure 5-7 show the SDIO switching characteristics over recommended operating
conditions and with the default rate for input and output.
tWH
tWL
VDD
VIH
VIH
VIH
Clock Input
VIL
VSS
VIL
tTHL
tTLH
tISU
VDD
tIH
VIH
Data Input
Not Valid
VIH
Valid
VIL
Not Valid
VIL
VSS
Figure 5-6. SDIO Default Input Timing
tTHL
VDD
tWH
tWL
VIH
VIH
VIH
Clock Input
VIL
VIL
VSS
tTLH
tODLY(max)
tODLY(min)
VDD
VOH
VOH
Data Output
Valid
Not Valid
Not Valid
VOL
VOL
VSS
Figure 5-7. SDIO Default Output Timing
Table 5-1 lists the SDIO default timing characteristics.
Table 5-1. SDIO Default Timing Characteristics (1)
PARAMETER (2)
MIN
MAX
UNIT
fclock
Clock frequency, CLK
0.0
26.0
MHz
DC
Low, high duty cycle
40.0%
60.0%
tTLH
Rise time, CLK
10.0
ns
tTHL
Fall time, CLK
10.0
ns
tISU
Setup time, input valid before CLK ↑
3.0
tIH
Hold time, input valid after CLK ↑
2.0
tODLY
Delay time, CLK ↓ to output valid
7.0
Cl
Capacitive load on outputs
(1)
(2)
ns
ns
10.0
ns
15.0
pF
To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.
Parameter values reflect maximum clock frequency.
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5.22.6.2 SDIO Switching Characteristics – High Rate
Figure 5-8 and Figure 5-9 show the parameters for maximum clock frequency.
tWH
tWL
VDD
VIH
VIH
Clock Input
VIL
VSS
VIL
tTHL
tTLH
tISU
VDD
tIH
VIH
Data Input
VIH
50% VDD
Not Valid
VIH
Valid
VIL
Not Valid
VIL
VSS
Figure 5-8. SDIO HS Input Timing
tWL
tTHL
VDD
tWH
VIH
Clock Input
VIH
VIH
50% VDD
50% VDD
VIL
VIL
VSS
tTLH
tODLY(max)
VDD
tOH(min)
VOH
Data Output
VOH
Valid
Not Valid
VOL
Not Valid
VOL
VSS
Figure 5-9. SDIO HS Output Timing
Table 5-2 lists the SDIO high-rate timing characteristics.
Table 5-2. SDIO HS Timing Characteristics
PARAMETER
MIN
MAX
UNIT
fclock
Clock frequency, CLK
DC
Low, high duty cycle
0.0
52.0
40.0%
60.0%
MHz
tTLH
Rise time, CLK
tTHL
Fall time, CLK
tISU
Setup time, input valid before CLK ↑
3.0
ns
tIH
Hold time, input valid after CLK ↑
2.0
ns
tODLY
Delay time, CLK ↑ to output valid
7.0
Cl
Capacitive load on outputs
3.0
ns
3.0
ns
10.0
ns
10.0
pF
5.22.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
The device includes a UART module dedicated to the Bluetooth shared-transport, host controller interface
(HCI) transport layer. The HCI transports commands, events, and ACL between the Bluetooth device and
its host using HCI data packets acting as a shared transport for all functional blocks except WLAN.
space
WLAN
SHARED HCI FOR ALL FUNCTIONAL BLOCKS EXCEPT WLAN
BLUETOOTH VOICE-AUDIO
WLAN HS SDIO
Over UART
Bluetooth PCM
24
Specifications
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The HCI UART supports most baud rates (including all PC rates) for all fast-clock frequencies up to a
maximum of 4 Mbps. After power up, the baud rate is set for 115.2 Kbps, regardless of the fast-clock
frequency. The baud rate can then be changed using a VS command. The device responds with a
Command Complete Event (still at 115.2 Kbps), after which the baud rate change occurs.
HCI hardware includes the following features:
• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
• Receiver-transmitter underflow detection
• CTS, RTS hardware flow control
• 4 wire (H4)
Table 5-3 lists the UART default settings.
Table 5-3. UART Default Setting
PARAMETER
VALUE
Bit rate
115.2 Kbps
Data length
8 bits
Stop-bit
1
Parity
None
5.22.7.1 UART 4-Wire Interface – H4
The interface includes four signals:
• TXD
• RXD
• CTS
• RTS
Flow control between the host and the device is byte-wise by hardware.
When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS
signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops
transmitting on the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device
finishes transmitting the byte and stops the transmission.
Figure 5-10 shows the UART timing.
_
_
Figure 5-10. UART Timing Diagram
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Table 5-4 lists the UART timing characteristics.
Table 5-4. UART Timing Characteristics
PARAMETER
CONDITION
SYMBOL
MIN
Baud rate
MAX
UNIT
37.5
TYP
4364
Kbps
Baud rate accuracy per byte
Receive-transmit
–2.5%
+1.5%
Baud rate accuracy per bit
Receive-transmit
–12.5%
+12.5%
CTS low to TX_DATA on
t3
CTS high to TX_DATA off
Hardware flow control
CTS high pulse width
RTS low to RX_DATA on
RTS high to RX_DATA off
0.0
2.0
t4
Interrupt set to 1/4 FIFO
µs
1.0
t6
1.0
t1
0.0
Byte
Bit
2.0
t2
µs
16.0
Bytes
Figure 5-11 shows the UART data frame.
tb
STR
TX
STR-Start-bit;
D0
D1
D2
Dn
D0..Dn - Data bits (LSB first);
PAR
STP
PAR - Parity bit (if used); STP - Stop-bit
Figure 5-11. UART Data Frame
5.22.8 Bluetooth Codec-PCM (Audio) Timing Specifications
Figure 5-12 shows the Bluetooth codec-PCM (audio) timing diagram.
tW
tCLK
tis
tW
tih
top
Figure 5-12. Bluetooth Codec-PCM (Audio) Master Timing Diagram
26
Specifications
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Table 5-5 lists the Bluetooth codec-PCM master timing characteristics.
Table 5-5. Bluetooth Codec-PCM Master Timing Characteristics
MIN
MAX
Cycle time
PARAMETER
SYMBOL
Tclk
162.76 (6.144 MHz)
15625 (64 kHz)
High or low pulse width
Tw
35% of Tclk min
AUD_IN setup time
tis
10.6
AUD_IN hold time
tih
0
AUD_OUT propagation time
top
0
15
FSYNC_OUT propagation time
top
0
15
Capacitive loading on outputs
Cl
40
UNIT
ns
pF
Table 5-6 lists the Bluetooth codec-PCM slave timing characteristics.
Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics
PARAMETER
SYMBOL
MIN
Cycle time
Tclk
81.38 (12.288 MHz)
High or low pulse width
Tw
35% of Tclk min
AUD_IN setup time
tis
5
AUD_IN hold time
tih
0
AUD_FSYNC setup time
tis
5
AUD_FSYNC hold time
tih
0
AUD_OUT propagation time
top
0
Capacitive loading on outputs
Cl
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MAX
UNIT
ns
19
40
pF
Specifications
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6 Detailed Description
The WiLink 8 module is a self-contained connectivity solution based on WiLink 8 connectivity. As the
eighth-generation connectivity combo chip from TI, the WiLink 8 module is based on proven technology.
Figure 6-1 shows a high-level view of the WL1837MOD variant.
VBAT
32 KHz
XTAL
Antenna 1
WiFi/BT
TI Sitara Processor
running Linux or
Android
VIO
WPA Supplicant &
WiFi Driver
Bluetooth
Stack &Profiles
32KHz
Antenna 2
WiFi
(Optional)
WL18XXMOD
WL1837MOD
Enable
WiFi
SDIO
UART Driver
SDIO Driver
BT
UART
Figure 6-1. WL1837MOD High-Level System Diagram
Table 6-1 through Table 6-3 list performance parameters along with shutdown and sleep currents.
Table 6-1. WLAN Performance Parameters
WLAN (1)
SPECIFICATION (TYP)
Maximum TX power, 5 GHz (OFDM6)
CONDITIONS
18 dBm
6 Mbps OFDM
Maximum TX power, 2.4 GHz (1DSSS)
16.5 dBm
1 Mbps DSSS
Minimum sensitivity, 5 GHz (OFDM6)
–92.5dBm
6 Mbps OFDM
Minimum sensitivity, 2.4GHz (1DSSS)
–95 dBm
1 Mbps DSSS
Sleep current
160 µA
Leakage, firmware retained
Connected IDLE
750 µA
No traffic IDLE connect
RX search
58 mA
2.4GHz SISO 20
RX current (SISO20)
69 mA
MCS7, 2.4 GHz
RX current (SISO20)
77 mA
MCS7, 5 GHz
TX current (SISO20)
238 mA
MCS7, 2.4 GHz
TX current (SISO20)
324 mA
MCS7, 5 GHz
Maximum peak current consumption during calibration (2)
850 mA
(1)
(2)
System design power scheme must comply with both peak and average TX bursts.
Peak current VBAT can hit 850 mA during device calibration.
• At wakeup, the WiLink 8 module performs the entire calibration sequence at the center of the 2.4-GHz band.
• Once a link is established, calibration is performed periodically (every 5 minutes) on the specific channel tuned.
• The maximum VBAT value is based on peak calibration consumption with a 30% margin.
Table 6-2. Bluetooth Performance Parameters
BLUETOOTH
SPECIFICATION (TYP)
CONDITIONS
Maximum TX power
11.7 dBm
GFSK
Minimum sensitivity
–92.2 dBm
GFSK
28
Detailed Description
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Table 6-2. Bluetooth Performance Parameters (continued)
BLUETOOTH
SPECIFICATION (TYP)
CONDITIONS
Sniff
178 µA
1 attempt, 1.28 s (+4 dBm)
Page or inquiry
253 µA
1.28-s interrupt, 11.25-ms scan window (+4 dBm)
A2DP
7.5 mA
MP3 high quality 192 kbps (+4 dBm)
Table 6-3. Shutdown and Sleep Currents
PARAMETER
Shutdown mode
All functions shut down
WLAN sleep mode
Bluetooth sleep mode
6.1
POWER SUPPLY CURRENT
TYP
VBAT
10
VIO
2
VBAT
160
VIO
60
VBAT
110
VIO
60
UNIT
µA
µA
µA
WLAN Features
The device supports the following WLAN features:
• Integrated 2.4-GHz power amplifiers (PAs) for a complete WLAN solution
• Baseband processor: IEEE Std 802.11a, 802.11b/g, and IEEE Std 802.11n data rates with 20- or 40MHz SISO and 20-MHz MIMO
• Fully calibrated system (production calibration not required)
• Medium access controller (MAC)
– Embedded ARM® central processing unit (CPU)
– Hardware-based encryption-decryption using 64-, 128-, and 256-bit WEP, TKIP, or AES keys
– Requirements for Wi-Fi-protected access (WPA and WPA2.0) and IEEE Std 802.11i (includes
hardware-accelerated Advanced Encryption Standard [AES])
• New advanced coexistence scheme with Bluetooth and Bluetooth LE wireless technology
• 2.4- and 5-GHz radio
– Internal LNA and PA
– IEEE Std 802.11a, 802.11b, 802.11g, and 802.11n
• 4-bit SDIO host interface, including high speed (HS) and V3 modes
6.2
Bluetooth Features
The device supports the following Bluetooth features:
• Bluetooth 4.1 as well as CSA2
• Concurrent operation and built-in coexisting and prioritization handling of Bluetooth and Bluetooth LE
wireless technology, audio processing, and WLAN
• Dedicated audio processor supporting on-chip SBC encoding + A2DP
– Assisted A2DP (A3DP): SBC encoding implemented internally
– Assisted WB-speech (AWBS): modified SBC codec implemented internally
6.3
Bluetooth LE Features
The device supports the following Bluetooth LE features:
• Bluetooth 4.0 LE dual-mode standard
• All roles and role combinations, mandatory as well as optional
• Up to 10 LE connections
• Independent LE buffering allowing many multiple connections with no affect on BR-EDR performance
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6.4
www.ti.com
WiLink 8 Module Markings
Figure 6-2 shows the markings for the TI WiLink 8 module.
Model: WL18MODGI
Test Grade: &7
FCC ID: Z64-WL18DBMOD
IC: 451I-WL18DBMOD
R 201-140447
LTC: 1212 013
Figure 6-2. WiLink 8 Module Markings
Table 6-4 describes the WiLink 8 module markings.
Table 6-4. Description of WiLink 8 Module Markings
MARKING
WL18 MODGI
&7
DESCRIPTION
Model
Test grade (for more information, see Section 6.5, Test Grades)
Z64-WL18DBMOD
FCC ID: single modular FCC grant ID
451I-WL18DBMOD
IC: single modular IC grant ID
201-140447
R: single modular TELEC grant ID
YYWW SSF
LTC (lot trace code):
•
YY = year (for example, 12 = 2012)
•
WW = week
•
SS = serial number (01 to 99) matching manufacturer lot number
•
F = Reserved for internal use
TELEC compliance mark
CE
6.5
CE compliance mark
Test Grades
To minimize delivery time, TI may ship the device ordered or an equivalent device currently available that
contains at least the functions of the part ordered. From all aspects, this device will behave exactly the
same as the part ordered. For example, if a customer orders device WL1807MOD, the part shipped can
be marked with a test grade of 37, 07 (see Table 6-5).
Table 6-5. Test Grade Markings
30
MARK
WLAN 2.4 and 5 GHz
07
Tested
–
37
Tested
Tested
Detailed Description
BLUETOOTH
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7 Applications and Implementation
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
7.1.1
Application Information
Typical Application – WL1837MOD Reference Design
Figure 7-1 shows the TI WL1837MODI reference design.
BT_EN
WLAN/BT Enable Control.
Connect to Host GPIO.
WLAN_EN
For Debug only
VBAT_IN
TP1 TP2
VIO_IN
C1
1uF
0402
EXT_32K
33
GND
36
35
38
37
39
40
34
GND
GND
EXT_32K
GND
VIO
GND
WLAN_EN_SOC
43
42
41
BT_EN_SOC
BT_UART_DBG
WL_UART_DBG
46
44
GND
47
45
GND
GND
RF_ANT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
32
ANT1
W3006
ANT-10.0X3.2MM_B
C13
1pF
0402
R1
0R
0402
1
FEED
NC
2
31
R2
NU_0R
0402
30
29
28
27
WL_RS232_TX_1V8
TP3
26
WL_RS232_RX_1V8
TP4
25
J5
U.FL-R-SMT(10)
U.FL
L2
NU
0402
L1
1.3nH
0402
2
1
3
TP5
For Debug only
24
For Debug only
23
22
TP6
21
TP7
ANT2 - WL_2.4_IO1/WL_5GHz
20
19
R3
0R
0402
18
C14
2.4pF
0402
ANT2
W3006
ANT-10.0X3.2MM_A
1
FEED
NC
2
17
R4
NU_0R
0402
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
J6
U.FL-R-SMT(10)
U.FL
L4
2.2nH
0402
L3
1.8nH
0402
2
1
3
For Debug only
16
WLAN_IRQ
GND
15
14
WL_SDIO_D3
13
WL_SDIO_D2
12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
WL_SDIO_D1
RESERVED
1
External TCXO option.
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
GND
RESERVED3
WL_SDIO_D0
R14
0R
0402
RESERVED1
GND
GND
64
GND
BT_AUD_CLK
9
63
GND
RESERVED2
11
62
GPIO_4
GND
10
61
BT_AUD_FSYNC
WL_SDIO_CLK
60
TP8
BT_AUD_OUT
GND
BT_AUD_CLK
Connect to Host BT PCM Bus.
U1
WL1837MODGI
E-13.4X13.3-N100_0.75-TOP
BT_AUD_IN
WL_SDIO_CMD
59
GPIO_2
8
58
GND
7
57
GPIO_1
6
56
BT_AUD_FSYNC
GND
GND
GPIO12
BT_AUD_IN
BT_AUD_OUT
GND
BT_HCI_RX
5
55
GND
BT_HCI_TX
GPIO10
54
Connect to Host HCI Interface.
BT_HCI_CTS
4
53
GND
GND
52
BT_HCI_RX_1V8
GND
GPIO9
BT_HCI_TX_1V8
ANT1 - WL_2.4_IO2/BT/WL_5GHz
RF_ANT1
BT_HCI_RTS
GPIO11
51
GND
50
3
BT_HCI_RTS_1V8
BT_HCI_CTS_1V8
GND
2
49
VBAT
48
C3
0.1uF
0402
VBAT
C2
10uF
0603
VIO_IN
For Debug only
R13
NU
RES1005
TP10TP11TP12TP13
WL_IRQ_1V8
WL_SDIO_D3_1V8
WL_SDIO_D2_1V8
WL_SDIO_D1_1V8
WL_SDIO_D0_1V8
WL_SDIO_CLK_1V8
WL_SDIO_CMD_1V8
Connect to Host SDIO Interface.
Figure 7-1. TI Module Reference Schematics
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Table 7-1 lists the bill materials (BOM).
Table 7-1. Bill of Materials
ITEM
DESCRIPTION
PART NO.
PACKAGE
REFERENCE
QTY
MFR
13.4 × 13.3 ×
2.0 mm
U1
1
TI
7XZ3200005
3.2 × 2.5 ×
1.0 mm
OSC1
1
TXC
ANT/Chip/2.4 GHz and 5 GHz (1)
W3006
10.0 × 3.2 ×
1.5 mm
ANT1, ANT2
2
Pulse
4
Mini-RF header receptacle
U.FL-R-SMT-1 (10)
3.0 × 2.6 ×
1.25 mm
J5, J6
2
Hirose
5
Inductor 0402/1.3 nH/±0.1 nH/SMD
LQP15MN1N3B02
0402
L1
1
Murata
6
Inductor 0402/1.8 nH/±0.1 nH/SMD
LQP15MN1N8B02
0402
L3
1
Murata
7
Inductor 0402/2.2 nH/±0.1 nH/SMD
LQP15MN2N2B02
0402
L4
1
Murata
8
Capacitor 0402/1 pF/50 V/C0G/±0.1 pF
GJM1555C1H1R0BB01
0402
C13
1
Murata
9
Capacitor 0402/2.4 pF/50 V/C0G/±0.1 pF
GJM1555C1H2R4BB01
0402
C14
1
Murata
10
Capacitor 0402/0.1 µF/10 V/X7R/±10%
0402B104K100CT
0402
C3
1
Walsin
11
Capacitor 0402/1 µF/6.3 V/X5R/±10%/HF
GRM155R60J105KE19D
0402
C1
1
Murata
12
Capacitor 0603/10 µF/6.3 V/X5R/±20%
C1608X5R0J106M
0603
C2
1
TDK
13
Resistor 0402/0R/±5%
WR04X000 PTL
0402
R1, R3
2
Walsin
1
WL1837 Wi-Fi/Bluetooth module
WL1837MODGI
2
XOSC 3225/32.768 kHz/1.8 V/±50 ppm
3
(1)
For more information, see productfinder.pulseeng.com/product/W3006.
7.1.2
Design Recommendations
This section describes the layout recommendations for the WL1837 module, RF trace, and antenna.
Table 7-2 summarizes the layout recommendations.
Table 7-2. Layout Recommendations Summary
ITEM
DESCRIPTION
Thermal
1
The proximity of ground vias must be close to the pad.
2
Signal traces must not be run underneath the module on the layer where the module is mounted.
3
Have a complete ground pour in layer 2 for thermal dissipation.
4
Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
5
Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.
6
Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.
RF Trace and Antenna Routing
7
The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.
8
The RF trace bends must be gradual with an approximate maximum bend of 45 degrees with trace mitered. RF traces must not
have sharp corners.
9
RF traces must have via stitching on the ground plane beside the RF trace on both sides.
10
RF traces must have constant impedance (microstrip transmission line).
11
For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be
solid.
12
There must be no traces or ground under the antenna section.
13
RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The
proximity of the antenna to the enclosure and the enclosure material must also be considered.
Supply and Interface
32
14
The power trace for VBAT must be at least 40-mil wide.
15
The 1.8-V trace must be at least 18-mil wide.
16
Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.
Applications and Implementation
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Table 7-2. Layout Recommendations Summary (continued)
ITEM
DESCRIPTION
17
If possible, shield VBAT traces with ground above, below, and beside the traces.
18
SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than
12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater
than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these
traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.
19
SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a
clearance around them.
7.1.3
RF Trace and Antenna Layout Recommendations
Figure 7-2 shows the location of the antenna on the WL1837MODCOM8I board as well as the RF trace
routing from the WL1837 module (TI reference design). The Pulse multilayer antennas are mounted on
the board with a specific layout and matching circuit for the radiation test conducted in FCC, CE, and IC
certifications.
Antennas are orthogonal
to each other.
Antennas distance is Higher than
half wavelength.
76.00 mm
No sharp corners.
Constant 50 Ω control
impedance RF Trace.
Antenna placement on
the edge of the board.
Figure 7-2. Location of Antenna and RF Trace Routing on the WL1837MODCOM8I Board
Follow these RF trace routing recommendations:
• RF traces must have 50-Ω impedance.
• RF traces must not have sharp corners.
• RF traces must have via stitching on the ground plane beside the RF trace on both sides.
• RF traces must be as short as possible. The antenna, RF traces, and module must be on the edge of
the PCB product in consideration of the product enclosure material and proximity.
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7.1.4
www.ti.com
Module Layout Recommendations
Figure 7-3 and Figure 7-4 show layer 1 and layer 2 of the TI module layout.
Figure 7-3. TI Module Layout: Layer 1
Figure 7-4. TI Module Layout: Layer 2 (Solid GND)
34
Applications and Implementation
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Follow these module layout recommendations:
• Ensure a solid ground plane and ground vias under the module for stable system and thermal
dissipation.
• Do not run signal traces underneath the module on a layer where the module is mounted.
• Signal traces can be run on a third layer under the solid ground layer and beneath the module
mounting.
• Run the host interfaces with ground on the adjacent layer to improve the return path.
• TI recommends routing the signals as short as possible to the host.
7.1.5
Thermal Board Recommendations
The TI module uses µvias for layers 1 through 6 with full copper filling, providing heat flow all the way
to the module ground pads.
TI recommends using one big ground pad under the module with vias all the way to connect the pad to
all ground layers (see Figure 7-5).
Module
COM8 Board
Figure 7-5. Block of Ground Pads on Bottom Side of Package
Figure 7-6 shows via array patterns, which are applied wherever possible to connect all of the layers to
the TI module central or main ground pads.
Figure 7-6. Via Array Patterns
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7.1.6
www.ti.com
Baking and SMT Recommendations
7.1.6.1
Baking Recommendations
Follow these baking guidelines for the WiLink 8 module:
• Follow MSL level 3 to perform the baking process.
• After the bag is open, devices subjected to reflow solder or other high temperature processes must be
mounted within 168 hours of factory conditions (< 30°C/60% RH) or stored at 10%, devices require baking before they are mounted.
• If baking is required, bake devices for 8 hours at 125°C.
7.1.6.2
SMT Recommendations
Figure 7-7 shows the recommended reflow profile for the WiLink 8 module.
Temp
(degC)
D3
D2
T3
D1
T1
Meating
T2
Soldering
Preheat
Cooling
Time
(SeC)
Figure 7-7. Reflow Profile for the WiLink 8 Module
Table 7-3 lists the temperature values for the profile shown in Figure 7-7.
Table 7-3. Temperature Values for Reflow Profile
ITEM
TEMPERATURE (°C)
TIME (s)
Preheat
D1 to approximately D2: 140 to 200
T1: 80 to approximately 120
Soldering
D2: 220
T2: 60 ±10
Peak temperature
D3: 250 maximum
T3: 10
space
NOTE
TI does not recommend the use of conformal coating or similar material on the WiLink 8
module. This coating can lead to localized stress on the WCSP solder connections inside the
module and impact the device reliability. Care should be taken during module assembly
process to the final PCB to avoid the presence of foreign material inside the module.
36
Applications and Implementation
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8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
For a complete listing of development-support tools, visit the Texas Instruments WL18xx Wiki. For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
8.1.2
Device Support Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These
prefixes represent evolutionary stages of product development from engineering prototypes through fully
qualified production devices.
X
null
8.2
Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and
may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the
contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of
fitness for a specific purpose, of this device.
Device is qualified and released to production. TI’s standard warranty applies to production devices.
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
8.3
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
WL1807MOD
Click here
Click here
Click here
Click here
Click here
WL1837MOD
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
8.4
Trademarks
WiLink, E2E are trademarks of Texas Instruments.
ARM is a registered trademark of ARM Physical IP, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc..
Android is a trademark of Google, Inc.
IEEE Std 802.11 is a trademark of IEEE.
Linux is a registered trademark of Linus Torvalds.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
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8.5
www.ti.com
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
Device and Documentation Support
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9 Mechanical Packaging and Orderable Information
9.1
TI Module Mechanical Outline
Figure 9-1 shows the mechanical outline for the device.
W
e4
T
e5
W
e2
d2
e3
d1
e1
L
L
e6
Pin 2 Indicator
a3
c2 c3
b1
b2
4 3 2
a1
a2
b3
1
c1
Bottom View
Top View
Side View
Figure 9-1. TI Module Mechanical Outline
Table 9-1 lists the dimensions for the mechanical outline of the device.
NOTE
The TI module weighs 0.684 g (±0.005 g).
Table 9-1. Dimensions for TI Module Mechanical Outline
MARKING
MIN (mm)
NOM (mm)
MAX (mm)
MARKING
MIN (mm)
NOM (mm)
MAX (mm)
L (body size)
13.20
13.30
13.40
c2
0.65
0.75
0.85
W (body size)
13.30
13.40
13.50
c3
1.15
1.25
1.35
T (thickness)
1.90
2.00
d1
0.90
1.00
1.10
a1
0.30
0.40
0.50
d2
0.90
1.00
1.10
a2
0.60
0.70
0.80
e1
1.30
1.40
1.50
a3
0.65
0.75
0.85
e2
1.30
1.40
1.50
b1
0.20
0.30
0.40
e3
1.15
1.25
1.35
b2
0.65
0.75
0.85
e4
1.20
1.30
1.40
b3
1.20
1.30
1.40
e5
1.00
1.10
1.20
c1
0.20
0.30
0.40
e6
1.00
1.10
1.20
Mechanical Packaging and Orderable Information
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WL1807MOD, WL1837MOD
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9.2
www.ti.com
Tape and Reel Information
Emboss taping specification for MOC 100 pin.
Tape and Reel Specification
P2
Po
E
9.2.1
F
Do
W
Pin 1
T
P
C0.5
Ko
5.00°
Ao = Bo
Figure 9-2. Tape Specification
Table 9-2. Dimensions for Tape Specification
ITEM
W
E
F
P
Po
P2
Do
T
Ao
Bo
Ko
DIMENSION
(mm)
24.00
(±0.30)
1.75
(±0.10)
11.50
(±0.10)
20.00
(±0.10)
4.00
(±0.10)
2.00
(±0.10)
2.00
(±0.10)
0.35
(±0.05)
13.80
(±0.10)
13.80
(±0.10)
2.50
(±0.10)
330.00±2.0
2.20±0.7
100.00±1.5
W1
W2
Figure 9-3. Reel Specification
Table 9-3. Dimensions for Reel Specification
9.2.2
ITEM
W1
W2
DIMENSION (mm)
24.4 (+1.5, –0.5)
30.4 (maximum)
Packing Specification
9.2.2.1
Reel Box
The reel is packed in a moisture barrier bag fastened by heat-sealing. Each moisture-barrier bag is
packed into a reel box, as shown in Figure 9-4.
40
Mechanical Packaging and Orderable Information
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856
45
370
572
360
Figure 9-4. Reel Box
The reel box is made of corrugated fiberboard.
9.2.2.2
Shipping Box
Figure 9-5 shows a typical shipping box. If the shipping box has excess space, filler (such as cushion) is
added.
NOTE
362
616
The size of the shipping box may vary depending on the number of reel boxes packed.
354
250
1,243
Figure 9-5. Shipping Box
The shipping box is made of corrugated fiberboard.
Mechanical Packaging and Orderable Information
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9.3
www.ti.com
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
Orderable Device
Status(1)
Package Type
Package
Drawing
Pins
Package Qty
Eco Plan(2)
Lead/Ball Finish
MSL Peak Temp (°C) (3)
Op Temp (°C)
WL1807MODGIMOCR
ACTIVE
Module
MOC
100
1200
RoHS Compliant
NiPdAu
250
–40 to 85
WL1807MODGIMOCT
ACTIVE
Module
MOC
100
250
RoHS Compliant
NiPdAu
250
–40 to 85
WL1837MODGIMOCR
ACTIVE
Module
MOC
100
1200
RoHS Compliant
NiPdAu
250
–40 to 85
WL1837MODGIMOCT
ACTIVE
Module
MOC
100
250
RoHS Compliant
NiPdAu
250
–40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS Compliance: This product has an RoHS exemption for one or more subcomponent(s). The product is otherwise considered Pb-Free (RoHS compatible) as defined above.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Mechanical Packaging and Orderable Information
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43
PACKAGE OUTLINE
QFM - 2.0 mm max height
MOC0100A
QUAD FLAT MODULE
13.4
13.2
B
A
1
PIN 1
INDEX AREA
13.5
13.3
C
2 MAX
0.08 C
2X 11.95
2X 9.8
7.7
TYP
17
56X
0.7
33
G36
G6
7.7
TYP
(1.4) TYP
SYMM
2X 9.8
G3
60X 0.8
0.7
2X 12.05
60X 0.45
0.35
G1
G7
G19
G31
0.1
0.05
1
PIN 2
ID
64
4X
0.8
0.7
C A B
C
49
SYMM
36X
(1.4) TYP
1.05
0.95
4221006/B 10/2016
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
QFM - 2.0 mm max height
MOC0100A
QUAD FLAT MODULE
2X (11.95)
64
1
49
G1
G7
G19
G13
G25
G31
2X
(12.05)
SYMM
56X (0.7)
(1.05) TYP
(1.4) TYP
60X (0.75)
60X (0.4)
G6
G12
G18
G24
G30
(1.05) TYP
G36
(1.4) TYP
33
17
4X
(0.75)
36X
(1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
ALL AROUND
SOLDER MASK DETAILS
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(R0.05) TYP
METAL UNDER
SOLDER MASK
4221006/B 10/2016
NOTES: (continued)
4.
5.
6.
This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271) .
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, it is recommended
that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
QFM - 2.0 mm max height
MOC0100A
QUAD FLAT MODULE
2X (11.95)
64
1
49
G1
G7
G19
G13
G25
G31
60X (0.4)
60X (0.75)
2X
(12.05)
SYMM
56X (0.7)
(1.05) TYP
(1.4) TYP
SEE DETAIL B
G6
G12
G18
(1.05) TYP
G24
G30
G36
(1.4) TYP
33
17
SYMM
SEE DETAIL A
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PADS 1, 17, 33, 49, G1-G36
90% PRINTED COVERAGE BY AREA
SCALE: 8X
SOLDER
PASTE
METAL UNDER
SOLDER MASK
METAL UNDER
SOLDER MASK
4X
(0.713)
DETAIL A
SCALE 20X
SOLDER
PASTE
SOLDER
MASK
EDGE
SOLDER
MASK
EDGE
36X
(0.95)
DETAIL B
SCALE 20X
4221006/B 10/2016
NOTES: (continued)
7.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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