CDK1300

Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs features n n n n n n n General Description The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 310mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The CDK1300 digital outputs are demuxed (double-wide) with both dualchannel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40°C to +85°C. TTL/CMOS/PECL input logic compatible High conversion rate: 250 MSPS Single +5V power supply Very low power dissipation: 310mW 220MHz full power bandwidth Power-down mode +3.0V/+5.0V (LVCMOS) digital output logic compatibility Single/demuxed output ports selectable n applications n n n n n RGB video processing Digital communications High-speed instrumentation Digital Sampling Oscilloscopes (DSO) Projection display systems Block Diagram REV 1A Ordering Information Part Number CDK1300ITQ44 CDK1300ITQ44_Q Package TQFP-44 TQFP-44 Pb-Free Yes No RoHS Compliant Yes No Operating Temperature Range -40°C to +85°C -40°C to +85°C Packaging Method Rail Rail Moisture sensitivity level for all parts is MSL-1. ©2008 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Pin Configuration TQFP-44 CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs CDK1300 Pin Assignments Pin No. 40 39 16-9 19-26 28 27 4 3 5 6 Pin Name VIN+ VINDA0–DA7 DB0–DB7 DCLKOUT DCLKOUT CLK CLK RESET RESET Description Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Data output bank A; 3V/5V LVCMOS compatible Data output bank B; 3V/5V LVCMOS compatible Non-inverted data output clock; 3V/5V LVCMOS compatible Inverted data output clock; 3V/5V LVCMOS compatible Non-inverted clock input pin; 100k pulldown to AGND, internally Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally RESET synchronizes the data sampling and data output bank relationship when in dual channel mode (DMODE1 = 0); 100k pulldown to AGND, internally Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2 32, 31 DMODE1,2 Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output DMODE1 = 0, DMODE2 = 1: interleaved dual channel output DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max) 2 37 35, 36, 42, 43 7, 17, 30 1, 33, 34, 38, 41, 44 8, 18, 29 PD VCM AVCC OVDD AGND DGND Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down mode; 100k pulldown to AGND, internally 2.5V common mode voltage reference output +5V analog supply +3V/+5V digital output supply Analog ground Digital ground REV 1A ©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs Parameter Supply Voltage AVCC OVDD Input Voltages Analog inputs Digital inputs Min Max +6 +6 Unit V V V V -0.5V -0.5V Vcc +0.5V Vcc +0.5V Reliability Information Parameter Storage Temperature Range Min -65 Typ Max +125 Unit °C Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C REV 1A ©2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Electrical Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) symbol parameter Resolution conditions Min typ 8 Max units bits CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs DC Performance DLE ILE Differential Linearity Error Integral Linearity Error No Missing Codes +25°C, ƒIN = 1KHz -40°C to +85°C, ƒIN = 1KHz +25°C, ƒIN = 1KHz -40°C to +85°C, ƒIN = 1KHz @250 MSPS, ƒIN = 1KHz with respect to VIN2.3 +25°C +25°C +25°C +25°C (-3dB of FS) +25°C +25°C AVcc = 5V ±0.25V 250 (2) -0.7/1.05 -0.95/+1.5 ±1.7 ±2.25 Guaranteed ±470 2.5 10 50 4 220 2 ±10 0.5 2.0 LSB LSB LSB LSB Analog Input Input Voltage Range VCM Input Common Mod Input Bias Current Input Resistance Input Capacitance Input Bandwidth Gain Error Offset Error PSRR Offset Power Supply Rejection Ratio Conversion Rate(1) tpd1 tap Output Delay (Clock-to-Data) Output Delay Tempco Aperture Delay Time Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time tpd2 tpd3 Single Channel Mode(2) Dual Channel Mode (2) (2) mVpp V µA kΩ pF MHz % mV mV/V MSPS Timing Characteristics -40°C to +85°C 6 8 22 0.5 2.0 2.5 2.5 2.5 3.5 4 5.3 ƒIN = 70MHz, +25°C(1) ƒIN = 70MHz, -40°C to +85°C ƒIN = 70MHz, +25°C(1) ƒIN = 70MHz, -40°C to +85°C(2) ƒIN = 70MHz, +25°C (1) (2) 10.5 ns ps/°C ns ps-RMS Cycle Cycle Cycle Cycle REV 1A 6 6.16 6.4 6.0 43 40 -43 -42 7 7.8 ns ns Bits Bits dB dB Dynamic Performance ENOB SNR THD SINAD Effective Number of Bits Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion 5.8 5.5 42 36 -40 -37 dB dB dB dB ƒIN = 70MHz, -40°C to +85°C(2) ƒIN = 70MHz , +25°C(1) ƒIN = 70MHz, -40°C to +85°C (2) 37 35 40 38 notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle, ƒIN = 70MHz, dual channel mode; unless otherwise noted) symbol AVcc OVDD AVcc parameter Analog Voltage Supply(2) Digital Voltage Supply(2) Current (1) conditions Min 4.75 2.75 typ 5.0 62 Max 5.25 5.25 70 350 2.55 units Power Supply Requirements CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs V V mA mW V ppm/°C kΩ mV/V mVpp Power Dissipation(1) with Internal Voltage Reference 2.45 IOUT = ±50µA 310 2.5 100 1 63 400 Common Mode Reference Output Voltage(1) Voltage Tempco Output Impedance PSRR VDIFF VIHD VILD VCMD VIH VIL IIH IIL Power Supply Rejection Ratio Differental Signal Amplitude(1) Differental High Input Voltage (2) Clock and Reset Inputs (Differential and Single-Ended) 1.4 0 1.2 1.8 1.2 VID = 1.5V VID = 1.5V -100 -100 2.0 0 (1) (2) 5 3.9 4.1 V V V V V µA µA V V µA µA V Differental Low Input Voltage(2) Differental Common Mode Input(2) Single-Ended High Input Voltage High Input Current(1) Low Input Current(1) High Input Voltage(2) Low Input Voltage(2) Max Input Current Low Max Input Current High