CDK1307EILP40

Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit Analog-to-Digital Converters (ADCs) CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs FEATURES n n General Description The CDK1307 is a high performance ultra low power Analog-to-Digital Converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. 13-bit resolution 10/20/40/65/80/100MSPS max sampling rate Ultra-Low Power Dissipation: 17/19/33/50/60/75mW 72.4dB SNR at 80MSPS and 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7 – 3.6V I/O supply voltage Parallel CMOS output 40-pin QFN package Pin compatible with CDK1308 n n n n n n n n APPLICATIONS n n n n Medical Imaging Portable Test Equipment Digital Oscilloscopes IF Communication Functional Block Diagram Ordering Information Part Number CDK1307ILP40 CDK1307AILP40 CDK1307BILP40 CDK1307CILP40 CDK1307DILP40 CDK1307EILP40 Speed 10MSPS 20MSPS 40MSPS 65MSPS 80MSPS 100MSPS Package QFN-40 QFN-40 QFN-40 QFN-40 QFN-40 QFN-40 Pb-Free Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray Tray Tray Tray Tray Rev 1A Moisture sensitivity level for all parts is MSL-2A. ©2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Pin Configuration CM_EXTBC_0 CM_EXTBC_1 QFN-40 SLP_N OVDD OVDD D_12 D_10 D_11 D_9 D_8 CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs 40 39 38 37 36 35 34 33 32 DVDD CM_EXT AVDD AVDD IP IN AVDD DVDDCLK CLKP CLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 D_7 D_6 D_5 CLK_EXT OVDD OVDD ORNG D_4 D_3 D_2 CDK1307 QFN-40 27 26 25 24 23 22 21 DFRMT OE_N OVDD OVDD DVDD DVDD D_0 Pin Assignments Pin No. 0 1, 11, 16 2 3, 4, 7 5, 6 8 9 10 12 13 14 15 17, 18, 25, 26, 36, 37 19 20 21 22 Pin Name VSS DVDD CM_EXT AVDD IP, IN DVDDCLK CLKP CLKN CLK_EXT_EN DFRMT PD_N OE_N OVDD D_0 D_1 D_2 D_3 Description Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog input (non-inverting, inverting) Clock circuitry supply voltage, 1.8V Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. Output Enable. Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V Output Data (LSB, 13-bit output or 1Vpp full scale range) Output Data (LSB, 12-bit output 2Vpp full scale range) Output Data Output Data CLK_EXT_EN PD_N D_1 Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Pin Assignments (Continued) Pin No. 23 24 27 28 29 30 31 32 33 34 35 38, 39 Pin Name D_4 ORNG CLK_EXT D_5 D_6 D_7 D_8 D_9 D_10 D_11 D_12 CM_EXTBC_1, CM_EXTBC_0 SLP_N Description Output Data Out of Range flag. High when input signal is out of range CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Output clock signal for data synchronization. CMOS levels Output Data Output Data Output Data Output Data Output Data Output Data Output Data (MSB for 1Vpp full scale range, see Reference Voltages section) Output Data (MSB for 2Vpp full scale range) Bias control bits for the buffer driving pin CM_EXT 00: OFF 10: 500μA 01: 50μA 11: 1mA 40 Sleep Mode when low Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Parameter AVDD DVDD AVSS, DVSSCK, DVSS, OVSS OVDD, OVSS CLKP, CLKN Analog inputs and outpts (IPx, INx) Digital inputs Digital outputs Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max TBD +150 Unit °C °C ESD Protection Product Human Body Model (HBM) QFN-40 2kV Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Conditions Min Typ Guaranteed Max Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Midscale offset Full scale range deviation from typical 12-bit level 12-bit level -6 1 6 ±0.2 ±0.6 VAVDD/2 mV %FS LSB LSB V VCM +0.2 V Vpp Vpp pF MHz DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range, Normal Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range, Differential input voltage range, 1V (see section Reference Voltages) Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 500 1.7 1.7 1.8 2.5 2.0 3.6 VCM -0.1 2.0 1.0 2 Full Scale Range, Option Input Capacitance Bandwidth Power Supply AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Electrical Characteristics - CDK1307A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 72.5 Max Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 15 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz 71.5 72.2 72.1 71.6 72.4 SINAD Signal to Noise and Distortion Ratio 71 72.0 71.7 71.3 87 SFDR Spurious Free Dynamic Range 75 85 80 80 -90 HD2 Second order Harmonic Distortion -85 -95 -95 -95 -87 HD3 Third order Harmonic Distortion -75 -85 -80 -80 11.7 ENOB Effective number of Bits 11.5 11.7 11.6 11.6 7.8 Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 20 1.0 1.7 1.3 14.0 5.1 19.1 9.9 9.2 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Rev 1A Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Electrical Characteristics - CDK1307B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 72.5 Max Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 20 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz 71.9 72.7 72 70.8 71.7 SINAD Signal to Noise and Distortion Ratio 71 72.1 71.5 71.2 81 SFDR Spurious Free Dynamic Range 75 81 80 80 -90 HD2 Second order Harmonic Distortion -85 -95 -95 -90 -81 -81 HD3 Third order Harmonic Distortion -75 -80 -80 11.6 ENOB Effective number of Bits 11.5 11.7 11.6 11.4 13.4 Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 40 1.7 3.3 2.4 24.1 9.1 33.2 9.7 14.2 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Rev 1A Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Electrical Characteristics - CDK1307C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 71.6 Typ 72.6 71.8 71.5 70.4 Max Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 40 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 70.5 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 75 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -85 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -75 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 11.4 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz 71.7 71.7 71.1 70 81 84 79 77 -95 -95 -95 -95 -81 -84 -79 -79 11.6 11.6 11.5 11.3 20.4 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 65 2.3 5.1 3.5 36.7 12.9 49.6 9.3 20.4 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Rev 1A Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Electrical Characteristics - CDK1307D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 70.4 Typ 72 71.7 71.2 70.7 Max Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 65 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 69.5 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 74 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -80 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -74 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 11.3 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 70.5 70.5 70.5 70.3 77 78 78 78 -95 -90 -90 -85 -77 -78 -78 -78 11.4 11.4 11.4 11.4 24.5 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 80 2.9 6.1 4.1 44.1 15.5 59.6 9.1 24.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Rev 1A Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet D i g i t a l a n d T i m i n g E l e c t r i c a l C h a ra c t e r i s t i c s (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, - 1 d B F S i n p u t s i g n a l , 5 p F c a p a c i t i ve l o a d , u n l e s s o t h e r w i s e n o t e d ) Symbol Clock Inputs Parameter Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance Conditions Min 20 Typ Max 80 Units CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs % high mVpp Vpp CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential 400 1.6 0.3 2 VOVDD -0.3 V pF Timing TPD TSLP TOVR TAP Start Up Time from Power Down Start Up Time from Sleep Out Of Range Recovery Time Aperture Delay Aperture Jitter Pipeline Delay Output Delay Output Delay Relative to CLK_EXT 5pF load on output bits (see timing diagram) See timing diagram VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V 3 1 2 0.8 • VOVDD 0 0 -10 -10 3 -0.1 +VOVDD 0.1 Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VVDVDD Post-driver supply voltage above 2.25V (1) 10 5 0.8 0.2 • VOVDD 10 10 From Power Down Mode to Active Mode From Sleep Mode to Active Mode 1 0.8 0.5V 0.5V +0.24mV -0.24mV -0.5V < -0.5V 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 1000 0000 0000 D_12 = 1 & D_11 = 1 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 D_12 = 0 & D_11 = 1 D_12 = 0 & D_11 = 0 1000 0000 0000 D_12 = 1 & D_11 = 0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet Mechanical Dimensions QFN-40 Package D D2 Pin 1 ID - Dia. 0.5 (Top Side) 1.14 Pin 1 ID - Dia. R F A G A3 0.45 Pin 0 Exposed Pad A1 Symbol A A1 A2 A3 b D D1 D2 L e 1 Min – 0.001 – 0.008 0.156 0.012 0° 0.008 0.0096 0.004 F G R Inches Typ – 0.0004 0.023 0.008 REF 0.010 0.236 BSC 0.226 BSC 0.162 0.016 0.020 BSC – – 0.0168 0.008 Max 0.035 0.002 0.028 0.013 Min – 0.00 – 0.2 0.167 0.020 12° – 0.024 – 3.95 0.3 0° 0.2 0.24 0.1 Millimeters Typ – 0.01 0.65 0.2 REF 0.25 6.00 BSC 5.75 BSC 4.10 0.4 0.50 BSC – – 0.42 0.2 Max 0.9 0.05 0.7 0.32 CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs 4.25 0.5 12° – 0.6 – NOTE: D D2 D1 Package dimensions in millimeter unless otherwise noted. 1 L e b A2 Rev 1A For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e