CDK1308CILP40

ADVANCE Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters (ADCs) CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs FEATURES n n n General Description The CDK1308 is a high performance ultra low power analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. 10-bit resolution 20/40/65/80MSPS max sampling rate Ultra-Low Power Dissipation: 15/25/38/46mW 61.6dB SNR at 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7 – 3.6V I/O supply voltage Parallel CMOS output 40-pin QFN package Pin compatible with CDK1307 n n n n n n n APPLICATIONS n n n n Medical Imaging Portable Test Equipment Digital Oscilloscopes IF Communication Functional Block Diagram Rev 0.1 10 Ordering Information Part Number CDK1308AILP40 CDK1308BILP40 CDK1308CILP40 CDK1308DILP40 Speed 20MSPS 20MSPS 65MSPS 80MSPS Package QFN-40 QFN-40 QFN-40 QFN-40 Pb-Free Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray Tray Tray Moisture sensitivity level for all parts is MSL-3. ©2008 CADEKA Microcircuits LLC www.cadeka.com ADVANCE Data Sheet Pin Configuration CM_EXTBC_0 CM_EXTBC_1 QFN-40 SLP_N OVDD OVDD D_9 D_8 D_7 D_6 D_5 CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs 40 39 38 37 36 35 34 33 32 DVSS CM_EXT AVDD AVDD IP IN AVDD DVDDCLK CLKP CLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 D_4 D_3 D_2 CLK_EXT OVDD OVDD ORNG D_1 D_0 NC CDK1308 QFN-40 27 26 25 24 23 22 21 DFRMT OE_N OVDD OVDD NC DVDD Pin Assignments Pin No. 0 1, 11, 16 2 3, 4, 7 5, 6 8 9 10 12 13 14 15 17, 18, 25, 26, 36, 37 19 20 21 22 Pin Name VSS DVDD CM_EXT AVDD IP, IN DVDDCLK CLKP CLKN CLK_EXT_EN DFRMT PD_N OE_N OVDD NC NC NC D_0 Output Data Description Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog input (non-inverting, inverting) Clock circuitry supply voltage, 1.8V Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. Output Enable. Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V CLK_EXT_EN DVDD PD_N NC Rev 0.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 2 ADVANCE Data Sheet Pin Assignments (Continued) Pin No. 23 24 27 28 29 30 31 32 33 34 35 38, 39 Pin Name D_1 ORNG CK_EXT D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_9 CM_EXTBC_1, CM_EXTBC_0 SLP_N Description Output Data Out of Range flag. High when input signal is out of range CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Output clock signal for data synchronization. CMOS levels Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data (MSB) Bias control bits for the buffer driving pin CM_EXT 00: OFF 10: 500μA 10: 50μA 11: 1mA 40 Sleep Mode when low Rev 0.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 3 ADVANCE Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Parameter AVDD DVDD AVSS, DVSSCK, DVSS, OVSS OVDD CLKP, CLKN Analog inputs and outpts (IPx, INx) Digital inputs Digital outputs Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 TBD Typ Max TBD +150 Unit °C °C °C ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) QFN-40 2kV TBD Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C Rev 0.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 ADVANCE Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Conditions Min Typ Guaranteed Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Midscale offset Full scale range deviation from typical -6 -0.3 -0.6 TBD 6 0.3 0.6 VAVDD/2 mV %FS LSB LSB V VCM +0.1 V Vpp pF MHz DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) Analog Input VCMI VFSR VCM -0.1 2.0 1.8 500 1.7 1.7 1.8 2.5 2.0 3.6 Power Supply AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V Rev 0.1 ©2008 CADEKA Microcircuits LLC www.cadeka.com 5 ADVANCE Data Sheet Electrical Characteristics - CDK1308A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.7 61.6 61.6 61.6 61.7 61.6 60.5 61.6 84.1 85.5 70.3 87.5 -88.8 -89.5 -95.9 -91.4 -89.5 -90.5 -70.3 -89.7 10.0 9.9 9.8 9.9 5.6 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 15 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 20 1.0 1.7 1.2 10.1 4.8 14.9 9.9 7.7 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC www.cadeka.com 6 ADVANCE Data Sheet Electrical Characteristics - CDK1308B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.6 61.6 61.6 61.5 61.6 61.6 61.2 61.4 78.8 82.3 72.0 82.5 -87.9 -92.0 -84.8 -88.8 -81.8 -85.7 -72.0 -83.9 9.9 9.9 9.9 9.9 9.3 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 20 MSPS SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 40 1.7 3.1 2.2 16.7 8.6 25.3 9.7 11.3 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC www.cadeka.com 7 ADVANCE Data Sheet Electrical Characteristics - CDK1308C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min Typ 61.6 61.6 61.5 61.3 61.6 61.6 60.4 61.1 80.6 85.6 66.4 76.9 -91.4 -93.0 -83.8 -90.7 -80.6 -86.4 -66.4 -76.9 9.9 9.9 9.7 9.9 13.8 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 40 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 65 2.6 4.9 3.4 24.8 13.2 38.0 9.3 15.7 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC www.cadeka.com 8 ADVANCE Data Sheet Electrical Characteristics - CDK1308D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min Typ 61.6 61.2 61.3 61.3 61.3 60.7 61.0 58.7 74.8 73.9 74.7 61.7 -88.5 -95.0 -88.9 -79.0 -74.8 -75.0 -74.7 -61.7 9.9 9.8 9.8 9.5 16.5 Max Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits mA mA mA mA mW mW mW μW mW MSPS 65 MSPS SNR Signal to Noise Ratio FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode 80 3.3 5.9 4.1 29.7 16.2 45.9 9.1 18.3 Rev 0.1 OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2008 CADEKA Microcircuits LLC www.cadeka.com 9 ADVANCE Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Clock Inputs Parameter Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance Conditions Min 20 Typ Max 80 200 800 VOVDD -0.3 Units CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs % high mVpp mVpp V pF CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential From Power Down Mode to Active Mode References has reached 99% of final value From Sleep Mode to Active Mode 0.5 1 0.8