CDK2307BITQ64

Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters FEATURES n n n n n n n n n General Description The CDK2307 is a high performance, low power dual Analog-to-Digital Converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Several idle modes with fast startup times exist. Each channel can be independently powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. 13-bit resolution 20/40/65/80MSPS maximum sampling rate Ultra-low power dissipation: 30/55/85/102mW SNR 72dB at 80MSPS and 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7V – 3.6V I/O supply voltage Parallel CMOS output 64-pin QFN package (TQFP-64 package option also available) Dual channel Pin compatible with CDK2308 n n APPLICATIONS n n n n n n n Handheld Communication, PMR, SDR Medical Imaging Portable Test Equipment Digital Oscilloscopes Baseband / IF Communication Video Digitizing CCD Digitizing Functional Block Diagram CLKN CLK_EXT CLKP Ordering Information Part Number CDK2307AILP64 CDK2307BILP64 CDK2307CILP64 CDK2307DILP64 CDK2307AITQ64 CDK2307BITQ64 CDK2307CITQ64 CDK2307DITQ64 Speed 20MSPS 40MSPS 65MSPS 80MSPS 20MSPS 40MSPS 65MSPS 80MSPS Package QFN-64 QFN-64 QFN-64 QFN-64 TQFP-64 TQFP-64 TQFP-64 TQFP-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray Tray Tray Tray Tray Tray Tray Rev 2B Moisture sensitivity level for all parts is MSL-2A. ©2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Pin Configuration QFN-64, TQFP-64 CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 1 2 3 4 5 6 7 8 9 10 11 12 DVSSCLK DVDDCLK CLKP CLKN 49 48 47 46 45 44 QFN-64, TQFP-64 CDK2307 43 42 41 40 39 38 37 36 35 34 33 CLK_EXT 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Assignments Pin No. 1, 18, 23 2 3, 9, 12 4, 5, 8 6, 7 10, 11 13 14 15 16 17, 64 19 20 21 22 24, 41, 58 25, 40, 57 26 27 28 29 Pin Name DVDD CM_EXT AVDD AVSS IP0, IN0 IP1, IN1 DVSSCLK DVDDCLK CLKP CLKN DVSS CLK_EXT_EN DFRMT PD_N OE_N_1 OVDD OVSS D1_0 D1_1 D1_2 D1_3 Description Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog ground Analog input Channel 0 (non-inverting, inverting) Analog input Channel 1 (non-inverting, inverting) Clock circuitry ground Clock circuitry supply voltage, 1.8V Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground Digital circuitry ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active Mode to reset chip. Output Enable Channel 0. Tristate when high. I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. Ground for I/O ring Output Data Channel 1 (LSB, 13-bit output or 1Vpp full scale range ) Output Data Channel 1 (LSB, 12-bit output 2Vpp full scale range) Output Data Channel 1 Output Data Channel 1 CLK_EXT_EN Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Pin Assignments (Continued) Pin No. 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 60, 61 Pin Name D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 D1_10 D1_11 D1_12 ORNG_1 CLK_EXT D0_0 D0_1 D0_2 D0_3 D0_4 D0_5 D0_6 D0_7 D0_8 D0_9 D0_10 D0_11 D0_12 ORNG_0 OE_N_0 CM_EXTBC_1, CM_EXTBC_0 SLP_N_1, SLP_N_0 Description Output Data Channel 1 Output Data Channel 1 CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section) Output Data Channel 1 (MSB for 2Vpp full scale range) Out of Range flag Channel 1. High when input signal is out of range Output clock signal for data synchronization. CMOS levels. Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range) Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range) Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section) Output Data Channel 0 (MSB for 2Vpp full scale range) Out of Range flag Channel 0. High when input signal is out of range. Output Enable Channel 0. Tristate when low. Bias control bits for the buffer driving pin CM_EXT 00: Off 01: 50uA 10: 500uA 11: 1mA Sleep Mode 00: Sleep Mode 10: Channel 1 active 01: Channel 0 active 11: Both channels active 62, 63 Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters Parameter AVDD, AVSS DVDD, DVSS AVSS, DVSSCLK, DVSS, OVSS OVDD, OVSS CKP, CKN, DVSSCLK Analog inputs and outpts (IPx, INx, AVSS) Digital inputs Digital outputs Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -40 -60 J-STD-020 Typ Max 85 +150 Unit °C °C ESD Protection Product Human Body Model (HBM) QFN-64 2kV TQFP-64 2kV Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Gain Matching Conditions Min Typ Guaranteed Max Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters Midscale offset Full scale range deviation from typical Gain matching between channels. ±3 sigma value at worst case conditions. 12-bit level 12-bit level -6 1 6 ±0.5 ±0.2 ±0.6 VAVDD/2 LSB %FS %FS LSB LSB V VCM +0.2 V Vpp Vpp pF MHz DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range, Normal Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range, Differential input voltage range, 1V (see section Reference Voltages) Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VDVDD) 500 1.7 1.7 1.8 2.5 2.0 3.6 VCM -0.1 2.0 1.0 2.0 Full Scale Range, Option Input Capacitance Bandwidth Power Supply AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Electrical Characteristics - CDK2307A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 72.5 Max Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dB SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 71.5 72.2 72.1 71.6 72.4 SINAD Signal to Noise and Distortion Ratio 71 72 71.7 71.3 87 SFDR Spurious Free Dynamic Range 75 85 80 80 -90 HD2 Second order Harmonic Distortion -85 -95 -95 -95 -87 HD3 Third order Harmonic Distortion -75 -85 -80 -80 11.7 ENOB Effective number of Bits 11.5 11.7 11.6 11.6 -105 XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 20 15 11.6 1.8 2.9 2.4 20.9 9.2 30.1 9.9 20.5 9.2 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Electrical Characteristics - CDK2307B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 72.5 Max Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dB SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 71.9 72.7 72 70.8 71.7 SINAD Signal to Noise and Distortion Ratio 71 72.1 71.5 71.2 81 SFDR Spurious Free Dynamic Range 75 81 80 80 -90 HD2 Second order Harmonic Distortion -85 -95 -95 -90 -81 HD3 Third order Harmonic Distortion -75 -81 -80 -80 11.6 ENOB Effective number of Bits 11.5 11.7 11.6 11.5 -100 XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 40 20 21.1 3.3 5.3 4.4 38.0 16.9 54.9 9.7 36.1 14.2 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Electrical Characteristics - CDK2307C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 71.6 Typ 72.6 71.8 71.5 70.4 Max Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dB SNR Signal to Noise Ratio FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 70.5 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 75 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -85 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -75 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 11.4 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 71.7 71.7 71.7 70 81 84 79 77 -95 -95 -95 -95 -81 -84 -79 -79 11.6 11.6 11.5 11.3 -95 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 65 40 32.8 5.0 8.2 6.6 59.0 25.5 84.5 9.3 55.3 20.4 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Electrical Characteristics - CDK2307D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 70.4 Typ 72 71.7 71.2 70.7 Max Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dB SNR Signal to Noise Ratio FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 69.5 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 74 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -80 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -74 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 11.3 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 70.5 70.5 70.4 70.3 77 78 78 78 -95 -90 -90 -85 -77 -78 -78 -78 11.4 11.4 11.4 11.4 -95.0 SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 80 65 39.7 6.0 9.4 7.7 71.5 30 101.5 9.1 66.4 24.1 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet D i g i t a l a n d T i m i n g E l e c t r i c a l C h a ra c t e r i s t i c s (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, - 1 d B F S i n p u t s i g n a l , 5 p F c a p a c i t i ve l o a d , u n l e s s o t h e r w i s e n o t e d ) Symbol Clock Inputs Parameter Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance Conditions Min 20 Typ Max 80 Units CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters % high mVpp Vpp CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential From Power Down Mode to Active Mode From Sleep Mode to Active 1 0.8 0.5V 0.5V +0.24mV -0.24mV -0.5V < -0.5V 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 1000 0000 0000 Dx_12 = 1 & Dx_11 = 1 0111 1111 1111 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 D_12 = 0 & D_11 = 1 Rev 2B Dx_12 = 0 & Dx_11 = 0 1000 0000 0000 Dx_12 = 1 & Dx_11 = 0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet Mechanical Dimensions QFN-64 Package aaa C A A D D1 aaa C B ccc C A A2 A3 A1 Symbol A A1 A2 A3 b D D1 D2 E E1 E2 F G L e Min – 0.00 – 0.008 Inches Typ – 0.0004 0.026 0.008 REF 0.010 0.354 BSC 0.354 BSC 0.205 0.354 BSC 0.344 BSC 0.205 Max 0.035 0.002 0.028 0.012 Min – 0.00 – 0.2 Millimeters Typ – 0.01 0.65 0.2 REF 0.25 9.00 BSC 8.75 BSC 5.2 9.00 BSC 8.75 BSC 5.2 Max 0.9 0.05 0.7 0.30 CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters 0.197 0.213 5.0 5.4 0.197 0.05 0.0096 0.012 0° 0.213 5.0 5.4 – 0.6 0.5 12° E E1 1 aaa bbb ccc – – 1.3 – 0.0168 0.024 0.24 0.42 0.016 0.020 0.3 0.4 0.020 BSC 0.50 BSC – 12° 0° – Tolerance of Form and Position 0.10 0.004 0.10 0.004 0.05 0.002 Pin 1 ID 0.05 Dia. 1 bbb C A C seating plane NOTES: 1. All dimensions are in millimeters. 2. Die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. Dimensioning & tolerances conform to ASME y14.5m. -1994. 4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max 0.08mm. 8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring. 9. Applied only to terminals. 10. Package corners unless otherwise specipied are r0.175±0.025mm. bbb C B B 1.14 1.14 TOP VIEW Pin 1 ID Dia. 0.20 0.45 D2 F SIDE VIEW G E2 L e b 0.10 M C A B L BOTTOM VIEW Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 15 Data Sheet Mechanical Dimensions (Continued) TQFP-64 Package Symbol A A1 A2 D D1 E E1 R2 R1 1 2 3 Min – 0.002 0.037 c L L1 S b e D2 E2 aaa bbb ccc ddd 0.003 0.003 0° 0° 11° 11° 0.004 0.018 0.008 0.007 Inches Typ – – 0.039 0.472 BSC 0.393 BSC 0.472 BSC 0.393 BSC – – 3.5° – 12° 12° – 0.24 0.039 REF – 0.008 0.020 BSC 0.295 0.295 0.008 0.008 0.003 0.003 Max 0.047 0.006 0.041 Min – 0.05 0.95 0.008 – 7° – 13° 13° 0.008 0.030 – 0.011 0.08 0.08 0° 0° 11° 11° 0.09 0.45 0.20 0.17 Millimeters Typ – – 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC – – 3.5° – 12° 12° 0.20 0.75 1.00 REF – 0.20 0.520 BSC 7.50 7.50 0.20 0.20 0.08 0.08 Max 1.2 0.15 1.05 CDK2307 Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters 0.20 – 7° – 13° 13° – 0.27 TOP VIEW SIDE VIEW NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maxmum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 3. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. DETAIL SIDE VIEW Rev 2B For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e