CDK2308BILP64

Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters FEATURES n n n n n n n n n General Description The CDK2308 is a high performance, low power dual Analog-to-Digital Converters (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. 10-bit resolution 20/40/65/80MSPS maximum sampling rate Ultra-low power dissipation: 24/43/65/78mW 61.6dB SNR at 80MSPS and 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7V – 3.6V I/O supply voltage Parallel CMOS output 64-pin QFN package (TQFP-64 package option also available) Dual channel Pin compatible with CDK2307 n n APPLICATIONS n n n n Medical Imaging Portable Test Equipment IF Communication Digital Oscilloscopes Functional Block Diagram CLKN CLK_EXT 10 10 Ordering Information Part Number CDK2308AILP64 CDK2308BILP64 CDK2308CILP64 CDK2308DILP64 CDK2308AITQ64 CDK2308BITQ64 CDK2308CITQ64 CDK2308DITQ64 Speed 20MSPS 40MSPS 65MSPS 80MSPS 20MSPS 40MSPS 65MSPS 80MSPS Package QFN-64 QFN-64 QFN-64 QFN-64 TQFP-64 TQFP-64 TQFP-64 TQFP-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray Tray Tray Tray Tray Tray Tray CLKP Rev 2B Moisture sensitivity level for all parts is MSL-2A. Preliminary ©2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Pin Configuration QFN-64, TQFP-64 D0_5 D0_4 D0_3 CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 1 2 3 4 5 6 7 8 9 10 11 12 DVSSCLK DVDDCLK CLKP CLKN 49 48 47 46 45 44 N/C N/C N/C CLK_EXT QFN-64,TQFP-64 CDK2308 43 42 41 40 39 38 37 36 35 34 33 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N/C N/C Pin Assignments Pin No. 1, 18, 23 2 3, 9, 12 4, 5, 8 6, 7 10, 11 13 14 15 16 17, 64 19 20 21 22 24, 41, 58 25, 40, 57 Pin Name DVDD CM_EXT AVDD AVSS IP0, IN0 IP1, IN1 DVSSCLK DVDDCLK CLKP CLKN DVSS CLK_EXT_EN DFRMT PD_N OE_N_1 OVDD OVSS Description Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog ground Analog input Channel 0 (non-inverting, inverting) Analog input Channel 1 (non-inverting, inverting) Clock circuitry ground Clock circuitry supply voltage, 1.8V Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground Digital circuitry ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active mode to reset chip. Output Enable Channel 1. Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. Ground for I/O ring CLK_EXT_EN N/C Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Pin Assignments (Continued) Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 60, 61 Pin Name NC NC NC D1_0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 ORNG_1 CLK_EXT NC NC NC D0_0 D0_1 D0_2 D0_3 D0_4 D0_5 D0_6 D0_7 D0_8 D0_9 ORNG_0 OE_N_0 CM_EXTBC_1, CM_EXTBC_0 SLP_N_1, SLP_N_0 Description No Connect No Connect CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters No Connect Output Data Channel 1 (LSB) Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 (MSB) Out of Range flag Channel 1. High when input signal is out of range Output clock signal for data synchronization. CMOS levels. No Connect No Connect No Connect Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 (MSB) Out of Range flag Channel 0. High when input signal is out of range. Output Enable Channel 0. Tristate when low. Bias control bits for the buffer driving pin CM_EXT 00: Off 01: 50uA 10: 500uA 11: 1mA Sleep Mode 00: Sleep Mode 10: Channel 1 active 01: Channel 0 active 11: Both channels active Rev 2B 62, 63 ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Parameter AVDD, AVSS DVDD, DVSS AVSS, DVSSCK, DVSS, OVSS OVDD, OVSS CKP, CKN, DVSSCK Analog inputs and outpts (IPx, INx, AVSS) Digital inputs Digital outputs Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 Unit V V V V V V V V Reliability Information Parameter Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max +150 Unit °C ESD Protection Product Human Body Model (HBM) TQFP-64, QFN-64 2kV Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Gain Matching Conditions Min Typ Guaranteed Max Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Midscale offset Full scale range deviation from typical Gain matching between channels 12-bit level 12-bit level -6 1 6 ±0.05 ±0.15 ±0.2 VAVDD/2 LSB %FS %FS LSB LSB V VCM +0.2 V Vpp pF MHz DNL ILE VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 500 1.7 1.7 1.8 2.5 2 3.6 VCM -0.1 2 2 Power Supply AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V Rev 2B ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Electrical Characteristics - CDK2308A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.7 Max Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 20MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 60 61.6 61.6 61.6 61.7 SNDR Signal to Noise and Distortion Ratio 60 61.6 60.5 61.6 80 SFDR Spurious Free Dynamic Range 70 81 70 80 -90 HD2 Second order Harmonic Distortion -80 -90 -90 -90 -80 HD3 Third order Harmonic Distortion -70 -81 -70 -80 10 ENOB Effective number of Bits 9.7 9.9 9.8 9.9 -105 XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 20 15 8.2 1.7 2.8 2.3 14.8 8.8 23.6 9.9 15.2 7.7 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Electrical Characteristics - CDK2308B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 2MHz Min Typ 61.6 Max Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc SNR Signal to Noise Ratio FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN ≃ FS/2 FIN = 30MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 60 61.6 61.6 61.5 61.6 SNDR Signal to Noise and Distortion Ratio 60 61.6 61.2 61.4 80 SFDR Spurious Free Dynamic Range 70 81 72 80 -90 HD2 Second order Harmonic Distortion -80 -90 -85 -85 -80 HD3 Third order Harmonic Distortion -70 -81 -72 -80 9.9 ENOB Effective number of Bits 9.7 9.9 9.9 9.9 -100 XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 40 20 14.4 3.4 5.1 4.2 25.9 16.6 42.5 9.7 25.7 11.3 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Electrical Characteristics - CDK2308C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD=2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 60 Typ 61.6 61.6 61.5 61.3 Max Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc SNR Signal to Noise Ratio FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 60 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 70 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -80 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz -70 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz FIN = 8MHz 9.7 FIN = 20MHz FIN ≃ FS/2 FIN = 40MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 61.6 61.6 60.4 61.1 77 77 70 75 -90 -95 -85 -90 -77 -77 -70 -75 9.9 9.9 9.7 9.9 -97 SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 65 40 22 5.2 7.9 6.4 39.6 25.4 65 9.3 38.2 15.7 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Electrical Characteristics - CDK2308D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Performance Parameter Conditions FIN = 8MHz Min 60 Typ 61.6 61.2 61.3 61.3 Max Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc SNR Signal to Noise Ratio FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 60 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 70 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -80 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz -70 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 FIN = 8MHz 9.7 FIN = 20MHz FIN = 30MHz FIN ≃ FS/2 Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz 61.3 60.7 61 59 75 75 75 65 -90 -95 -90 -80 -75 -75 -75 -65 9.9 9.8 9.8 9.5 -95 SNDR Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range HD2 Second order Harmonic Distortion HD3 Third order Harmonic Distortion ENOB Effective number of Bits XTALK Crosstalk Power Supply AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 80 65 26.5 6.1 9.5 7.6 47.7 30 77.7 9.1 46.1 18.3 mA mA mA mA mW mW mW µW mW mW MSPS MSPS OIDD Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2 Rev 2B Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Clock Inputs Parameter Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance Conditions Min 20 Typ Max 80 Units CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters % high mVpp Vpp CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential From Power Down Mode to Active Mode From Sleep Mode to Active Mode 20 1 0.8