CDK8307CILP64

PRELIMINARY Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS FEATURES n n CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS General Description The CDK8307 is a high performance low power octal analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a serial control interface and serial LVDS output data, and is based on a proprietary structure. An integrated PLL multiplies the input sampling clock by a factor of 12 or 14, according to the LVDS output setting. The multiplied clock is used for data serialization and data output. Data and frame synchronization output clocks are supplied for data capture at the receiver. Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determines the exact function of this external pin. The CDK8307 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. The very low startup times of the CDK8307 allow significant power reduction in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when the receive path is idle. 20/40/50/65MSPS maximum sampling rate Low Power Dissipation – 22mW/channel at 20MSPS – 34mW/channel at 40MSPS – 40mW/channel at 50MSPS – 50mW/channel at 65MSPS 72.2dB SNR at 8MHz FIN 0.5μs startup time from Sleep 15μs startup time from Power Down Internal reference circuitry requires no external components Internal offset correction Reduced power dissipation modes available – 32mW/channel at 50MSPS – 71.5dB SNR at 8MHz FIN Coarse and fine gain control 1.8V supply voltage Serial LVDS output – 12- and 14-bit output available Package alternatives – TQFP-80 – QFN-64 n n n n n n n n n n Block Diagram RESETN SCLK SDATA AVDD AVSS DVDD DVSS LVDS FCLKP FCLKN LCLKP LCLKN D1N D1P D2N D2P LVDS LVDS CLKP CLKN CSN PD PLL Digital Gain Digital Gain APPLICATIONS n n n n Medical Imaging Wireless Infrastructure Test and Measurement Instrumentation IP1 IN1 IP2 IN2 Serial Control Interface ADC Clock Input ADC • • • IP8 IN8 ADC • • • Digital Gain • • • LVDS D8N D8P Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com PRELIMINARY Data Sheet Table of Contents Features .................................................................. 1 Applications ............................................................ 1 General Description ................................................ 1 Block Diagram ........................................................ 1 Table of Contents ................................................... 2 Ordering Information ............................................. 3 Pin Configurations .................................................. 4 Pin Assignments .................................................. 5-8 Absolute Maximum Ratings ................................... 9 Reliability Information ........................................... 9 ESD Protection ........................................................ 9 Recommended Operating Conditions .................... 9 Electrical Characteristics...................................... 10 Electrical Characteristics – CDK8307A ................ 10 Electrical Characteristics – CDK8307B ................ 11 Electrical Characteristics – CDK8307C ................ 11 Electrical Characteristics – CDK8307C Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data ............................... 18 Table 7. LVDS Internal Termination CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Programmability ....................................... 19 Table 8. Bit Clock Internal Termination .................... 19 Table 9. Analog Input Invert................................... 19 Table 10. LVDS Test Patterns .................................. 20 Table 11. Programmable Gain................................. 20 Table 12. Gain Setting for Channels 1-8 .................. 21 Table 13. LVDS Clock Programmability and Data Output Modes ................................. 21 Figure 6. Phase Programmability Modes for LCLK ..... 22 Figure 7. SDR Interface Modes ............................... 22 Table 14. Number of Serial Output Bits ................... 22 Table 15. Full Scale Control .................................... 23 Table 16. Register Values with Corresponding Charge in Full-Scale Range ...................... 23 Table 17. Clock Frequency ...................................... 23 Table 18. Clock Frequency Settings ......................... 23 Table 19. Performance Control................................ 24 Table 20. Performance Control Settings ................... 24 Table 21. External Common Mode Voltage Buffer Driving Strength ........................... 24 Theory of Operation ............................................. 25 Recommended Usage ........................................... 25 Analog Input ......................................................... 25 Figure 8. Input Configuration Diagram ................ 25 DC-Coupling.......................................................... 25 Figure 9. DC-Coupled Input ................................ 25 AC-Coupling .......................................................... 26 Figure 10. Transformer Coupled Input ................. 26 Figure 11. AC-Coupled Input .............................. 26 Figure 12. Alternative Input Network................... 26 Clock Input and Jitter Considerations ...................... 27 Mechanical Dimensions ................................... 28-29 QFN-64 Package.................................................... 28 TQFP-80 Package .................................................. 29 (Continued)........................................................... 12 Electrical Characteristics – CDK8307D................ 12 Digital and Timing Electrical Characteristics ...... 13 LVDS Timing Diagrams ......................................... 14 Figure 1. 12-bit Output, DDR Mode......................... 14 Figure 2. 14-bit Output, DDR Mode......................... 14 Figure 3. 12-bit Output, SDR Mode ......................... 14 Figure 4. Data Timing ............................................ 14 Serial Interface ..................................................... 15 Timing Diagram .................................................... 15 Figure 5. Serial Port Interface Timing Diagram ..... 15 Table 1. Serial Port Interface Timing Definitions ... 15 Register Initialization ............................................. 15 Serial Register Map .......................................... 16-17 Table 2. Summary of Functions Supported by Serial Interface ................................ 16-17 Description of Serial Registers ........................ 17-24 Table 3. Software Reset ......................................... 17 Table 4. Power-Down Modes .................................. 17 Table 5. LVDS Drive Strength Programmability ......... 18 Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 2 PRELIMINARY Data Sheet Ordering Information Part Number CDK8307AITQ80* CDK8307AILP64* CDK8307AILP64B2** CDK8307BITQ80* CDK8307BILP64* CDK8307BILP64B2** CDK8307CITQ80* CDK8307CILP64* CDK8307CILP64B2** CDK8307DITQ80* CDK8307DILP64* CDK8307DILP64B2** Speed 20MSPS 20MSPS 20MSPS 40MSPS 40MSPS 40MSPS 50MSPS 50MSPS 50MSPS 65MSPS 65MSPS 65MSPS Package TQFP-80 QFN-64 QFN-64 TQFP-80 QFN-64 QFN-64 TQFP-80 QFN-64 QFN-64 TQFP-80 QFN-64 QFN-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Tray Tray Tray Tray Tray Tray Tray Tray Tray Tray Moisture sensitivity level for all parts is MSL-3. *Preliminary. **Preliminary, pinout matches AD9222. Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 PRELIMINARY Data Sheet Pin Configurations QFN-64 RESETN SDATA OVDD AVDD AVDD AVDD CLKN SCLK CLKP AVSS VCM CSN NC NC NC NC QFN-64 (B2 Version: AD9222 Pinout Option) ACDD AVDD AVDD VCM IN2 IN1 IN8 IN7 IP2 IP1 IP8 IP7 NC NC NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 49 CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS IP1 IN1 AVSS IP2 IN2 AVSS IP3 IN3 AVSS IP4 IN4 DVSS PD DVSS D1P D1N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 17 18 19 20 21 22 23 24 25 26 27 28 29 32 48 47 46 45 44 IN8 IP8 AVSS IN7 IP7 AVSS IN6 IP6 AVSS IN5 IP5 AVSS DVSS DVDD D8N D8P AVDD IP3 IN3 AVDD IN4 IP4 AVDD AVDD CLKN CLKP AVDD AVDD DVSS DVDD D4N D4P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 17 18 19 20 21 22 23 24 25 26 27 28 29 32 48 47 46 45 44 AVDD IP6 IN6 AVDD IN5 IP5 AVDD PD CSN SDATA SCLK AVDD DCVSS DVDD D5P D5N CDK8307 QFN-64 43 42 41 40 39 38 37 36 35 34 33 CDK8307 QFN-64 43 42 41 40 39 38 37 36 35 34 33 FCLKP D3P D2P D1P D8P D7P LCLKP FCLKN D3N D2N D1N D8N D7N FCLKP FCLKN LCLKP LCLKN OVDD AVDD AVDD CLKN SCLK CLKP AVSS AVSS AVSS AVSS AVSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 AVDD IP1 IN1 AVSS IP2 IN2 AVDD AVSS IP3 IN3 AVSS IP4 IN4 AVDD DVSS PD DVSS DVSS LCLKP LCLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 AVSS VCM CSN NC NC NC NC NC TQFP-80 SDATA LCLKN D2P D3P D4P D5P D6P D2N D3N D4N D5N D6N D7P D7N 60 59 58 57 56 55 54 AVDD IN8 IP8 AVSS IN7 IP7 AVDD AVSS IN6 IP6 AVSS IN5 IP5 AVDD DVSS RESETN DVSS DVSS FCLKN FCLKP CDK8307 TQFP-80 53 52 51 50 49 48 47 46 45 44 43 42 41 33 34 35 37 38 39 21 22 23 24 25 26 27 28 29 30 31 32 36 40 D6N D6P Rev 0.4.0 D1P D2P D3P D4P D5P D6P D7P DVSS DVSS D1N D2N D3N D4N D5N D6N D7N D8P DVDD DVDD D8N ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 PRELIMINARY Data Sheet Pin Assignments Pin No. QFN-64 49, 50, 57 3, 6, 9, 37, 40, 43, 46, 52 1 2 4 5 7 8 10 11 38 39 41 42 44 45 47 48 12, 14, 36 35 13 15 16 17 18 19 20 21 22 27 28 29 30 31 32 33 34 23 24 25 26 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N FCLKP FCLKN LCLKP LCLKN Analog power supply, 1.8V Pin Name Description CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output LVDS bit clock, positive output LVDS bit clock, negative output Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. 51, 54, 55, 56 53 58 59 60 61 62 63 64 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 0 60 61 64 63 2 3 6 5 43 44 47 46 49 50 53 52 13, 36 14, 35 41 22 21 20 19 18 17 16 15 34 33 Pin Name NC VCM CLKP CLKN OVDD CSN SDATA SCLK RESETN Description Not connected Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input Reset SPI interface CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS QFN-64 (B2 version: AD9222 pinout option) AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N Analog power supply, 1.8V Analog ground (Exposed paddle, Pin 0, bottom of package) Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. 32 31 30 29 28 27 26 25 24 23 54 55 56 57 58 10 9 40 39 38 TQFP 1, 7, 14, 47, 54, 60, 63, 70 4, 8, 11, 50, 53, 57, 61, 68, 73, 74, 79, 80 2 3 5 6 9 10 12 13 48 49 51 52 55 56 58 59 15, 17, 18, 26, 36, 43, 44, 46 25, 35 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD Analog power supply, 1.8V Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Pin Name D6P D6N D7P D7N D8P D8N FCLKP FCLKN LCKP LCKN NC NC VCM NC NC CLKP CLKN CSN SDATA SCLK Description LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output LVDS frame clock (1X), positive output LVDS frame clock (1X), negative output LVDS bit clock, positive output LVDS bit clock, negative output Not connected Not connected Common mode output pin, 0.5*AVDD Not connected Not connected Positive differential input clock Negative differential input clock. Chip select enable. Active Low Serial data input Serial clock input CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 7 PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. 16 19 20 21 22 23 24 27 28 29 30 31 32 33 34 37 38 39 40 41 42 45 62, 64, 66, 67, 69 65 71 72 75 76 77 78 Pin Name PD LCKP LCKN D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N FCLKP FCLKN RESETN NC VCM CLKP CLKN OVDD CSN SDATA SCLK Description Power-down input LVDS bit clock, positive output LVDS bit clock, negative output LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output Reset SPI interface Not connected Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 PRELIMINARY Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Parameter AVDD DVDD OVDD AVSS, DVSS Analog inputs and outpts (IPx, INx) CLKx LVDS outputs Digital inputs Reference Pin AVSS DVSS AVSS DVSS / AVSS AVSS AVSS DVSS DVSS Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +3.9 +0.3 +2.3 +2.3 +2.3 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max TBD +150 Unit °C °C ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) QFN-64 TBD TBD TQFP-80 TBD TBD Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range from device failure to performance degradation. Analog circuitry may be more susceptible to damage as vary small parametric changes can result in specification noncompliance. Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 9 PRELIMINARY Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Gain Matching Conditions Min Typ Guaranteed Max Units CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS Offset error after digital offset cancellation -6 Gain matching between channels. ±3sigma value at worst case conditions. 12-bit level 12-bit level -0.5 1 6 0.5 ±0.2 ±0.6 VAVDD/2 LSB %FS %FS LSB LSB V VCM +0.2 V Vpp pF MHz DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth 500 1.7 Digital and output driver supply voltage 1.7 1.7 1.8 1.8 1.8 2.0 2.0 3.6 VCM -0.1 2.0 2 Power Supply AVDD DVDD OVDD Analog Supply Voltage Digital Supply Voltage Digital CMOS Input Supply Voltage V V V Electrical Characteristics - CDK8307A (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz Signal applied to 7 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz Min Typ 72.2 71.5 82 95 82 11.6 95 Max Units dBFS dBFS dBc dBc dBc bits dBc Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power dissipation with all chs in sleep mode Power dissipation savings per channel off 20 15 Digital and output driver supply 47 50 85 90 175 10 43 44 16 mA mA mW mW mW μW mW mW mW MSPS MSPS Rev 0.4.0 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate ©2009 CADEKA Microcircuits LLC www.cadeka.com 10 PRELIMINARY Data Sheet Electrical Characteristics - CDK8307B (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz Signal applied to 7 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz Min Typ 72.2 71.5 82 95 82 11.6 95 Max Units dBFS CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS dBFS dBc dBc dBc bits dBc Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power dissipation with all chs in sleep mode Power dissipation savings per channel off 40 20 Digital and output driver supply 91 60 164 108 272 10 67 72 23 mA mA mW mW mW μW mW mW mW MSPS MSPS Clock Inputs Maximum Conversion Rate Minimum Conversion Rate Electrical Characteristics - CDK8307C (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz Signal applied to 7 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz Min Typ 72.2 71.5 82 95 82 11.6 95 Max Units dBFS dBFS dBc dBc dBc bits dBc Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Digital and output driver supply 112 66 202 119 321 10 78 mA mA mW mW mW μW mW Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 11 PRELIMINARY Data Sheet Electrical Characteristics - CDK8307C Continued Symbol Parameter Sleep Channel Mode Dissipation Sleep Channel Mode Savings Conditions Power dissipation with all chs in sleep mode Power dissipation savings per channel off Min Typ 80 28 Max Units mW mW MSPS Clock Inputs Maximum Conversion Rate Minimum Conversion Rate 50 20 CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS MSPS Electrical Characteristics - CDK8307D (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz FIN = 8MHz Signal applied to 7 chs (FIN0). Measurement taken on one ch, full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz Min Typ 72.2 71.5 82 95 82 11.6 95 Max Units dBFS dBFS dBc dBc dBc bits dBc Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power dissipation with all chs in sleep mode Power dissipation savings per channel off 65 20 Digital and output driver supply 145 67 261 121 382 10 96 98 38 mA mA mW mW mW μW mW mW mW MSPS MSPS Clock Inputs Maximum Conversion Rate Minimum Conversion Rate Rev 0.4.0 ©2009 CADEKA Microcircuits LLC www.cadeka.com 12 PRELIMINARY Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted) Symbol Clock Inputs Duty Cycle Compliance Input range Input range Input common mode voltage Input capacitance Differential input swing Differential input swing, sine wave clock input Keep voltages within gnd and voltage of AVDD Differential VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V 2 0.8 • VOVDD 0 0 -10 -10 3 LVDS 247 1.125 Default/Optional 454 1.375 mV V 0.8 0.2 • VOVDD 10 10 20 200 800 0.3 2 80 200 800 VAVDD -0.3 %high mVpp mVpp V pF V V V V μA μA pF Parameter Conditions Min Typ Max Units CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS CMOS, LVDS, LVPECL Logic Inputs (CMOS) VIH VIL IIH IIL CI High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Input Capacitance Compliance VOUT VCM Digital Output Voltage Output Common Mode Voltage Output Coding Data Outputs (LVDS) Offset Binary/2‘s Complement 0.8