CDK8307EITQ80

Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS FEATURES n n CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS General Description The CDK8307 is a high performance low power octal analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a serial control interface and serial LVDS output data, and is based on a proprietary structure. An integrated PLL multiplies the input sampling clock by a factor of 12 or 14, according to the LVDS output setting. The multiplied clock is used for data serialization and data output. Data and frame synchronization output clocks are supplied for data capture at the receiver. Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determines the exact function of this external pin. The CDK8307 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. The very low startup times of the CDK8307 allow significant power reduction in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when the receive path is idle. 20/40/50/65/80MSPS max sampling rate Low Power Dissipation – 23mW/channel at 20MSPS – 35mW/channel at 40MSPS – 41mW/channel at 50MSPS – 51mW/channel at 65MSPS – 59mW/channel at 80MSPS 72.2dB SNR at 8MHz FIN 0.5μs startup time from Sleep 15μs startup time from Power Down Internal reference circuitry requires no external components Internal offset correction Reduced power dissipation modes available – 34mW/channel at 50MSPS – 71.5dB SNR at 8MHz FIN Coarse and fine gain control 1.8V supply voltage Serial LVDS output – 12- and 14-bit output available n n n n n n n n n Block Diagram RESETN SCLK SDATA AVDD AVSS DVDD DVSS LVDS FCLKP FCLKN LCLKP LCLKN D1N D1P D2N D2P LVDS LVDS CLKP CLKN CSN PD PLL Digital Gain Digital Gain n Package alternatives – TQFP-80 – QFN-64 APPLICATIONS n n n n Medical Imaging Wireless Infrastructure Test and Measurement Instrumentation IP2 IN2 IP1 IN1 Serial Control Interface ADC Clock Input ADC • • • IP8 IN8 ADC • • • Digital Gain • • • LVDS D8N D8P Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Table of Contents Features .................................................................. 1 Applications ............................................................ 1 General Description ................................................ 1 Block Diagram ........................................................ 1 Table of Contents ................................................... 2 Ordering Information ............................................. 3 Pin Configurations .................................................. 4 Pin Assignments .................................................. 5-8 Absolute Maximum Ratings ................................... 9 Reliability Information ........................................... 9 ESD Protection ........................................................ 9 Recommended Operating Conditions .................... 9 Electrical Characteristics...................................... 10 Electrical Characteristics – CDK8307A ............ 10-11 Electrical Characteristics – CDK8307B ................ 11 Electrical Characteristics – CDK8307C ............ 11-12 Electrical Characteristics – CDK8307D............ 12-13 Electrical Characteristics – CDK8307E ................ 13 Digital and Timing Electrical Characteristics .. 13-14 LVDS Timing Diagrams ......................................... 15 Figure 1. 12-bit Output, DDR Mode......................... 15 Figure 2. 14-bit Output, DDR Mode......................... 15 Figure 3. 12-bit Output, SDR Mode ......................... 15 Figure 4. Data Timing ............................................ 15 Serial Interface ..................................................... 16 Timing Diagram .................................................... 16 Figure 5. Serial Port Interface Timing Diagram ..... 16 Table 1. Serial Port Interface Timing Definitions ... 16 Register Initialization ............................................. 16 Serial Register Map .......................................... 17-18 Table 2. Summary of Functions Supported by Serial Interface ................................ 17-18 Description of Serial Registers ........................ 18-25 Table 3. Software Reset ......................................... 18 Table 4. Power-Down Modes .................................. 18 Table 5. LVDS Drive Strength Programmability ......... 19 Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data ............................... 19 Table 7. LVDS Internal Termination Programmability ....................................... 20 Table 8. LVDS Output Internal Termination .............. 20 Table 9. Analog Input Invert................................... 20 Table 10. LVDS Test Patterns .................................. 21 Table 11. Programmable Gain................................. 21 Table 12. Gain Setting for Channels 1-8 .................. 22 Table 13. LVDS Clock Programmability and Data Output Modes ................................. 22 Figure 6. Phase Programmability Modes for LCLK ..... 23 Figure 7. SDR Interface Modes ............................... 23 Table 14. Number of Serial Output Bits ................... 23 Figure 8. LVDS Output Timing Adjustment .............. 24 Table 15. Full Scale Control .................................... 24 Table 16. Register Values with Corresponding Charge in Full-Scale Range ...................... 25 Table 17. Clock Frequency ...................................... 25 Table 18. Clock Frequency Settings ......................... 25 Table 19. Performance Control................................ 25 Table 20. Performance Control Settings ................... 26 Table 21. External Common Mode Voltage Buffer Driving Strength ........................... 26 Theory of Operation ............................................. 27 Recommended Usage ........................................... 27 Analog Input ......................................................... 27 Figure 9. Input Configuration Diagram ................ 27 DC-Coupling.......................................................... 27 Figure 10. DC-Coupled Input .............................. 27 AC-Coupling .......................................................... 28 Figure 11. Transformer Coupled Input ................. 28 Figure 12. AC-Coupled Input .............................. 28 Figure 13. Alternative Input Network................... 28 Clock Input and Jitter Considerations ...................... 29 Mechanical Dimensions ................................... 30-31 QFN-64 Package.................................................... 30 TQFP-80 Package .................................................. 31 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Ordering Information Part Number CDK8307AITQ80 CDK8307AILP64 CDK8307BITQ80 CDK8307BILP64 CDK8307CITQ80 CDK8307CILP64 CDK8307DITQ80 CDK8307DILP64 CDK8307EITQ80 CDK8307EILP64 Speed 20MSPS 20MSPS 40MSPS 40MSPS 50MSPS 50MSPS 65MSPS 65MSPS 80MSPS 80MSPS Package TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Tray CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Tray Tray Tray Tray Tray Tray Tray Tray Moisture sensitivity level for QFN package is MSL-2A, for TQFP package is MSL-3. Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Pin Configurations QFN-64 RESETN SDATA OVDD AVDD AVDD TP AVSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD CLKN SCLK CLKP VCM CSN NC NC NC NC CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS IP1 IN1 AVSS IP2 IN2 AVSS IP3 IN3 AVSS IP4 IN4 DVSS PD DVSS D1P D1N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 17 18 19 20 21 22 23 24 25 26 27 28 29 32 48 47 46 45 44 IN8 IP8 AVSS IN7 IP7 AVSS IN6 IP6 AVSS IN5 IP5 AVSS DVSS DVDD D8N D8P CDK8307 QFN-64 43 42 41 40 39 38 37 36 35 34 33 FCLKP D2P D3P D4P D5P D6P FCLKN LCLKP D2N D3N D4N D5N D6N D7P OVDD AVDD AVDD CLKN SCLK CLKP AVSS AVSS AVSS AVSS AVSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 AVDD IP1 IN1 AVSS IP2 IN2 AVDD AVSS IP3 IN3 AVSS IP4 IN4 AVDD DVSS PD DVSS DVSS LCLKP LCLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 TP AVSS VCM CSN NC NC NC NC NC TQFP-80 SDATA LCLKN D7N 60 59 58 57 56 55 54 AVDD IN8 IP8 AVSS IN7 IP7 AVDD AVSS IN6 IP6 AVSS IN5 IP5 AVDD DVSS RESETN DVSS DVSS FCLKN FCLKP CDK8307 TQFP-80 53 52 51 50 49 48 47 46 45 44 43 42 41 33 34 35 37 38 39 21 22 23 24 25 26 27 28 29 30 31 32 36 40 Rev 1A D1P D2P D3P D4P D5P D6P D7P DVSS DVSS D1N D2N D3N D4N D5N D6N D7N D8P DVDD DVDD D8N ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Pin Assignments - QFN Pin No. QFN-64 49, 50, 57 3, 6, 9, 37, 40, 43, 46 1 2 4 5 7 8 10 11 38 39 41 42 44 45 47 48 12, 14, 36 35 13 15 16 17 18 19 20 21 22 27 28 29 30 31 32 33 34 23 24 25 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N FCLKP FCLKN LCLKP Analog power supply, 1.8V Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature. LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output LVDS bit clock, positive output Pin Name Description CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Pin Assignments QFN (Continued) Pin No. 26 51, 54, 55, 56 52 53 58 59 60 61 62 63 64 Pin Name LCLKN NC TP VCM CLKP CLKN OVDD CSN SDATA SCLK RESETN Description LVDS bit clock, negative output Not connected Test pin. Leave open (un-connected) or connect to GND. Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input Reset SPI interface CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Pin Assignments - TQFP Pin No. TQFP 1, 7, 14, 47, 54, 60, 63, 70 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 2 3 5 6 9 10 12 13 48 49 51 52 55 56 58 59 15, 17, 18, 26, 36, 43, 44, 46 25, 35 16 19 20 21 22 23 24 27 28 29 30 31 32 33 34 37 38 39 40 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD LCKP LCKN D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N Analog power supply, 1.8V Pin Name Description CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature. LVDS bit clock, positive output LVDS bit clock, negative output LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Pin Assignments - TQFP (Continued) Pin No. 41 42 45 61 62, 64, 66, 67, 69 65 71 72 75 76 77 78 Pin Name FCLKP FCLKN RESETN TP NC VCM CLKP CLKN OVDD CSN SDATA SCLK Description LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output Reset SPI interface Test pin. Leave open (un-connected) or connect to GND. Not connected Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Parameter AVDD DVDD OVDD AVSS, DVSS Analog inputs and outpts (IPx, INx) CLKx LVDS outputs Digital inputs Reference Pin AVSS DVSS AVSS DVSS / AVSS AVSS AVSS DVSS DVSS Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +3.9 +0.3 +2.3 +3.9 +2.3 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max TBD +150 Unit °C °C ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) QFN-64 2kV 500V Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit °C This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range from device failure to performance degradation. Analog circuitry may be more susceptible to damage as vary small parametric changes can result in specification noncompliance. Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Gain Matching Conditions Min Typ Guaranteed Max Units CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Offset error after digital offset cancellation 1 ±6 LSB %FS %FS LSB LSB V VCM +0.2 V Vpp pF MHz Gain matching between channels. ±3sigma value at worst case conditions. 12-bit level 12-bit level ±0.5 ±0.2 ±0.6 VAVDD/2 DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth 500 1.7 Digital and output driver supply voltage Digital and output driver supply voltage 1.7 1.8 1.7 1.8 1.8 1.9 1.8 2.0 2.0 2.0 3.6 VCM -0.1 2.0 2 Power Supply AVDD DVDD OVDD Analog Supply Voltage Digital Supply Voltage (up to 65MSPS) Digital Supply Voltage (above 65MSPS) Digital CMOS Input Supply Voltage V V V V Electrical Characteristics - CDK8307A (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 47 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW µW mW Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Power down mode Deep sleep mode Digital and output driver supply 54 84 97 180 10 30 Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet Symbol Parameter Sleep Channel Mode Dissipation Sleep Channel Mode Savings Conditions All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off Min Typ 46 17 Max Units mW mW MSPS Clock Inputs Maximum Conversion Rate Minimum Conversion Rate 20 15 MSPS CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Electrical Characteristics - CDK8307B (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 90 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW µW mW mW mW MSPS Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 40 20 Digital and output driver supply 67 162 120 280 10 41 71 26 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Electrical Characteristics - CDK8307C (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz Min 70 69 Typ 72.2 71.5 71.5 70.7 Max Units dBFS dBFS dBFS dBFS Rev 1A Signal to Noise Ratio Signal to Noise and Distortion Ratio ©2009 CADEKA Microcircuits LLC www.cadeka.com 11 Data Sheet Symbol SFDR HD2 HD3 ENOB Crosstalk Parameter Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 75 85 75 Typ 82 77 95 95 82 77 11.6 11.5 95 111 Max Units dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW µW mW mW mW MSPS CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 50 20 Digital and output driver supply 73 200 132 331 10 46 83 31 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Electrical Characteristics - CDK8307D (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 143 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW µW mW mW Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation ©2009 CADEKA Microcircuits LLC Digital and output driver supply 83 257 149 405 Rev 1A Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) 10 54 103 www.cadeka.com 12 Data Sheet Symbol Clock Inputs Maximum Conversion Rate Minimum Conversion Rate 65 20 MSPS MSPS Parameter Sleep Channel Mode Savings Conditions Power dissipation savings per channel off Min Typ 38 Max Units mW CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Electrical Characteristics - CDK8307E (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 68.5 68 74 85 75 Typ 70.1 70 69.6 69.5 77 76 90 90 77 76 11.3 11.3 95 173 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW µW mW mW mW MSPS Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 80 40 Digital and output driver supply 88 312 158 470 10 56 116 44 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted) Symbol Clock Inputs Duty Cycle Compliance Input range, differential Input range, sine Input range, CMOS Input common mode voltage Input capacitance Differential input swing Differential input swing, sine wave clock input CLKN connected to ground Keep voltages within gnd and voltage of OVDD Differential 0.3 2 20 ±200 ±800 VOVDD VOVDD -0.3 80 %high mVpp mVpp mVpp V pF CMOS, LVDS, LVPECL Parameter Conditions Min Typ Max Units Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 13 Data Sheet Symbol Parameter Conditions VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V Min 2 0.8 • VOVDD 0 0 Typ Max Units V V Logic Inputs (CMOS) VIH VIL IIH IIL CI High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Input Capacitance Compliance VOUT VCM Differential Output Voltage Output Common Mode Voltage Output Coding Default/Optional 350 1.2 Offset Binary/2‘s Complement 0.8