SPT5510

SPT5510 16-BIT, 200 MWPS ECL D/A CONVERTER FEATURES • • • • • • • 16-Bit, 200 MWPS digital-to-analog converter Differential linearity of ±0.6 LSB (typical) Integral linearity of ±0.75 LSB (typical) Fast settling time: 35 ns to 0.0008%; 25 ns to 0.01% Low glitch energy On-chip voltage reference ECL compatibility APPLICATIONS • • • • • • • High-precision arbitrary waveform generation Test and measurement instrumentation Digital waveform synthesis Microwave and satellite modems Disk drive test equipment Industrial process control Military applications GENERAL DESCRIPTION The SPT5510 is a 16-bit, 200 MWPS digital-to-analog converter designed for high-resolution waveform synthesis for test and measurement instrumentation applications. It features true 16-bit linearity, with differential non-linearity of typically ±0.6 LSB and integral non-linearity of ±0.75 LSB. It has a very high-speed update rate of up to 200 MHz and is ECL compatible. It has an ultrafast settling time of 25 ns to 0.01% and 35 ns to 0.0008%. The SPT5510 operates over an industrial temperature range of –40 °C to +85 °C and is available in a 10 x 10 mm, 44-lead metric quad flat pack (MQFP) plastic package. BLOCK DIAGRAM REFIN D15–D12 IOUT IOUT MSB Decoder 16 MSB Latch 16 IOUT Digital Inputs D15–D0 16 Input Latch LSB Buffer 12 LSB Latch 12 Bias D11–D0 CLK BGOUT Current Cells IOUT Bandgap Reference Bias RSET AMPINB + – Ref Amp Reference Cell 20 AMPOUT 10 AMPCC ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 Supply Voltages Negative supply voltage (VEE) ................................. –7 V A/D ground voltage differential ................................ 0.5 V Input Voltages Digital input voltage (D15–D0, Clock)... ........... –2.5 to 0 V Ref amp input voltage range .......................... –2.5 to 0 V Reference input voltage range (Ref In) ...... VEE to –2.5 V Output Currents Bandgap reference output current ..................... ±500 µA Ref amplifier output current ................................ ±2.5 mA Temperature Operating temperature ............................... –40 to +85 °C Junction temperature .......................................... +150 °C Lead, soldering (10 seconds) ............................. +250 °C Storage .................................................... –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal operating conditions. ELECTRICAL SPECIFICATIONS TA= 25 °C, VEE=–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. PARAMETERS DC Performance1 Resolution Differential Linearity Differential Linearity Integral Linearity Integral Linearity Integral Linearity Drift Offset Drift Monotonicity Output Capacitance Gain Error Gain Error Tempco Gain Error Tempco Offset Error Compliance Voltage Output Resistance Dynamic Performance Conversion Rate Settling Time tST2 TEST CONDITIONS TEST LEVEL MIN SPT5510 TYP 16 ±0.6 ±1.0 ±0.75 ±1.5 MAX UNITS Bits LSB LSB LSB LSB LSB/°C ppm FS/°C Bits pF % FS ppm FS/°C ppm FS/°C µA V kΩ MHz TMIN–TMAX TMIN–TMAX TMIN–TMAX With Ext Reference With Internal Bandgap Ref VI IV VI IV IV IV V V I V V I IV IV IV –1.95 –4.0 –1.95 –4.0 –0.2 –2.5 15 –2 1.95 4.0 1.95 4.0 0.2 2.5 10 0.4 50 50 2 –4 –1.2 0.88 200 1.1 4 2 1.32 Settling to ±0.01% Settling to ±0.0008% Delay Time tD Glitch Energy Full Scale Output Current Rise Time/Fall Time Spurious Free Dynamic Range ƒOUT=5 MHz; ƒCLOCK=30 MHz ƒOUT=10 MHz; ƒCLOCK=100 MHz 1Measured 2Measured With On-Chip References RL = 50 Ω 10 MHz Span 10 MHz Span V V V V V V V V 25 35 2 30 19 2 84 76 ns ns ns pV-s mA ns dB dB at 0 V output using I-V. as voltage settling for mid-scale transition; RL = 50 Ω. SPT5510 2 9/27/00 ELECTRICAL SPECIFICATIONS TA= 25 °C, VEE=–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. TEST PARAMETERS Power Supply Requirements Negative Supply Current (–5.2 V) Nominal Power Dissipation Power Supply Rejection Ratio Voltage Input and Control Bandgap Reference Voltage Bandgap Output Current Ref Amp Bandwidth3 Ref Amp Input Current Ref Amp Output Current Ref In Operating Voltage Digital Inputs Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Clock Pulse Width (tPWH) 3Ref TEST LEVEL VI V I V IV V V V V VI VI V V V IV IV IV MIN SPT5510 TYP 115 600 ±0.002 –1.2 16 40 16 200 –3.4 –0.8 –1.7 2.5 0 3 MAX 150 800 0.6 UNITS mA mW % FS V µA MHz µA µA V V V µA µA pF ns ns ns CONDITIONS TMIN –TMAX ∆V Supply = ±5 % –0.6 TA=25 °C ±10 °C –110 220 TMIN –TMAX TMIN –TMAX –0.8 V –1.8 V –1.0 –1.5 3.0 0.5 1.5 Amp Bandwidth is limited by its compensation network TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT5510 3 9/27/00 THEORY OF OPERATION The SPT5510 is a segmented 16-bit current-output DAC. The four MSBs, D15–D12, are decoded to fifteen unit cells (current sinks). The remaining bits (D11–D0) are binary; bits D9–D0 are derived from an R-2R ladder. All cells are laser trimmed for maximum accuracy. The block diagram shows the basic architecture. All output cells are always on, with the data determining whether a given cell’s current is routed from IOUT or IOUT. This provides nearly constant power dissipation independent of data and clock rate. It also reduces noise transients on power and ground lines. The reference loop utilizes an MSB-weighted cell and provides a gain of about 16 to the output. The on-chip reference amplifier has very high open-loop gain and is offset trimmed to provide a very low temperature drift (typically