SPT7610SIQ

SPT7610 6-BIT, 1 GSPS FLASH A/D CONVERTER JANUARY 21, 2002 FEATURES • 1:2 demuxed ECL-compatible outputs • 1.0 GSPS conversion rate • Wide input bandwidth: 1.4 GHz • Low input capacitance: 8 pF • Metastable errors reduced to 1 LSB • Monolithic construction • Binar y/Two’s complement output APPLICATIONS • Radar, EW, ECM • Direct RF down-conversion • Microwave modems • Industrial ultrasound • Transient capture • Test and measurement GENERAL DESCRIPTION The SPT7610 is a full parallel (flash) analog-to-digital conver ter capable of digitizing full-scale (0 to –1 V) inputs into six-bit digital words at an update rate of 1 GSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data-ready outputs to ease the task of data capture. The SPT7610’s wide input bandwidth and low capacitance eliminate the need for exter nal track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7610 operates from a single –5.2 V supply, with a nominal power dissipation of 2.75 W. The SPT7610 is available in a 44L her metic cerquad surface-mount package in the industr ial temperature range (–40 °C to +85 °C). BLOCK DIAGRAM Analog V RT Input Preamp Comparator 64 CLK CLK CLOCK BUFFER DEMUX CLOCK BUFFER 63 64 TO 6 BIT DECODER WITH METASTABLE ERROR CORRECTION D6B D6 (OVR) D5 (MSB) D5B 49 TESTABILITY TEST ECL OUTPUT BUFFERS AND LATCHES D4B D3B D2B D1B V R3 48 33 1:2 DEMULTIPLEXER D4 D0B V RM 32 D3 DRB (DATA READY) DRB (DATA READY) D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) BANK B D6A D5A D4A D3A D2A D1A 17 D2 BANK A V R1 16 D1 2 DO (LSB) D0A MINV LINV 1 VRB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Negative Supply Voltage (AVEE TO GND) . –7.0 to +0.5 V Ground Voltage Differential ........................ –0.5 to +0.5 V Input Voltage Analog Input Voltage ................................ +0.5 V to AVEE Reference Input Voltage ........................... +0.5 V to AVEE Digital Input Voltage .................................. +0.5 V to AVEE Reference Current VRT to VRB ............................ +20 mA Output Digital Output Current ................................... 0 to –25 mA Temperature Operating Temperature, Ambient ............... –40 to +85 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVEE = –5.2 V, VRB = –1.00 V, VRM = –0.5 V, VRT = 0.00 V, ƒCLK = 1000 MSPS, Duty Cycle = 50%, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Linearity Differential Linearity No missing codes Analog Input Offset Error VRT Offset Error VRB Input Voltage Range Input Capacitance Input Resistance Input Bias Current Bandwidth Input Slew Rate Clock Synchronous Input Currents Power Supply Requirements Supply Current Power Dissipation Reference Inputs Ladder Resistance Reference Bandwidth Digital Outputs Digital Output High Voltage Digital Output Low Voltage Digital Inputs Digital Input High Voltage (CLK, NCLK) Digital Input Low Voltage (CLK, NCLK) Clock Input Swing (CLK, NCLK) Maximum Sample Rate Clock Low Width, TPW0 Clock High Width, TPW1 TEST CONDITIONS TEST LEVEL MIN 6 SPT7610 TYP MAX UNITS Bits VI VI VI VI VI VI V V VI V V V VI VI VI V R1 = 50 Ω to –2 V R1 = 50 Ω to –2 V VI VI –0.5 –0.5 Guaranteed –30 –30 –1 8 50 200 1.4 5 2 550 2.85 60 80 100 –0.9 –1.8 +0.5 +0.5 LSB LSB +30 +30 0.0 400 Over Full Input Range Small Signal mV mV Volts pF kΩ µA GHz V/ns µA mA W Ω MHz Volts Volts 770 4.0 120 –1.2 –1.5 VI VI IV VI VI VI –1.1 –2.0 100 1000 0.5 0.5 700 1200 0.4 0.4 –0.7 –1.5 Volts Volts mV MSPS ns ns SPT7610 2 1/21/02 ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVEE = –5.2 V, VRB = –1.00 V, VRM = –0.5 V, VRT = 0.00 V, ƒCLK = 1000 MSPS, Duty Cycle = 50%, unless otherwise specified. PARAMETERS Timing Characteristics Clock to Data Ready delay (tdr) Data Bank A Data Bank B Clock to Output Data (tod) Data Bank A Data Bank B Output Data to Data Ready (todr) Data Bank A Data Bank B Output Data Skew (tosk) Aperture Jitter Acquisition Time TEST CONDITIONS TEST LEVEL MIN SPT7610 TYP MAX UNITS +25 °C case +25 °C case +25 °C case +25 °C case –40 to 85 °C case –40 to 85 °C case –40 to 85 °C case V V V V IV IV IV V V 1.68 1.73 2.14 2.00 1.54 1.73 –150 2 250 150 ns ns ns ns ns ns ps ps ps Dynamic Performance Spurious Free Dynamic Range (SFDR) ƒIN = 250 MHz ƒIN = 400 MHz Signal-to-Noise and Distortion (SINAD) ƒIN = 250 MHz ƒIN = 400 MHz Signal to Noise Ratio (SNR) ƒIN = 250 MHz ƒIN = 400 MHz Total Harmonic Distortion (THD) ƒIN = 250 MHz ƒIN = 400 MHz V V VI VI VI VI VI VI 31 28 33 32 45 34 34 32 36 36 –40 –34 –37 –30 dB dB dB dB dB dB dB dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT7610 3 1/21/02 GENERAL OVERVIEW The SPT7610 is an ultra high-speed monolithic 6-bit parallel flash A/D converter. The nominal conversion rate is 1 GSPS, and the analog bandwidth is typically 1.4 GHz. A major advance over previous flash converters is the inclusion of 64 input preamplifiers between the reference ladder and input comparators. (See the block diagram.) This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges. This makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7610 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 Ω loads. Only one –5.2 V power supply is required. Two external references are applied across the internal reference ladder that has a resistance of 80 Ω typical (60 Ω minimum). The top reference is typically 0 V or connected to AGND (analog ground). The device has top force and sense pins (VRFT and VRST) that are internally connected together. These voltage force and sense pins can be used to minimize the voltage drop across the parasitic line resistance. The bottom reference is typically –1 V. The device also has bottom force and sense pins (VRFB and VRSB) that are internally connected together. These can also be used to minimize the voltage drop across the parasitic line resistance. Three additional reference taps (VR3 = –0.25 V typ, VRM = –0.5 V typ, and VR1 = –0.75 V typ) are brought out. These taps can be used to control the linearity error. All logic levels are compatible with both 10K ECL or 100K ECL. It is recommended that the clock input be driven differentially (CLK and NCLK) to improve noise immunity and reduce aperture jitter. The digital outputs are split into two banks of 6-bit words and an overrange bit. Each bank is updated at 1/2 of the clock rate and is 180° out of phase from the other. The differential data ready signals for each bank are provided to accurately latch each data bank into the register. The output data is in a straight binary, inverted binary, two’s complement or inverted two’s complement format. Figure 1 shows a timing diagram of the device and shows the input-to-output relationship, clock-to-output delay and output latency. The SPT7610 has a built-in offset in the ÷2 clock divider (D Flip-Flop) to assure that output bank A will come up first after power turn on. SPT7610 4 1/21/02 Figure 1 – Timing Diagram 1 nsec N+1 N+2 N+5 N+3 N+4 VIN N CLK (1 GHz) tdrA DRA DRA N–2 OutputA Skew (toskA) todA Data Bank A N DOA–DRA Delay (todrA) N+2 todB tdrB DRB DRB Data Bank B N–3 OutputB Skew (toskB) N–1 N+1 DOB–DRB Delay (todrB) Figure 2 – Test Mode Timing Diagram FIRST POWER RISING EDGE ON 1 2 VIN 8 7 6 3 5 4 9 10 11 CLK IN LOGIC LOW TEST ADC (Normal Operation) tsu TEST MODE ADC (Normal Operation) DRA tdr NDRA tod OUTPUT BANK A (DA0-6) DRB INVALID DATA INVALID DATA 1 Bank A Test Pattern 1: - Even Bits = Hi - Odd Bits = Low Bank A Test Pattern 2: - Even Bits = Low - Odd Bits = Hi 7 9 tdr NDRB tod OUTPUT BANK B (DB0-6) INVALID DATA INVALID DATA 2 Bank B Test Pattern 1: - Even Bits = Hi - Odd Bits = Low Bank B Test Pattern 2: - Even Bits = Low - Odd Bits = Hi 8 SPT7610 5 1/21/02 Figure 3 – Typical Interface Circuit VIN** 50 W VIN VIN DRB DRB DRA VRTF R VRTS DRA DRB (DATA READY) DRB (DATA READY) DRA (DATA READY) DRA (DATA READY) D6B (OVR) D5B (MSB) D4B D3B D2B D1B D0B (LSB) D6A (OVR) D5A (MSB) D4A D3A D2A D1A D0A (LSB) + – R –2.0 V Reference Convert U1 22 W * * * VR3 VRM VR1 VRBS VRBF 50 W 50 W SPT7610 U1 22 W 2N2907 –5.2 V U2 AGND DGND AVEE TYPICAL INTERFACE CIRCUIT The typical interface circuit is shown in figure 3. External reference taps are provided for correcting integral nonlinearity errors. These taps can be actively driven to reduce these errors. (See the Reference Inputs discussion below.) The SPT7610 evaluation board application note contains more details on interfacing the SPT7610. The function of each pin and external connections to other components is as follows: POWER SUPPLY PINS: AVEE, AGND, DGND AVEE is the supply pin with AGND as ground for the device. The AVEE power supply pin should be bypassed as close to the device as possible with a 10 µF tantalum capacitor, in parallel with 100 pF and .01 µF chip capacitors. Place the 100 pF chip capacitor closest to the SPT7610. Digital ground (DGND) is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 3. + – * –5.2 V CLK NCLK 50 W 50 W MINV LINV Test –5.2 V –5.2 V –5.2 V .1 µF FB = Ferrite bead –2.0 V Pulldown (Digital) U1 = TLV2464 or equivalent with low offset/noise. R = 1 kW; 0.05% matched or better = AGND –2 V Pulldown (Analog) –5.2 V * FB = DGND U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver. * = 2.2 µF Tantalum Capacitor, 0.1 µF and 100 pF chip capacitors. ** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. ANALOG INPUT: VIN There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7610 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. CLOCK INPUTS: CLK, NCLK The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. SPT7610 6 1/21/02 DIGITAL OUTPUTS: D0 TO D6, DR, NDR (A AND B) The digital outputs can drive 50 Ω to ECL levels when pulled down to –2 V. When pulled down to –5.2 V, the outputs can drive 130 Ω to 1 kΩ loads. CADEKA recommends SPT7610 TEST MODE FUNCTION: TEST PIN using differential receivers on the outputs of the data The SPT7610 suppor ts a special test mode function that ready lines to ensure the proper output rise and fall times. overrides the SPT7610’s internal data output latch stage BINARY AND TWO’S COMPLEMENT OUTPUT: and exercises the digital outputs in an alter nating test patMINV, LINV ter n. This enables the user to test digital interface logic downstream from the SPT7610 with a known set of digital Control pins are provided that enable selection of one of test patterns. four digital output for mats. (Table I shows selection of these output formats as a function of the MINV and LINV Test mode pin 3 controls the SPT7610 mode of operation pins.) When the MINV pin is high, the MSB output is in- such that when it is low, the SPT7610 operates in normal ver ted and when it is low, the it is noninver ted. Likewise, mode. When test mode pin 3 is brought high, the when the LINV pin is high, the LSB output is inver ted and SPT7610 will begin to output test pattern 1 (table II) on the when it is low, the it is noninver ted. The user can select next rising edge of the clock. (See figure 2.) It will output either binar y, inver ted binar y, two’s complement or the test patter ns alter nating between test pattern 1 and inver ted two’s complement digital output format. test pattern 2 as long as test mode pin 3 is held high. The minimum set-up time (tsu) can be as low as 0 nsec. REFERENCE INPUTS: VRBF, VRBS, VR1, VRM, VR3, VRTF, VRTS Only the digital output stage is involved in the test mode operation. All ADC stages before the digital output stage There are two reference inputs and three external refercontinue normal data conversion operation while the test ence voltage taps. These are –1.0 V VRBF (bottom force) mode is active. When test mode pin 3 is brought back low, and VRBS (bottom sense), –0.75 V VR1 (1/4 tap), –0.5 V the SPT7610 will resume output of valid data on the next VRM (mid-point tap), –0.25 V VR3 (3/4 tap) and 0.0 V rising edge of the clock. The valid data output will corre(AGND) VRTF (top force) and VRTS (top sense). The top refspond to a two-clock-cycle pipeline delay as shown in erence pin is normally tied to analog ground (AGND) and figure 2. the bottom reference pin can be driven by an op amp as Table II – SPT7610 Test Mode Output Bit Patterns shown in figure 3. The reference voltage taps can be used to control integral linear ity over temperature. The mid-point reference tap (VRM) is normally driven by an op amp to insure temperature stable operation or may be bypassed for limited temperature operation. The 1/4 (VR1) and 3/4 (VR3) reference Table I – Output Coding Table TRUE MINV=LINV=0 ANALOG INPUT VOLTAGE –1 V + 1/2 LSB D6 0 0 –0.5 V 0 D5_______D0 000000 000001 0111111 100000 0 V – 1/2 LSB 0 1 0V 1 Tie ladder taps are typically bypassed to add noise suppression as shown in figure 3 or may be driven with op amps to adjust integral linearity. D6 Test Pattern 1 Test Pattern 2 1 0 D5 0 1 D4 1 0 D3 0 1 D2 1 0 D1 0 1 D0 1 0 BINARY INVERTED TWOs COMPLEMENT TRUE INVERTED MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1 D5______D0 111111 111110 100000 011111 000000 000000 000000 V.) D5______D0 1000000 1000001 111111 000000 011111 011111 011111 D5______D0 0111111 0111110 000000 111111 100000 100000 100000 111111 111111 111111 1 MINV/LINV to GND for logic 1. 2 Float MINV/LINV for logic 0. (MINV/LINV are inter nally pulled down to –5.2 SPT7610 7 1/21/02 THERMAL MANAGEMENT Adequate heat sinking and air flow must be provided to keep the die temperature below +150 °C. This device is packaged with the cavity up (the die is on the bottom of the package). Therefore, CADEKA recommends that the device be heat sinked by contacting the bottom of the package through a hole in the circuit board. The ther mal coefficients of the SPT7610 (44L cerquad) are as follows: θja = +78 °C/W (junction to ambient in still air with no heat sink) θjc = +4 °C/W (junction to case) SUBCIRCUIT SCHEMATICS Figure 3A – Input Circuit AGND AGND DGND Figure 3B – Output Circuit Figure 3C – Clock Input AGND VIN Vr CLK Data Out CLK AVEE AVEE SPT7610 8 1/21/02 PACKAGE OUTLINE 44-Lead Cerquad INCHES SYMBOL C MILLIMETERS MIN 17.40 0.94 MAX 18.00 1.04 14.0 typ MIN 0.685 0.037 MAX 0.709 0.041 A B C A B 0.551 typ D D E F G H 0.016 typ 0.008 typ 0.027 0.080 0.051 0.150 0.006 typ 0.41 typ 0.20 typ 0.69 2.03 1.30 3.81 0.15 typ A B 0–5° H E F G SPT7610 9 1/21/02 PIN ASSIGNMENTS AGND VRM VR1 AVEE VRBF VR3 AGND VIN VIN VRTF AVEE 33 32 31 30 PIN FUNCTIONS Name AVEE AGND VRTF VRTS AGND CLK NCLK AGND LINV AVEE DRB NDRB D0B D1B Function Negative Supply; nominally –5.2 V Analog Ground Reference Voltage Force Top; nominally 0 V Reference Voltage Sense Top Reference Voltage Middle; nominally –0.5 V Reference Voltage Force Bottom; nominally –1.0 V Reference Voltage Sense Bottom Analog Input Voltage; can be either Voltage or Sense Digital Ground Data Output Bank A Data Output Bank B Data Ready Bank A Not Data Ready Bank A Data Ready Bank B Not Data Ready Bank B Overrange Output Bank A Overrange Output Bank B Clock Input Clock Input MSB Control Pin LSB Control Pin Test Control Pin Reference Voltage 1/4, nominally –0.75 V Reference Voltage 3/4, nominally –0.25 V 44 43 42 41 40 39 38 37 36 35 34 VRBS MINV Test AGND AVEE D6A D5A D4A D3A DGND D2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VRTS VRM VRBF VRBS VIN DGND D0–D5A D0–D5B DRA NDRA DRB NDRB D6A D6B CLK NCLK MINV LINV TEST VR1 VR3 SPT7610 Top View 29 28 27 26 25 24 23 ORDERING INFORMATION PART NUMBER SPT7610SIQ TEMPERATURE RANGE –40 to +85 °C PACKAGE 44L Cerquad DGND D2B D3B D4B D5B D6B DGND DRA NDRA D0A D1A SPT7610 10 1/21/02