SPT7725BIJ

SPT7725 8-BIT, 300 MSPS, FLASH A/D CONVERTER TECHNICAL DATA AUGUST 17, 2001 FEATURES • Metastable errors reduced to 1 LSB • Low input capacitance: 10 pF • Wide input bandwidth: 210 MHz • 300 MSPS conversion rate • Typical power dissipation: 2.2 watts APPLICATIONS • Digital oscilloscopes • Transient capture • Radar, EW, ECM • Direct RF down-conversion • Medical electronics: ultrasound, CAT instrumentation of 2.2 W. A proprietar y decoding scheme reduces metastable errors to the 1 LSB level. The SPT7725 is available in 42-lead ceramic sidebrazed DIP, surface-mount 44-lead cerquad, and 46-lead PGA packages (all are pin-compatible with the SPT7710); the cerquad and PGA packages allow access to additional reference ladder taps, an overrange bit, and a data ready output. The SPT7725 is available in the industrial temperature range. GENERAL DESCRIPTION The SPT7725 is a monolithic flash A/D conver ter capable of digitizing a two volt analog input signal into 8-bit digital words at a 300 MSPS (typ) update rate. For most applications, no external sample-and-hold is required for accurate conversion due to the device’s narrow aper ture time, wide bandwidth, and low input capacitance. A single standard –5.2 volt power supply is required for operation of the SPT7725, with nominal power dissipation BLOCK DIAGRAM VRTS VRTF Analog Input (Force or Sense) AGND DGND VEE LINV MINV Preamp 256 Comparator DRINV MSB D7 DREAD Clock Buffer 255 VR3 152 Overrange 151 D7 MSB 128 VR2 127 D6 256 to 8-Bit Encoder D6 ECL Latches and Buffers D5 D4 64 D5 VR1 63 D4 D3 2 D2 D1 D0 LSB VRBF VRBS Convert CLK CLK 2 LSB D0 D1 D2 D3 These functions are available in the PGA and cerquad packages only. 1 Analog Input (Sense or Force) VEE AGND ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V Ground Voltage Differential .................... –0.5 to +0.5 V Input Voltage Analog Input Voltage ............................... VEE to +0.5 V Reference Input Voltage .......................... VEE to +0.5 V Digital Input Voltage ................................ VEE to +0.5 V Reference Current VRTF to VRBF ........................ 25 mA Output Digital Output Current ............................... 0 to –30 mA Temperature Operating Temperature,ambient ............. –25 to +85 °C junction ...................... +150 °C Lead Temperature, (soldering 10 seconds) ..... +300 °C Storage Temperature ............................ –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA= TMIN to TMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00 V, VR2=–1.00 V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified. PARAMETERS DC Accuracy Integral Linearity Error Differential Linearity Error No missing codes Analog Input Offset Error VRT Offset Error VRB Input Voltage Range Input Capacitance Input Resistance Input Current Input Slew Rate Large Signal Bandwidth Small Signal Bandwidth Clock Synchronous Input Currents Reference Input Ladder Resistance Reference Bandwidth Timing Characteristics Maximum Sample Rate Clock to Data Delay Output Delay Tempco CLK-to-Data Ready Delay (tD) Aperture Jitter Acquisition Time Dynamic Performance Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion (SINAD) TEST CONDITIONS ƒCLK = 100 kHz ƒCLK = 100 kHz TEST LEVEL VI VI MIN SPT7725A TYP MAX MIN –0.95 –0.95 SPT7725B TYP MAX ±0.80 Guaranteed +0.95 +0.95 UNITS LSB LSB –0.75 ±0.60 +0.75 –0.75 +0.75 Guaranteed –30 –30 –2.0 10 15 250 1,000 210 335 40 100 200 10 300 2.4 2 2.0 5 1.5 47 42 –52 –43 46 39 300 +30 +30 0.0 VI VI VI Over full input range V V VI V V V V VI V IV V V V V V ƒIN = 3.58 MHz ƒIN = 50 MHz ƒIN = 3.58 MHz ƒIN = 50 MHz ƒIN = 3.58 MHz ƒIN = 50 MHz VI VI VI VI VI VI –30 –30 –2.0 10 15 250 1,000 210 335 40 100 200 10 300 2.4 2 2.0 5 1.5 46 41 –50 –42 44 37 +30 +30 0.0 mV mV Volts pF kΩ µA V/µs MHz MHz µA 500 500 VIN=F.S. VIN=500 mVP-P 300 Ω MHz MSPS ns ps/°C ns ps ns dB dB dB dB dB dB 250 250 45 39 44 37 44 38 –48 –40 42 35 –46 –39 SPT7725 2 8/17/01 ELECTRICAL SPECIFICATIONS TA= TMIN to TMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00 V, VR2=–1.00 V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified. PARAMETERS Digital Inputs Digital Input High Voltage (MINV, LINV) Digital Input Low Voltage (MINV, LINV) Clock Low Width, tPWL Clock High Width, tPWH Digital Outputs Digital Output High Voltage Digital Output Low Voltage Power Supply Requirements Supply Current Power Dissipation TEST CONDITIONS TEST LEVEL MIN SPT7725A TYP MAX MIN SPT7725B TYP MAX UNITS VI VI VI VI 50 Ω to –2 V 50 Ω to –2 V +25 °C +25 °C VI VI VI VI –1.1 –2.0 2.2 2.2 –1.1 2.0 2.0 –0.7 –1.5 –1.1 –2.0 2 2 –1.1 1.8 1.8 –0.7 –1.5 Volts Volts ns ns Volts Volts mA W –1.5 425 2.2 550 2.9 425 2.2 –1.5 550 2.9 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT7725 3 8/17/01 TYPICAL PERFORMANCE CHARACTERISTICS SNR vs Input Frequency 52 50 48 75 70 65 60 55 50 45 40 35 30 THD vs Input Frequency ƒS = 250 MSPS ƒS = 250 MSPS 46 44 42 40 38 36 34 1 10 100 Total Harmonic Distortion (dB) Signal-to-Noise Ratio (dB) 1 10 100 Input Frequency (MHz) Input Frequency (MHz) SINAD vs Input Frequency 52 50 50 SNR, THD, SINAD vs Temperature ƒS = 250 MSPS ƒIN = 100 MHz Signal-to-Noise and Distortion (dB) 48 46 44 42 40 38 36 34 ƒS = 250 MSPS SNR, THD, SINAD (dB) 45 THD SNR SINAD 40 35 1 10 100 30 Input Frequency (MHz) –40 –20 0 20 40 60 80 Temperature (°C) SPT7725 4 8/17/01 Figure 1 – Typical Interface Circuit 1 L *See below + U1 – Voltage Limiter Analog Input Can Be Either Force Or Sense VIN VRTF Preamp Comparator 256 VEE 2.2 µF AGND .01 µF –5.2 V LINV MINV RT MSB D7 Clock Buffer 255 D6 152 Typical Voltage Limiter RS 49.9 D1 D2 151 D5 –5.2 D1=D2=HP, 1N 5712 VR2 .01 µF 127 128 D4 256 To 8-Bit Encoder ECL Latches And Buffers D3 64 D2 63 VEE 2 D1 VRef –2 V 10 2.2 + U2 – .01 µF Q1 (1N2907A) VRBF 2.2 µF .01 µF 1 LSB D0 Analog Input Can Be Either Force Or Sense VEE VIN CLK 50 W 2 50 W Convert 100116 50 W 50 W CLK .01 µF –2 V (Analog) AGND .01 µF VEE –5.2 V DGND .01 µF –2 V (Digital) GENERAL DESCRIPTION The SPT7725 is a fast monolithic 8-bit parallel flash A/D converter. The nominal conversion rate is 300 MSPS and the analog bandwidth is in excess of 200 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators. (See block diagram.) This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant for varying input voltages and frequencies and, therefore, makes the part easier to drive than previous flash converters. The SPT7725 incorporates a proprietary decoding scheme that reduces metastable errors (sparkle codes or flyers) to a maximum of 1 LSB. The SPT7725 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. Every comparator also has a clock buffer to reduce differential delays and to improve signal-tonoise ratio. The output drive capability of the device can provide full ECL swings into 50 Ω loads. TYPICAL INTERFACE CIRCUIT The typical interface circuit is shown in figure 1. The SPT7725 is relatively easy to apply depending on the accuracy needed in the intended application. Wire-wrap may be employed with careful point-to-point ground connections if desired, but to achieve the best operation, a SPT7725 5 8/17/01 Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only) *See below + U1 – Voltage Limiter VCC + U1 – VEE 22 VCC 10 W Q1 Analog Input Force RT DGND AGND L VEE 2.2 µF .01 µF –5.2 V D1 VRTF VIN LINV MINV 2.2 µF .01 µF VRTS Preamp Comparator 256 Clock Buffer 192 MSB D7 Overrange D8 Typical Voltage Limiter RS 49.9 D1 –5.2 191 D2 R + – U1 and U2= Rail-to-Rail Op Amp D1=HP, 1N5712 Q1=1N2222A Q2=1N2907A R = 1 kW, .1% U2 10-25 W VR3 D6 .01 µF 151 D5 R 10-25 W V + R2 U2 – .01 µF R 128 256 to 8-Bit Encoder ECL Latches And Buffers D4 127 D3 64 D2 .01 µF 63 D1 R 2 LSB D0 VREF –2 V + U2 – 22 W VRBF VRBS .01 µF + U2 – 10-25 W VR1 VEE 1 VEE .01 µF 2.2 µF DRINV DREAD 2 AGND VEE 50 W AGND –2 V .01 µF –5.2 V VEE .01 µF –2 V (Digital) .01 µF 50 W CLK Convert 100116 50 W 50 W –2 V (Analog) CLK Analog Input VIN (Sense) .01 µF double-sided PC board with a ground plane on the component side separated into digital and analog sections will give the best performance. The converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. Additionally, an RF bead connection through a single point from the analog to digital ground planes will reduce ground noise pickup. The circuit in figure 2 (PGA and cerquad packages only) is intended to show the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power supply/ground noise. This is achieved by the use of external reference ladder tap connections, an input buffer, and supply decoupling. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 µF ceramic capacitor. A 1 µF tantalum should also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 1. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by SPT7725 6 8/17/01 Table I – Output Coding TRUE BINARY INVERTED MINV=LINV=1 D7_____D0 11111111 11111110 10000000 01111111 00000000 00000001 00000000 TWOs COMPLEMENT TRUE INVERTED MINV=LINV=0 ANALOG INPUT VOLTAGE –2 V + 1/2 LSB D8 0 D7_____D0 00000000 00000001 –1.0 V 0 01111111 10000000 0 V – 1/2 LSB 0 11111111 11111110 ≥0 V 1 11111111 MINV=1; LINV=0 MINV=0; LINV=1 D7_____D0 10000000 10000001 11111111 00000000 01111111 01111110 01111111 D7_____D0 01111111 01111110 00000000 11111111 10000000 10000001 10000000 the same source. The SPT7725 is superior to similar devices, due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. An optional input buffer may be used. CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The clock may be driven single-ended since CLK is internally biased to –1.3 V. (See clock input circuit.) CLK may be left open, but a .01 µF bypass capacitor from CLK to AGND is recommended. NOTE: System performance may be degraded due to increased clock noise or jitter. MINV, LINV (OUTPUT LOGIC CONTROL) These are ECL-compatible digital controls for changing the output code from straight binary to two’s complement, etc. For more information, see table I. Both MINV and LINV are in the logic low (0) state when they are left open. The high state can be obtained by tying to AGND through a diode or 3.9 kΩ resistor. D0 TO D7 (DIGITAL OUTPUTS) The digital outputs can drive ECL levels into 50 Ω when pulled down to –2 V. When pulled down to –5.2 V, the outputs can drive 150 Ω to 1 kΩ loads. VRBF, VR2, VRTF (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are –2 V (VRBF), mid-tap (VR2), and AGND (VRTF). The reference pins can be driven as shown in figure 1. VR2 should be bypassed to AGND for further noise suppression. VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS REFERENCE INPUTS (PGA AND CERQUAD PACKAGES ONLY) These are five external reference voltage taps from –2 V (VRBF) to AGND (VRTF) that can be used to control integral linearity over temperature. The taps can be driven by op amps as shown in figure 2. These voltage level inputs can be bypassed to AGND for further noise suppression if so desired. VRB and VRT have force and sense pins for monitoring the top and bottom voltage references. N/C All Not Connected pins should be tied to DGND on the left side of the package and to AGND on the right side of the package. DREAD – DATA READY; DRINV – DATA READY INVERSE (PGA AND CERQUAD PACKAGES ONLY) The data ready pin is a flag that goes high or low at the output when data is valid or ready to be received. It is essentially a delay line that accounts for the time necessary for information to be clocked through the SPT7725’s decoders and latches. This function is useful for interfacing with high-speed memory. Using the data ready output to latch the output data ensures minimum set-up and hold times. DRINV is a data ready inverse control pin. (See the timing diagram.) D8 – OVERRANGE (PGA AND CERQUAD PACKAGES ONLY) This is an overrange function. When the SPT7725 is in an overrange condition, D8 goes high and all data outputs go high as well. This makes it possible to include the SPT7725 into higher resolution systems. SPT7725 7 8/17/01 OPERATION The SPT7725 has 256 preamp/comparator pairs that are each supplied with the voltage from VRTF to VRBF divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each comparator’s individual clock buffer. When CLK pin is in the low state, the master or input stage of the comparators compares the analog input voltage to the respective reference voltage. When CLK changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in Figure 3 – Timing Diagram sequence from the top comparators, closest to VRTF (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches that are enabled (track) when CLK changes from high to low. From here, the outputs of the latches are coded into 6 LSBs from 4 columns, and 4 columns are coded into 2 MSBs. Next are the MINV and LINV controls for output inversions, which consist of a set of eight XOR gates. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. N Analog Input VIN tPW1 Clock CLK CLK tPW0 N+2 N+1 Master Comparator Output 6 Bit Latch Output 8 Bit Latch Output Data Output D0–D7 Overrange D8 Data Ready tD N–1 N N+1 Timing for PGA and Cerquad Packages Only 8 Internal Timing SPT7725 8/17/01 Slave Figure 4 – Subcircuit Schematics Input Circuit AGND Output Circuit AGND DGND MINV, LINV Input Circuit AGND 10 kW VIN VR MINV LINV –1.3 V Data Out 16 kW VEE VEE Figure 5 – Clock Input AGND Figure 6 – Burn-In Circuit (42-lead DIP Package only) VEE 1N4736 VREF R4 R4 –2.0 V CLK VRBF R3 R1 R1 R1 R1 R1 R1 R1 R1 CLK 13 kW VEE 13 kW –1.3 V D0 D1 VIN R2 D2 VIN D3 D4 D5 D6 CLK CLK R2 R2 D7 CLK CLK DGND AGND VRTF VEE LINV MINV R2 EVALUATION BOARDS The EB7725 evaluation board is available to aid designers in demonstrating the full performance of the SPT7725. This board includes a voltage reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the operation of this board, as well as application tips, is also available. Contact the factory for price and delivery. R1 = 50 W 1/4 Watt CC 5% R2 = 1 kW 1/4 Watt CC 5% R3 = 6.5 W 1/4 Watt CC 5% R4 = 6.5 W 1/2 Watt CC 5% VREF = –2.0 Volts VEE = –6.6 Volts –2.0 V SPT7725 9 8/17/01 PACKAGE OUTLINES 42-Lead Sidebrazed DIP 42 1 G A E F C B H D SYMBOL A B C D E F G H I J INCHES MIN MAX 0.081 0.099 0.016 0.020 0.095 0.105 .050 typ .050 typ 0.275 2.080 2.120 0.585 0.605 0.008 0.015 0.600 0.620 MILLIMETERS MIN MAX 2.06 2.51 0.41 0.51 2.41 2.67 1.27 1.27 6.99 52.83 53.85 14.86 15.37 0.20 0.38 15.24 15.75 I J 46-Lead Pin Grid Array D A B Pin 1 E SYMBOL A B C D E F G INCHES MIN MAX 0.890 0.910 0.100 typ .045 dia .055 dia 0.084 0.096 0.169 0.193 .020 dia .030 dia .050 typ MILLIMETERS MIN MAX 22.61 23.11 2.54 typ 1.14 1.40 2.13 2.44 4.29 4.90 0.51 0.76 1.27 typ F Stand-off Pin C Diameter G SPT7725 10 8/17/01 44-Lead Cerquad SYMBOL A B C D E F G H INCHES MIN MAX 0.550 typ 0.685 0.709 0.037 0.041 0.016 typ 0.008 typ 0.027 0.051 0.006 typ 0.080 0.089 MILLIMETERS MIN MAX 13.97 typ 17.40 18.00 0.94 1.04 0.41 typ 0.20 typ 0.69 1.30 0.15 typ 2.03 2.26 C D A B A B 0–5° H E F G SPT7725 11 8/17/01 PIN ASSIGNMENTS 9 8 7 6 5 4 3 2 1 A D8 D6 D7 D5 D4 D3 D2 D1 D0 DGND 1 2 3 4 5 6 VEE N/C LINV VEE AGND DGND D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DGND AGND VEE MINV N/C CLK CLK N/C 42 VRTF 41 N/C 40 VEE VEE 39 38 PIN FUNCTIONS Name LINV VEE DGND D0 D1–D6 D7 MINV CLK Function D0 through D6 Output Inversion Control Pin Negative Analog Supply Nominally –5.2 V Digital Ground Digital Data Output (LSB) Digital Data Output Digital Data Output (MSB) D7 Output Inversion Control Pin Inverse ECL Clock Input Pin ECL Clock Input Pin Analog Ground Analog Input; Can be Connected to the Input Signal or Used as a Sense Reference Voltage Tap 2 (–1.0 V typ) Reference Voltage Top Reference Voltage Bottom AGND DREAD AGND B C D E N/C 37 N/C 36 AGND 35 VIN 34 VEE DGND N/C VEE DRINV 7 8 9 10 CLK VEE AGND VRBS VRBF MINV Bottom View PGA LINV CLK VEE VRTS N/C AGND DIP AGND 33 VR2 32 AGND 31 VIN 30 F AGND VRTF VEE 11 12 13 AGND VEE VR1 G H J VR3 14 15 16 17 18 19 AGND 29 N/C 28 N/C 27 VEE 26 VEE 25 N/C AGND VIN AGND VR2 AGND VIN AGND N/C CLK AGND VIN VR2 VRTF VRBF N/C 24 VRBF 23 N/C 22 DREADY 20 DGND 21 D8 D7 D4 D6 D3 D5 D2 D1 D0 36 44 41 38 35 43 40 DGND AGND VEE MINV CLK CLK VEE AGND AGND VRBS VRBF 42 39 37 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 AGND VEE LINV N/C DRINV N/C VEE AGND AGND VRTS VRTF The following pins are on PGA and cerquad packages only. DRINV DREAD VR1 VR3 VRTS VRBS Data Ready Inverse Data Ready Output Reference Voltage Tap 1 (–1.5 V typ) Reference Voltage Tap 3 (–0.5 V typ) Reference Voltage Top, Sense Reference Voltage Bottom, Sense Cerquad 29 28 27 26 25 24 23 Overrange Overrange Output D8 12 15 18 21 13 16 19 14 17 20 AGND VR1 AGND VEE AGND ORDERING INFORMATION PART NUMBER SPT7725AIJ SPT7725BIJ SPT7725AIG SPT7725BIG SPT7725AIQ SPT7725BIQ SPT7725BCU LINEARITY 0.75 LSB 0.95 LSB 0.75 LSB 0.95 LSB 0.75 LSB 0.95 LSB 0.95 LSB TEMPERATURE RANGE –25 to +85 °C –25 to +85 °C –25 to +85 °C –25 to +85 °C –25 to +85 °C –25 to +85 °C +25 °C PACKAGE TYPE 42L Ceramic S/B 42L Ceramic S/B 46L PGA 46L PGA 44L Cerquad 44L Cerquad Die* *Please see the die specification for guaranteed electrical perfor mance. AGND VR3 VEE VR2 VIN VIN 22 SPT7725 12 8/17/01