SPT7730SCU

SPT7730 8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER FEATURES • • • • • • 8-Bit, 1 kHz to 3.0 MSPS Analog-to-Digital Converter Monolithic CMOS Serial Output Internal Sample-and-Hold Analog Input Range: 0 to 2 V Nominal; 3.3 V Max Power Dissipation (Excluding Reference Ladder) 45 mW at +5 V 16 mW at +3 V • Single Power Supply: +3 V to +5 V Range • High ESD Protection: 3,000 V Minimum APPLICATIONS • • • • • • Handheld and Desktop Scanners DSP Interface Applications Portable Digital Radios Portable and Handheld Applications Automotive Applications Remote Sensing GENERAL DESCRIPTION The CADEKA 8-bit, 3.0 MSPS, serial analog-to-digital converter delivers excellent high speed conversion performance with low cost and low power. The serial port protocol is compatible with the serial peripheral interface (SPI) or MICROWIRE™ industry standard, high-speed synchronous MPU interfaces. The large input bandwidth and fast transient response time allow for CCD applications operating up to 3.0 MSPS. The device can operate with a power supply range from +3 V to +5 V with very low power dissipation. The small package size makes this part excellent for handheld applications where board space is a premium. The SPT7730 is available in an 8-lead SOIC package over the commercial temperature range. Contact the factory for availability of die and industrial temperature range versions. BLOCK DIAGRAM Ground VDD Track-and-Hold SAR Analog Input 8-Bit A/D Serial Output Logic Data Out Clock Timing And Control Start Convert VREF+ VREF- ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Supply Voltages VDD ...........................................................................+6 V Input Voltages Analog Input ................................................. -0.7 to +6 V VREF+ ........................................................... -0.7 to +6 V VREF- ............................................................ -0.7 to +6 V Clock and SC ............................................... -0.7 to +6 V Output Data Out ................................................................ 10 mA Temperature Operating, ambient ..................................... 0 to 70 °C junction ........................................ + 175 °C Lead, Soldering (10 seconds) ........................... + 300 °C Storage ................................................... -65 to + 150 °C Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = +25 °C, VDD = +5.0 V, VIN = 0 to +3 V, fCLK = 36 MHz, fS = 3.0 MSPS, VREF+ = +3.0 V, VREF- = 0.0 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL MIN TYP MAX UNITS DC ELECTRICAL CHARACTERISTICS DC Performance Resolution Differential Linearity Integral Linearity No Missing Codes Analog Input Input Voltage Range1 Input Resistance Input Capacitance Input Bandwidth (Small Signal) Offset Gain Error Reference Input Resistance Voltage Range1 VREF-2 VREF+2 VREF+ -VREF- (∆) Reference Settling Time Timing Characteristics Maximum Conversion Rate Minimum Conversion Rate Maximum External Clock Rate Minimum External Clock Rate Aperture Delay Time Aperture Jitter Time Data Ouput LSB Hold Time 8 ±0.2 ±0.2 Guaranteed VREF- +4% 5 5 30 -2 -2 250 -4% VREF-+∆ 1/10 VDD 280 0 +2 +2 350 VREF+-∆ 2/3 VDD 90 3.0 1 36 12 1.0 12 5 5 8 Bits LSB LSB I I I IV I IV IV IV IV IV IV IV IV IV I IV I IV IV IV IV ±0.5 ±0.5 VREF+ -6% V MΩ pF MHz % of FSR % of FSR Ω V V V ns MSPS kSPS MHz kHz ns ps ns TMIN to TMAX 6 1Percentages refer to percent of [(VREF+) -(VREF-)] 2∆ = Minimum (VREF+ -VREF-) SPT7730 2 12/19/97 ELECTRICAL SPECIFICATIONS TA = +25 °C, VDD = +5.0 V, VIN = 0 to +3 V, fCLK = 36 MHz, fS = 3.0 MSPS, VREF+ = +3.0 V, VREF- = 0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Effective Number of Bits fIN = 500 kHz Signal-to-Noise Ratio fIN = 500 kHz Harmonic Distortion fIN = 500 kHz Power Supply Requirements3 +VDD Supply Voltage +VDD Supply Current Power Dissipation 3Excluding the reference ladder. TEST CONDITIONS TEST LEVEL MIN TYP MAX UNITS IV IV IV IV IV I IV I 3 7.5 47 60 5.5 7 10 22 50 Bits dB dB V mA mA mW mW VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V 5.4 9 16 45 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. SPT7730 3 12/19/97 GENERAL DESCRIPTION AND OPERATION The SPT7730 is an 8-bit analog-to-digital converter that uses a successive approximation architecture to perform data conversion. Each conversion cycle is 12 clocks in length. When the Not Start Convert ( SC) line is held low, conversion begins on the next rising edge of the input clock. When the conversion cycle begins, the data output pin is forced low until valid data output begins. The first two clock cycles are used to perform internal offset calibrations and to track the analog input. The analog input is then sampled using an internal track-and-hold amplifier on the falling edge of the third clock cycle. On clock cycles 4 through 12, an 8-bit successive approximation conversion is performed, and the data is output starting with the MSB. Serial data output begins with output of the MSB. See the Data Output Timing section for details. Each bit of the data conversion is sequentially determined and placed on the data output pin at the clock rate. This process continues until the LSB has been determined and output. At this point, if the SC line is high, the data output pin will be forced into a high impedance state, and the converter will go into an idle state waiting for the SC line to go low. This is referred to as Single Shot Mode. See Modes of Operation for details. If the SC is either held low through the entire 12 clock conversion cycle (free run mode) or is brought low prior to the trailing edge of the twelfth clock cycle (synchronous mode), the data output pin goes low and stays low until valid data output begins. Because the chip has either remained selected in the free run mode or has been immediately selected again in the synchronous mode, the next conversion cycle begins immediately after the twelfth clock cycle of the previous conversion. See Modes of Operation for details. should be taken to ensure that the LSB is latched into an external latch with the proper amount of set and hold time. DATA OUTPUT CODING The coding of the output is straight binary. (See table I.) Table I - Data Output Coding ANALOG INPUT OUTPUT CODE D7 - DO +FS - 1/2 LSB 1111 111Ø +1/2 FS ØX X X XXXX +1/2 LSB OOOO OOOØ VREFOOOO OOOO Ø indicates the flickering bit between logic O and 1. X indicates the flickering bit between logic 1 and O. ANALOG INPUT AND REFERENCE SETTLING TRACK AND HOLD TIMING Figure 9 shows the timing relationship between the input clock and SC versus the analog input tracking and reference settling. The analog input is tracked from the twelfth clock cycle of the previous conversion to the third clock cycle of the current conversion. On the falling edge of the third clock cycle, the analog input is held by the internal sample-andhold. After this sample, the analog input may vary without affecting data conversion. The reference ladder inputs (VREF+ and VREF-) may be changed starting on the falling edge of the eleventh clock cycle of the previous conversion and must be settled by the falling edge of the third clock cycle of the current conversion. (See figure 9.) VOLTAGE REFERENCE AND ANALOG INPUT The SPT7730 requires the use of a single external voltage reference for driving the high side of the reference ladder. The VREF+ can be a maximum of 2/3 VDD. For example, if VDD = +5 V, then VREF+ max = (2/3) * 5 V = +3.3 V. The lower side of the ladder is typically tied to AGND (0.0 V) but can be run up to a voltage that is 1/10th of VDD below VREF+: VREF- max. = VREF+ - (1/10) * VDD. For example, if VDD = +5 V and VREF+ = 3 V, then VREF- max. = 3 V - (1/10)* 5 V = 2.5 V. The +Full Scale (+FS) of the analog input is expected to be 6% of [(VREF+)-(VREF-)] below VREF+ and the -Full Scale (-FS) of the analog input is expected to be 4% of [(VREF+) - (VREF-)] above VREF-. (See figure 1.) Therefore, Analog +FS = VREF+ - 0.06 * [(VREF+) - (VREF-)], and Analog -FS = VREF- +0.04 * [(VREF+) - (VREF-)]. For example, if VREF+ = 3 V and VREF- = 0 V, then Analog + FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and Analog - FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V. SPT7730 4 12/19/97 TYPICAL INTERFACE CIRCUIT CLOCK INPUT The SPT7730 requires a 50% ±10 % duty cycle clock running at 12 times the desired sample rate. The clock may be stopped in between conversion cycles without degradation of operation (single shot type of operation), however, the clock should remain running during a conversion cycle. POWER SUPPLY The SPT7730 requires only a single supply and operates from 3.0 V to 5.0 V. CADEKA recommends that a 0.01 µF chip capacitor be placed as close as possible to the supply pin. DATA OUTPUT SET UP AND HOLD TIMING As figure 8 shows, all of the data output bits (except the LSB) remains valid for a duration equivalent to one clock period and delayed by 8 ns after the falling edge of clock. Because the data converter enters into a next conversion ready state at the leading edge of clock 12, the LSB bit is valid for a duration equivalent to only the clock pulse width low and delayed by 8 ns after the falling edge of clock. Care Figure 1 - Analog Input Full-Scale Range VREF+ +FS MODES OF OPERATION The SPT7730 has three modes of operation.The mode of operation is based strictly on how the SC is used. Full-Scale Range 6% of [(VREF+) - (VREF-)] SINGLE SHOT MODE When SC goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). The MSB of data is valid 8 ns after the falling edge of the fourth conversion clock. (See figure 8.) The conversion is complete after 12 clock cycles. At the falling edge of the twelfth clock cycle, if SC is high (not selected), the data output goes to a high impedance state, and no more conversions will take place until the next SC low event. (See the single shot mode timing diagram in figure 4.) SYNCHRONIZED MODE 4% of [(VREF+) - (VREF-)] -FS VREF- The drive requirements for the analog input are minimal when compared to most other converters due to the SPT7730’s extremely low input capacitance of only 5 pF and very high input resistance of greater than 5 MΩ. If the input buffer amplifier supply voltages are greater than VDD + 0.7 V or less than Ground - 0.7 V, the analog input should be protected through a series resistor and a diode clamping circuit as shown in figure 2. Figure 2 - Recommended Input Protection Circuit +V AVDD When SC goes low, conversion will start on the next rising edge of the clock (defined as the first conversion clock). The MSB is valid 8 ns after the falling edge of the fourth conversion clock. The first conversion is complete after 12 clock cycles. At any time after the falling edge of the twelfth clock cycle, SC may go low again to initiate the next conversion. When the SC goes low, the conversion starts on the rising edge of the next clock. (See the synchronized mode timing diagram in figure 5.) The data output will go to a high impedance state until the next conversion is initiated. FREE RUN MODE When SC goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). The MSB data is valid 8 ns after the falling edge of the fourth conversion clock. As long as SC is held low, the device operates in the free run mode. New conversions start after every twelfth cycle with valid data available 8 ns after the falling edge of the fourth clock within each new conversion cycle. The data output remains low between conversion cycles. (See the free run mode timing diagram in figure 6.) D1 Buffer 47 Ω D2 ADC -V D1 = D2 = Hewlett Packard HP5712 or equivalent INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 3. This circuit provides ESD robustness to >3.0 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. Figure 3 - On-Chip Protection Circuit VDD 120 Ω Analog 120 Ω Pad SPT7730 5 12/19/97 Figure 4 - Single Shot Mode Timing Diagram tSC Start Convert Latch MSB 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A Clock High Z State Serial Data Out A7 MSB Start Conversion Sample Analog Input A6 A5 A4 A3 A2 A1 A0 LSB Figure 5 - Synchronous Mode Timing Diagram tSC tSC Start Convert Latch MSB Latch MSB Clock 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 11 A 12 A High Z State 1 B 2 B 3 B 4 B 5 B Serial Data Out A7 MSB Start Sample Analog Input A A6 A5 A4 A1 A0 LSB Sample Analog Input B B7 MSB Figure 6 - Free Run Mode Timing Diagram Start Convert Latch MSB Clock 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 1 1 A 1 2 A 1 B 2 B 3 B 4 B 5 B 6 B 7 B Serial Data Out A7 MSB Start Sample Analog Input A A6 A5 A4 A1 A0 LSB Sample Analog Input B B7 MSB B6 B5 Figure 7 - Typical Interface Circuit Figure 8 - Data Output Timing td=8 ns td=8 ns td=8 ns td=8 ns REF IN .01 µF VREF+ 0V VIN VREF+ VDD +VDD .01 µF Analog In Data Out +VDD 0V Clock 4 A 5 A 1 1 A 1 2 A VREF- Clock +VDD 0V Data Out A7 MSB A1 A0 LSB Ground SC +VDD 0V SPT7730 6 12/19/97 Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing Synchronous Mode* Single Shot Mode (SC high, no B cycle) SC Free Run Mode (SC always Ø) Clock 1 A 2 A 3 A 4 A 11 A 12 A 1 B 2 B 3 B 4 B VREF+ Ref Hold Ref Settling Window** AIN Sample Input Sample Input * The rising edge of the SC line can occur any time between the rising edge of clock 1A and the falling edge of clock 12A. ** The reference settling window can be extended in the synchronous mode by adding extra clocks between conversion cycles. The example shown is the minimum number of clocks required (12) per conversion cycle. PACKAGE OUTLINE 8-Lead SOIC INCHES MAX 0.194 0.242 0.019 0.010 0.067 0.060 0.156 8° 0.010 0.035 MILLIMETERS MIN MAX 4.80 5.84 1.27 typ 0.35 0.13 1.55 1.40 3.81 0° 0.19 0.41 4.98 6.20 0.49 0.25 1.73 1.55 3.99 8° 0.25 0.89 A SYMBOL A B C D E F G H I J K MIN B 0.187 0.228 0.050 typ 0.014 0.005 0.060 0.055 0.149 0° 0.007 0.016 H G F C D E I K J SPT7730 7 12/19/97 PIN ASSIGNMENTS External VREF+ Analog In External VREFGround 1 2 3 4 8 7 6 5 PIN FUNCTIONS Name Function Analog Signal Input Start Convert. A high-to-low transition on this input begins the conversion cycle and enables serial data output. Clock that drives A/D conversion cycle and the synchronous serial data output Serial Data. Tri-state serial data output for the A/D result driven by the CLOCK input External voltage reference for top of reference ladder External voltage reference for bottom of reference ladder Analog and Digital +3 V to +5 V Power Supply Input Analog and Digital Ground VDD Data Out Analog In Start Convert Clock Start Convert Clock Data Out External VREF+ External VREFVDD GND ORDERING INFORMATION PART NUMBER SPT7730SCS SPT7730SCU* TEMPERATURE RANGE 0 to +70 °C +25 °C PACKAGE 8L SOIC Die* *Please see the die specification for guaranteed electrical performance. SPT7730 8 12/19/97