SPT7810

SPT7810 10-BIT, 20 MSPS, ECL OUTPUT A/D CONVERTER FEATURES • • • • • • • Monolithic 20 MSPS Converter On-Chip Track/Hold Bipolar ±2.0 V Analog Input 60 dB SNR @ 1 MHz Input Low Power (1.3 W Typical) 5 pF input Capacitance ECL Outputs APPLICATIONS • • • • • • Medical Imaging Professional Video Radar Receivers Instrumentation Electronic Warfare Digital Communications GENERAL DESCRIPTION The SPT7810 A/D converter is a 10-bit monolithic converter capable of word rates of a minimum of 20 MSPS. On board track/hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are ECL to provide a higher level of noise immunity in high speed system applications. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.3 watts with power supply voltages of +5.0 and -5.2 volts. The SPT7810 also provides a wide input voltage swing of ±2.0 volts. The SPT7810 is available in a 28-lead ceramic sidebrazed DIP, PDIP, and die form. Commercial and industrial temperature ranges are currently offered. Contact the factory for availability of military temperature range and /883 processed units. BLOCK DIAGRAM Analog Input Coarse A/D 4 Analog Prescaler T/H Amplifier Bank Decoding Network Digital Output 10 Successive Interpolation Stage i Successive Interpolation Stage i+1 Successive Interpolation Stage N ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VCC ............................................................... -0.3 to +6 V VEE ............................................................... +0.3 to -6 V Input Voltages Analog Input ............................................... VFB≤VIN≤VFT VFT, VFB. ................................................... +3.0 V, -3.0 V Reference Ladder Current ..................................... 12 mA Output Digital Outputs .......................................... +30 to -30 mA Temperature Operating Temperature .............................. -25 to +85 °C Junction Temperature (1) .............................................. 175 °C Lead Temperature, (soldering 10 seconds) .......... 300 °C Storage Temperature ................................ -65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=Tmin - Tmax, VCC=+5.0 V, VEE=-5.2 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fclock=20 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Resolution DC Accuracy (+25 °C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error Reference Input Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN=1 MHz fIN=3.58 MHz fIN=10.3 MHz TEST CONDITIONS TEST LEVEL MIN 10 SPT7810A TYP MAX MIN 10 SPT7810B TYP MAX UNITS Bits ± Full Scale 250 kHz Sample Rate V V VI VI VI VI V V V V VI V VI V IV V V V ±1.0 ±0.5 Guaranteed ±2.0 30 300 5 120 ±2.0 ±2.0 800 0.8 ±1.5 ±0.75 Guaranteed ±2.0 30 300 5 120 ±2.0 ±2.0 800 0.8 LSB LSB VIN=0 V 60 100 60 100 3 dB Small Signal V µA kΩ pF MHz LSB LSB Ω Ω/°C MHz ns 500 500 20 20 1 5 1 5 20 20 1 5 1 5 Clock Cycle TA=+25 °C TA=+25 °C TA=+25 °C ns ns ps-RMS 9.2 8.8 7.5 8.7 8.3 7.0 Bits Bits Bits Typical thermal impedances: 28L sidebrazed DIP. θja = 50 °C/W, 28L plastic DIP θja = 50 °C/W. SPT7810 2 3/11/97 ELECTRICAL SPECIFICATIONS TA=Tmin - Tmax, VCC=+5.0 V, VEE=-5.2 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=20 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fIN=1 MHz fIN=3.58 MHz fIN=10.3 MHz Harmonic Distortion fIN=1 MHz fIN=3.58 MHz fIN=10.3 MHz TEST CONDITIONS TEST LEVEL MIN SPT7810A TYP MAX MIN SPT7810B TYP MAX UNITS +25 °C +25 °C +25 °C I IV I IV I IV I IV I IV I IV I IV I IV I IV V V V VI VI VI VI IV IV 57 55 56 54 50 47 57 54 56 53 46 45 55 52 54 51 44 43 60 58 58 56 53 50 60 57 58 55 48 47 57 55 47 67 0.2 0.5 54 52 53 51 47 44 54 51 53 50 43 42 52 49 51 48 41 40 57 55 55 53 49 46 57 54 55 52 45 44 54 52 44 67 0.2 0.7 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Degree +25 °C +25 °C +25 °C Signal-to-Noise and Distortion fIN=1 MHz +25 °C fIN=3.58 MHz fIN=10.3 MHz +25 °C +25 °C Spurious Free Dynamic Range +25 °C, fIN =1 MHz Differential Phase +25 °C, fIN=3.58 & 4.35 MHz Differential Gain +25 °C, fIN=3.58 & 4.35 MHz Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) Digital Outputs Logic 1 Voltage Logic 0 Voltage 50 Ω to -2 V 50 Ω to -2 V % V -1.5 V +750 µA +750 µA ns 300 ns V -1.5 V +5.25 -5.45 190 160 1.8 V V mA mA W LSB -1.1 -500 -500 20 20 -1.1 ±200 ±300 -1.5 +750 +750 300 -0.8 -1.8 -5.0 -5.2 140 115 1.3 1.0 -1.1 -500 -500 20 20 -1.1 -1.5 +5.25 -5.45 170 140 1.6 +4.75 -4.95 ±200 +300 VI VI IV IV VI VI VI V -0.8 -1.8 +5.0 -5.2 140 115 1.3 1.0 Power Supply Requirements Voltages VCC -VEE Currents ICC -IEE Power Dissipation Outputs Open Power Supply Rejection Ratio (5 V ±0.25 V, -5.2 V ±2.0 V) +4.75 -4.95 SPT7810 3 3/11/97 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. Figure 1A: Timing Diagram N N+1 tpwH CLK tpwL N+2 CLK td Data Valid N Data Valid N+1 Output Data Figure 1B: Single Event Clock CLK CLK td Output Data Data Valid Table I - Timing Parameters PARAMETERS td tpwH tpwL DESCRIPTION CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width MIN 20 20 TYP 5 300 MAX UNITS ns ns ns SPT7810 4 3/11/97 SPECIFICATION DEFINITIONS APERTURE DELAY Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels that is applied to the input. Differential phase is the variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. DIFFERENTIAL NONLINEARITY (DNL) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) INTEGRAL NONLINEARITY (INL) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. N= S INAD - 1.76 6.02 ± FULL-SCALE ERROR (GAIN ERROR) Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage. SPT7810 5 3/11/97 TYPICAL PERFORMANCE CHARACTERISTICS SNR vs Input Frequency 80 80 THD vs Input Frequency 70 70 fs = 20 MSPS Signal-to-Noise Ratio (dB) 60 Total Harmonic Distortion (dB) fs = 20 MSPS 60 50 50 40 40 30 30 20 100 101 102 20 100 101 102 Input Frequency (MHz) Input Frequency (MHz) SINAD vs Input Frequency 80 SNR, THD, SINAD vs Sample Rate 80 Signal-to-Noise and Distortion (dB) 70 70 60 SNR, THD, SINAD (dB) fs =20 MSPS SNR, THD 60 50 50 SINAD 40 40 fin = 1 MHz 30 30 20 100 101 102 20 100 101 102 Input Frequency (MHz) Sample Rate (MSPS) Spectral Response 0 SNR, THD, SINAD vs Temperature 65 fs = 20 MSPS fin = 1 MHz 60 SNR SNR -30 SNR, THD, SINAD (dB) Amplitude (dB) THD 55 THD SINAD 50 -60 -90 fs = 20 MSPS fin = 1 MHz 45 -120 0 1 2 3 4 5 6 7 8 9 10 40 -25 0 +25 +50 +75 Input Frequency (MHz) Temperature (°C) SPT7810 6 3/11/97 TYPICAL INTERFACE CIRCUIT The SPT7810 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7810 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7810 requires the use of two supply voltages, VEE and VCC. Both supplies should be treated as analog supply sources. This means the VEE and VCC ground returns of the device should both be connected to the analog ground plane. All other -5.2 V requirements of the external digital logic circuit should be connected to the digital ground plane. Each power supply pin should be bypassed as closely as possible to the device with .01 µF and 10 µF capacitors as shown in figure 2. The two grounds available on the SPT7810 are AGND and DGND. DGND is used only for ECL outputs and is to be referenced to the output pulldown voltage. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of Figure 2 - Typical Interface Circuit CLK-IN CLK 2 CLK VIN1 VIN2 the SPT7810. The AGND and the DGND ground planes should be separated from each other and only connected together at the device through an inductance. Doing this will minimize the ground noise pickup. VOLTAGE REFERENCE The SPT7810 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. In addition, there are 3 reference ladder taps (VST,VRM and VSB). VST is the sense for the top of the reference ladder (+2.0 V), V RM i s the midpoint of the ladder (0.0 V typ) and V SB i s the sense for the bottom of the reference ladder (-2.0 V). The voltages seen at V ST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). These points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 uF connected to AGND from each tap is recommended to minimize high frequency noise injection. An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a CLK-IN Analog Input Analog Input Coarse A/D 4 D10 (OVERRANGE) D9 (MSB) D8 .01 µF 10 µF IC1 VOUT 2 VIN (REF-03) Trim GND 4 ANALOG PRESCALER VFT D7 Decoding Network 6 R1 10 kΩ + +2.5 V Digital Outputs D6 D5 D4 D3 D2 D1 R VST .01 µF R2* 30 kΩ 5 T/H AMPLIFIER BANK 2R SUCCESSIVE INTERPOLATION STAGE # i +5 V .01 µF 7 1 10 µF +5 V R4 10 kΩ 3 IC2 2 VRM -5.2 V .01 µF 2R + (OP-07) 4 2R .01 µF 8 6 R3* 30 kΩ VSB 2R SUCCESSIVE INTERPOLATION STAGE # N D0 (LSB) + 11 x 50 Ω *R2 and R3 matched to 0.1% .01 µF -2.5 V 10 µF + VFB R .01 µF VEE -5.2 V D1 -5.2 V DG DG +5 V D2 +5 V NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.) VEE + 10 µF .01 µF + 10 µF .01 µF VCC VCC AG AGND ( 5 V RTN & -5.2 V RTN ) AG L 10 µH + 10 µF .01 µF DGND ( -2 V RTN ) -2 V SPT7810 7 3/11/97 tolerance of 0.6% or ± 0.015 V. The potentiometer R1 is 10 kΩ and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. R1 and R4 should be adjusted such that VST and VSB are exactly +2.0 V and -2.0V respectively. The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is ± 20% of the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with ± 2.5 V references, the accuracy of the device will degrade if operated beyond a ± 2% range. The following errors are defined: +FS error = top of ladder offset voltage = ∆(+FS -VST+1 LSB) -FS error = bottom of ladder offset voltage = ∆(-FS -VSB -1 LSB) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. ANALOG INPUT VIN1 and VIN2 are the analog inputs. Both inputs are tied to the same point internally. Either one may be used as an analog input “sense” and the other for an input “force." The inputs can also be tied together and driven from the same source. The full scale input range will be 80% of the reference voltage or ±2 volts with VFB=-2.5 V and VFT=+2.5 V. The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due the SPT7810’s extremely low input capacitance of only 5 pF and very high input resistance of 300 kΩ. For example, for an input signal of ± 2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 µA. CLOCK INPUT The clock inputs (CLK, CLK ) are designed to be driven differentially with ECL levels. The clock may be driven single ended since CLK is internally biased to -1.3 V. CLK may be left open, but a .01 µF bypass capacitor to AGND is recommended. As with all high speed circuits, proper terminations are required to avoid signal reflections and possible ringing that can cause the device to trigger at an unwanted time. The CLK pulse width (tpwH) must be kept between 10 ns and 300 ns to ensure proper operation of the internal track-and-hold amplifier. (See timing diagram.) When operating the SPT7810 at sampling rates above 3 MSPS, it is recommended that the clock input duty cycle be kept at 50% to optimize performance. The analog input signal is latched on the rising edge of the CLK. DIGITAL OUTPUTS The format of the output data (D0-D9) is straight binary. These outputs are ECL with the output circuit shown in figure 4. The outputs are latched on the rising edge of CLK with a propagation delay of 4 ns. There is a one clock cycle latency between CLK and the valid output data (see timing diagram). These digital outputs can drive 50 ohms to ECL levels when pulled down to -2 V. The total specified power dissipation of the device does not include the power used by these loads. The additional power used by these loads can vary between 10 and 300 mW typically (including the overrange load) depending on the output codes. If lower power levels are desired, the output loads can be reduced, but careful consideration to the capacitive loads in relation to the operating frequency must be considered. Table II - Output Data Information ANALOG INPUT >+2.0 V + 1/2 LSB +2.0 V -1 LSB 0.0 V -2.0 V +1 LSB