SPT7862SIT

SPT7862 10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER FEATURES • Dual-channel, 10-Bit, 40 MSPS analog-to-digital converter • Low power dissipation: 320 mW (typical) • Internal track-and-hold • Single +5 volt supply • Tri-state, TTL/CMOS-compatible outputs • Selectable +3 or +5 V logic I/O • High ESD protection of 3,500 volts minimum APPLICATIONS • • • • • • • • • Video set-top boxes Cellular base stations QPSK/QAM RF demodulation S-video digitizers Composite video digitizers Portable and handheld instrumentation Medical ultrasound Cable modems Video frame grabbers GENERAL DESCRIPTION The SPT7862 contains two separate 10-bit CMOS analogto-digital converters that have sampling rates of up to 40 MSPS. Each device has its own separate clock and reference inputs so that they can be used independently in multichannel applications or can be driven from the same inputs for demanding quadrature demodulation and S-video applications. On-chip track-and-hold and advanced proprietary circuit design in a CMOS process technology provide very good dynamic performance. The SPT7862 operates from a single +5 V supply. Digital data outputs are user selectable at +3 or +5 V. Output data format is straight binary. The SPT7862 is available in a 64-lead TQFP package (10 x 10 mm) over the industrial temperature range of –40 °C to +85 °C. BLOCK DIAGRAM AVDD AGND DVDD DGND OVDDA (+3.3/5.0 V) VINA VINRA VRHFA VRHSA VRLFA VRLSA CLK A ADC Output Buffers DA9–0 OGNDA Reference Ladder DAVA EN Timing Generation OVDDB (+3.3/5.0 V) Output Buffers VINB VINRB VRHFB VRHSB VRLFB VRLSB CLK B ADC DB9–0 OGNDB Reference Ladder DAVB Timing Generation ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ......................................................................... +6 V DVDD ......................................................................... +6 V Input Voltages Analog Input ................................. –0.5 V to AVDD +0.5 V VREF ................................................................. 0 to AVDD CLK Input ................................................................... VDD AVDD – DVDD ...................................................... ±100 mV AGND – DGND .................................................. ±100 mV Note: Output Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ............................. –40 to +85 °C Junction Temperature ......................................... +175 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth Offset Gain Error Reference Input Resistance Voltage Range VRLS VRHS VRHS – VRLS ∆(VRHF – VRHS) ∆(VRLS – VRLF) Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz ƒIN = 10.0 MHz Signal-to-Noise Ratio (without Harmonics) ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz V V IV V V V V V V IV IV V V V VI IV IV V V 0 3.0 1.0 VRLS 29 5.0 250 ±2.0 ±2.0 500 – – 4.0 90 75 2.0 AVDD 5.0 TEST CONDITIONS TEST LEVEL MIN 10 ±1.0 ±0.5 VRHS SPT7862 TYP MAX UNITS Bits LSB LSB V kΩ pF MHz LSB LSB Ω V V V mV mV MHz MHz 12 4.0 7 Clock Cycles (Small Signal) 40 2 ns ps(rms) V VI 7.8 9.1 8.3 Bits Bits TA = +25 °C TA = TMIN to TMAX V I IV 52 47 57.9 54.2 dB dB dB SPT7862 2 2/23/00 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. TEST CONDITIONS 9 Distortion bins from 1024 pt FFT TA = +25 °C TA = TMIN to TMAX TEST LEVEL SPT7862 TYP PARAMETERS Dynamic Performance Harmonic Distortion ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz Signal-to-Noise and Distortion (SINAD) ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz Spurious Free Dynamic Range ƒIN = 10.0 MHz Differential Phase Differential Gain Channel-to-Channel Crosstalk ƒIN = 3.58 MHz ƒIN = 10.0 MHz Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage tRISE tFALL Output Enable to Data Output Delay Power Supply Requirements Voltages OVDD DVDD AVDD Currents AIDD + DIDD OIDD Power Dissipation Power Supply Refection Ratio MIN MAX UNITS V I IV –63 –55.7 –52 –52 dB dB dB TA = +25 °C TA = TMIN to TMAX V I IV V V V V V VI VI VI VI V 49 46 56.8 56.7 51.8 dB dB dB 60 dB Degree % dB dB V V µA µA pF V V ns ns ns ns 5.0 V V V mA mA mW dB 58.3 ±0.3 ±0.3 74 67 2.1 –10 –10 +5 OVDD –0.5 0.44 10 10 10 22 3.0 5.0 5.0 52 12 320 70 0.8 +10 +10 IOH = 0.5 mA IOL = 1.6 mA 15 pF load 15 pF load 20 pF load, TA = +25 °C 50 pF load over temp. VI VI V V V V IV IV IV VI VI VI V 62 14 380 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 °C. Parameter is guaranteed over specified temperature range. SPT7862 3 2/23/00 Figure 1a – Timing Diagram 1 1 2 3 9 8 4 5 6 7 10 11 12 13 14 15 16 17 ANALOG IN CLOCK IN SAMPLING CLOCK (Internal) INVALID VALID DATA OUTPUT 1 2 3 4 5 DATA VALID Figure 1b – Timing Diagram 2 tCLK tC tCH CLOCK IN tCL DATA OUTPUT Data Ø tOD tS Data 1 Data 2 Data 3 DATA VALID tCH tS tCL Table I – Timing Parameters DESCRIPTION Conversion Time Clock Period Clock High Duty Cycle Clock Low Duty Cycle Clock to Output Delay (30 pF Load) PARAMETERS tC tCLK tCH tCL tOD MIN TYP MAX tCLK 25 40 40 50 50 17 10 60 60 20 16 UNITS ns ns % % ns ns Clock to DAV (30 pF load) tS SPT7862 4 2/23/00 TYPICAL PERFORMANCE CHARACTERISTICS THD, SNR, SINAD vs Input Frequency 70 THD, SNR, SINAD vs Sample Rate 70 ƒIN = 10 MHz 65 65 THD, SNR, SINAD (dB) THD 60 THD, SNR, SINAD (dB) 60 SNR 55 SNR 55 THD 50 SINAD SINAD 50 45 45 40 0 5 10 15 20 40 0 1 5 10 20 30 40 50 Input Frequency (MHz) Sample Rate (MSPS) THD, SNR, SINAD vs Temperature 70 Power Dissipation vs Sample Rate 600 ƒIN = 10 MHz ƒIN = 10 MHz 65 500 60 Power Dissipation (mW) 85 125 THD, SNR, SINAD (dB) 400 THD 55 300 50 SNR SINAD 200 45 100 40 –55 –40 –25 0 25 70 0 0 1 5 Temperature (°C) 10 20 30 40 50 60 Sample Rate (MSPS) Spectral Response Amplitude (dB) Frequency (MHz) SPT7862 5 2/23/00 Figure 2 – Typical Interface Circuit +D5V Ref In (+4V) VRHFA VRHSA VRLSA VRLFA VINA VINRA CLKA VCAL VRHFB VRHSB VRLSB VRLFB VINB VINRB CLKB AVDD AGND +3V/5V OVDDA DA9–0 OGNDA VINA ClockINA 10 Interface Logic SPT7862 DAVA +3V/5V 10 Ref In (+4V) OVDDB DB9–0 OGNDB DAVB EN DGND* DVDD VINB ClockINB Interface Logic Enable/Tri-State (Enable = Active Low) +A5 FB +D5V +A5 + 10 µF +5V Analog +5V Analog Return *To reduce the possibility of latch-up, avoid connecting the DGND pins of the ADC to the digital ground of the system. +D5 + 10 µF NOTES: 1. FB is a 10 µH inductor or ferrite bead. It is to be located as close to the device as possible. 2. All capacitors are 0.1 µF surface-mount, unless +5V +5V otherwise specified. Digital Digital Return TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7862 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each SAR ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II – Clock Cycles Clock 1 2 3 4 5–15 16 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 11-bit SAR conversion Data transfer POWER SUPPLIES AND GROUNDING CADEKA suggests that both the digital and the analog supply voltages on the SPT7862 be derived from a single analog supply as shown in figure 2. A separate digital supply should be used for all interface circuitry. CADEKA suggests using this power supply configuration to prevent a possible latch-up condition on power up. OPERATING DESCRIPTION The general architecture for the dual CMOS ADC is shown in the block diagram. Each ADC design contains 16 identical successive approximation (SAR) ADC sections (all operating in parallel), a 16-phase clock generator, an 11-bit 16:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section. The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent SAR ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one SAR ADC section. After 16 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 12 clock cycles. SPT7862 6 2/23/00 • Since only 16 comparators are used, a huge power savings is realized. • The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator’s response to a reference zero. • The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each SAR ADC section. • Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. • The total input capacitance is very low, since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. Figure 3 – Ladder Force/Sense Circuit for Each ADC 1 AGND + - 2 VRHF VRHS 3 4 5 + - N/C VRLS VRLF VIN 6 7 All capacitors are 0.01 µF VOLTAGE REFERENCE The SPT7862 requires the use of a single external voltage reference for driving the high side of each reference ladder. Each ladder is totally independent and may operate at different voltage levels. The high side of the reference ladder must operate within a range of 3 V to 5 V. The lower side of each ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±2 LSB can be obtained. In cases in which wider variations in offset and gain can be tolerated, the external reference can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a .01 µF capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Figure 4 – Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit +4.0 V External Reference VRHS (+3.91 V) 90 mV R/2 R R R R=30 Ω (typ) All capacitors are 0.01 µF R R R VRLS (0.075 V) VRLF (AGND) 0.0 V 75 mV R/2 Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V) and a 75 mV increase is seen at VRLS (= 0.075 V). SPT7862 7 2/23/00 ANALOG INPUT VINA and VINB are the analog inputs and VINRA and VINRB are the respective input returns. Each input return is typically tied to its respective low side reference ladder sense line. (See Figure 2.) The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See the Voltage Reference section.) The drive requirements for the analog inputs are very minimal, when compared to most other converters, due to the SPT7862’s extremely low input capacitance of only 5 pF and a high input resistance in excess of 29 kΩ. Each analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. Figure 5 – Recommended Input Protection Circuit +V AVDD Figure 6 – On-Chip Protection Circuit VDD 120 Ω Analog 120 Ω Pad CLOCK INPUT Each ADC is driven independently from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, each ADC can operate over a wide range of input clock duty cycles without degrading the dynamic performance. D1 Buffer 47 Ω D2 ADC DIGITAL OUTPUTS The digital outputs (DA9–0 and DB9–0) are driven by separate supplies (OVDDA and OVDDB) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7862’s TTL/CMOS-compatible outputs with the user’s logic system supply. Each digital output supply may be driven independently. The format of the output data (D0–D9) is straight binary. (See Table III.) The outputs are latched on the rising edge of CLK. The EN pin controls tri-stating of both data output ports. These outputs can be switched into a tri-state mode by bringing EN high. Table III – Output Data Information ANALOG INPUT +F.S. + 1/2 LSB +F.S. –1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V OVERRANGE D10 1 0 0 0 0 OUTPUT CODE D9–D0 11 1111 1111 11 1111 111Ø ØØ ØØØØ ØØØØ 00 0000 000Ø 00 0000 0000 –V D1 = D2 = Hewlett Packard HP5712 or equivalent CALIBRATION The SPT7862 uses a user-transparent, auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. Upon power up, the SPT7862 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power up of 250 µsec (for a 40 MHz clock). Once calibrated, the SPT7862 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7862 to remain in calibration. (Ø indicates the flickering bit between logic 0 and 1) EVALUATION BOARD The EB7862 evaluation board is available to aid designers in demonstrating the full performance of the SPT7862. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7862 is also available. Contact the factory for price and availability. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness and prevents latch-up under severe discharge conditions without degrading analog transition times. SPT7862 8 2/23/00 PACKAGE OUTLINE 64-Lead TQFP G A B 64 49 INCHES SYMBOL A B MIN 0.465 0.390 0.017 0.006 0.295 typ 0.433 typ 0.055 0.005 0-10° 0.012 0.000 0.028 0.008 0.000 0.067 0.005 MAX 0.480 0.398 0.023 0.010 MILLIMETERS MIN 11.80 9.90 0.42 0.15 7.5 typ 11 typ 1.40 0.125 0-10° 0.30 0.00 0.70 0.20 1.70 0.132 MAX 12.20 10.10 0.58 0.26 1 48 C D E F EF Index G H I J 16 33 K 17 C D 32 H K J I SPT7862 9 2/23/00 PIN ASSIGNMENTS OGNDB OGNDA OVDDB OVDDA DGND CLKB CLKA DVDD DAVB EN DAVA DB0 DA0 N/C N/C N/C PIN FUNCTIONS Pin Name VINA VINB VINRA VINRB VRHFA/B VRHSA/B VRLFA/B VRLSA/B AVDD DVDD OVDD A/B AGND DGND OGND A/B CLK A/B EN D0–9A D0–9B DAV A/B VCAL Description Analog Input (A) Analog Input (B) Analog Input Return (A) Analog Input Return (B) VREF High Force Input A/B VREF High Sense Input A/B VREF Low Force Input A/B VREF Low Sense Input A/B Analog VDD Digital VDD Digital Output Power Supply +3.3 V to +5.0 V Analog Ground Digital Ground Digital Output Ground Input Clock A/B (separate) Enable Outputs (Active Low) Data Outputs A (10 bits) Data Outputs B (10 bits) Data Available A/B Decoupling Pin 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 AGND AGND VRHFA VRHFB VRHSA VRHSB VINRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 AGND AGND AVDD AVDD N/C AGND AGND SPT7862 TOP VIEW 64L TQFP N/C VRLSA VRLSB VRLFA VRLFB N/C AGND VINB AGND VINA AGND VCAL N/C AGND AGND ORDERING INFORMATION PART NUMBER SPT7862SIT TEMPERATURE RANGE –40 to +85 °C PACKAGE TYPE 64-Lead TQFP VINRB SPT7862 10 2/23/00