SPT7864

SPT7864 10-BIT, 40 MSPS A/D CONVERTER TECHNICAL DATA NOVEMBER 20, 2001 FEATURES • 40 MSPS maximum sample rate • 9.5 effective number of bits at ƒ IN = 10 MHz and ƒS = 40 MSPS • 2V P-P full-scale input range • Differential input 2.5 V common mode • Internal or external voltage reference • Common-mode voltage reference output • +3 V / +5 V digital output logic compatibility • +5 V analog power supply • Sleep mode power dissipation: 55 mW APPLICATIONS • Video imaging • Medical imaging • Radar receivers • IR imaging • Digital communications GENERAL DESCRIPTION The SPT7864 is a 10-bit, 40 MSPS analog-to-digital conver ter with low power dissipation at only 395 mW typical at 40 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. The SPT7864 has incor porated proprietar y circuit design and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to interface with TTL/CMOS logic systems. Output data format is offset binar y. The SPT7864 is available in a 28-lead SSOP package over the commercial temperature range. BLOCK DIAGRAM VDD GND Sleep VCM Bandgap Reference EXT/INT REFH REFL VIN VIN Bias Cell THA 10-BIT 40 MSPS ADC 2 CLK, CLK 10 Data Output Latches & Buffers 1 10 OR D0–D9 GND OVDD ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C Supply Voltages VDD ...................................................................... 6.0 V OVDD .................................................................... 6.0 V Input Voltages Analog Input ................................. –0.3 V to VDD +0.7 V CLK Input ..................................... –0.3 V to VDD +0.7 V Output Digital Outputs .............................. –0.3 V to VDD +0.7 V Temperature Operating Temperature ............................... 0 to +70 °C Storage Temperature ............................ –65 to +150 °C Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=+5.0 V, ƒS=40 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Differential Linearity Error (DLE) Integral Linearity Error (ILE) No Missing Codes Analog Input Input Voltage Range (Differential) Input Common Mode (VCM) Input Capacitance Input Bandwidth Common Mode Rejection Ratio (CMRR) Timing Characteristics Conversion Rate Pipeline Delay (Latency) Output Delay (tD) Aperture Delay Time (tAP) Aperture Jitter Time Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 10 MHz, ƒCLK = 40 MSPS Signal-to-Noise Ratio (SNR) ƒIN = 10 MHz, ƒCLK = 40 MSPS Total Harmonic Distortion (THD) ƒIN = 10 MHz, ƒCLK = 40 MSPS Signal-to-Noise and Distortion (SINAD) ƒIN = 10 MHz, ƒCLK = 40 MSPS Spurious Free Dynamic Range (SFDR) ƒIN = 10 MHz, ƒCLK = 40 MSPS TEST CONDITIONS TEST LEVEL MIN 10 SPT7864 TYP MAX UNITS Bits @ +25 °C full temperature @ +25 °C full temperature V V V V VI V IV V V V VI IV V V V ±0.5 ±0.75 ±0.6 ±1.0 Guaranteed ±1 2.5 2 50 40 6 7.5 1.5 15 LSB LSB LSB LSB 2 98 3 V V pF MHz dB MSPS clocks ns ns ps (rms) 25 °C 0 °C to +70 °C 25 °C 0 °C to +70 °C 25 °C 0 °C to +70 °C 25 °C 0 °C to +70 °C 25 °C 0 °C to +70 °C I IV I IV I IV I IV I IV 9.3 9.3 58 57 9.5 9.5 59 59 –71 –71 –66 –65 Bits Bits dB dB dB dB dB dB dB dB 57 57 70 68 59 59 73 71 SPT7864 2 11/20/01 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=+5.0 V, ƒS=40 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified. PARAMETERS Power Supply Requirements VDD Voltage (Analog Supply) OVDD Voltage (Output Supply) VDD Current OVDD Current Power Dissipation External Voltage Reference Internal Voltage Reference Sleep Mode Power Dissipation External Voltage Reference Internal Voltage Reference Power Supply Rejection Ratio (PSRR) TEST CONDITIONS TEST LEVEL IV IV VI VI VI VI VI VI V VI V V VI VI IV IV VI VI VI VI VI VI VI VI VI VI MIN 4.75 2.7 SPT7864 TYP 5.0 3.0/5.0 74 8 387 395 45 55 45 MAX 5.25 5.25 UNITS V V mA mA mW mW mW mW dB V ppm/°C kΩ V V V V V V V V µA µA V V µA µA 417 425 47 56 Internal References Common Mode Voltage Reference (VCM) IO = –1 µA Common Mode Voltage Tempco Output Impedance (VCM) (EXT/INT) = 0 Reference Low Output Voltage (VREFL) Reference High Output Voltage (VREFH) (EXT/INT) = 0 External References Reference Low Input Voltage Range Reference High Input Voltage Range Digital Outputs Output Voltage High Output Voltage Low Digital Inputs Input High Voltage Input Low Voltage Input High Current Input Low Current Clock Inputs Clock Inputs High Voltage Clock Inputs Low Voltage Clock Inputs High Current Clock Inputs Low Current (EXT/INT) = 1 (EXT/INT) = 1 IO = –2 mA IO = 2 mA 2.4 1.95 2.95 1.7 2.7 85% OVDD 2.5 100 2 2.0 3.0 2.0 3.0 90% OVDD 0.2 2.6 2.05 3.05 2.3 3.3 OVDD 0.4 80% VDD 20% VDD ±100 ±100 2 5 0.4 ±115 ±115 TEST LEVEL CODES TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. SPT7864 3 11/20/01 TYPICAL PERFORMANCE CHARACTERISTICS DLE Versus Sample Rate 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 30 ILE Versus Sample Rate 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 30 LSB 40 Sample Rate (MSPS) 50 60 70 LSB ƒIN = 1 kHz ƒIN = 1 kHz 40 Sample Rate (MSPS) 50 60 70 DLE Versus Temperature 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –20 ILE Versus Temperature 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –20 ƒIN = 1 kHz ƒS = 40 MSPS ƒIN = 1 kHz ƒS = 40 MSPS LSB LSB 0 Temperature (Degrees C) 20 40 60 80 0 Temperature (Degrees C) 20 40 60 80 SNR, SINAD, –THD, SFDR Versus Sample Rate 80 ƒIN = 10 MHz SFDR –THD 65 60 55 50 45 SNR SINAD SNR, SINAD, –THD, SFDR Versus Temperature 80 SFDR SNR, SINAD, –THD, SFDR (dB) SNR, SINAD, –THD, SFDR (dB) 75 70 75 70 65 60 55 50 45 –20 SNR SINAD ƒS = 40 MHz ƒIN = 10 MHz –THD 25 30 35 40 45 50 55 60 0 20 Sample Rate (MSPS) 40 60 80 Temperature (Degrees C) SPT7864 4 11/20/01 Figure 1 – Typical Interface Circuit T1 0.1 + 10 VCM VIN RT1 50 W Ext +A5 + 10 0.1 + 10 0.1 AIN SPT7864 VIN OGND OVDD GND CLK 0.1 0.1 RT2 50 W CLK VDD Mini-Circuits T1–6T or T1–1T EXT/INT REFL REFH D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) +D3/5 50 W Buffer + 10 + 10 +A5 +A3/5 AGND AGND 0.1 10 +D3/5 DGND + Ferrite Bead +A5 T2 CLKIN TYPICAL INTERFACE CIRCUIT REFERENCES The SPT7864 has a differential analog input. The input range is determined by the voltages VIN and VIN applied to reference pins REFH and REFL respectively, and is equal to ±(VIN–VIN). Externally generated reference voltages connected to REFH and REFL should be symmetric around 2.5 V. The input range can be defined between ±0.6 V and ±1.5 V. An internal reference exists, providing reference voltages at pins REFH and REFL equal to +3.0 V (VREFH) and +2.0 V (VREFL). These can be connected to REFH and REFL by connecting pin EXT/INT to GND. The references should be bypassed as close to the converter pins as possible using 100 nF capacitors in parallel with smaller capacitors (e.g. 220 pF) to ground. ANALOG INPUT The input of the SPT7864 can be configured in various ways, dependent upon whether a single-ended or differential, AC- or DC-coupled input is wanted. AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM node, as shown in figure 1. In order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full scale. Excellent results are obtained with the Mini- Circuits T1-6T or T1-1T. Proper termination of the input is important for input signal purity. A small capacitor (typically 68 pF) across the inputs attenuates kickback noise from the sample-and-hold. A small capacitor (1 nF) between VCM and ground has also been proven to be advantageous. If a DC-coupled, single-ended input is wanted, a solution based on operational amplifiers, as shown in figure 2, is usually preferred. The AD8138 is suggested for low distortion and video bandwidth. Lower cost operational amplifiers may be used if the demands are less strict. Figure 2 – DC-Coupled, Single-Ended to Differential Conversion (power supplies and bypassing not shown) 51 W 470 W Input Offset Analog In AD8138 470 W 100 W AD8138 Mini-Circuits T1–6T or T1–1T 1 kW 1 kW 51 W 15 pF 100 W 51 W 470 W 470 W AD8138 51 W 470 W SPT7864 5 11/20/01 Logic Interface Circuit ADC VIN VIN Sleep Sleep OR DIFFERENTIAL CLOCK INPUT The SPT7864 clock can be driven differentially or singleended. When driven differentially, CLK and CLK accommodate differential sinusodial signals centered around VDD/2. The peak-to-peak value should be 0.8 V. In order to preserve accuracy at high input frequency, it is important that the clock have low jitter. The differential clock input is made to allow a low-jitter clock design. To ensure low jitter, the differential input should be a pure sine wave with low white noise floor. SINGLE-ENDED CLOCK INPUT For single-ended operation, the CLK node is internally biased to 1.5 V, and should externally be decoupled to ground by a capacitor. A CMOS logic level clock (5 V or 3 V) is applied at the CLK node. (To get an inverted clock input, CLK should be decoupled and the clock signal applied at the CLK node). The duty cycle of the clock should be close to 50%. Consecutive pipeline stages in the ADC are clocked in antiphase. With a 50% duty cycle, every stage has the same time for settling. If the duty cycle deviFigure 3 – Driving Differential Inputs with a Differential Configuration ates from 50%, every second stage has a shorter time for settling; thus it operates less accurately, causing degradation of SNR. In order to preserve accuracy at high input frequency, it is important that the clock have low jitter and steep edges. Rise/fall times should be kept shorter than 2 ns whenever possible. Overshoot should be minimized. Low jitter is especially important when converting high-frequency input signals. Jitter causes the noise floor to rise proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB. It is therefore recommended that the clock trace on the PCB be made as short as possible. DIGITAL OUTPUTS The digital output data appears in offset binary code at CMOS logic levels. Full-scale negative input results in output code 000...0. Full-scale positive input results in output code 111...1. Output data are available 6 clock cycles after the data are sampled. The analog input is sampled one aperture delay (tAP) after the high-to-low clock transition. Output data should be sampled as shown in the timing diagram (figure 5). The OR pin is an out-of-range pin; if the outputs go either over or under range, OR is set high. PCB LAYOUT AND DECOUPLING A well designed PCB is necessary to get good spectral purity from any high-performance ADC. A multilayer PCB with a solid ground plane is recommended for optimum performance. If the system has a split analog and digital ground plane, it is recommended that all ground pins on the ADC be connected to the analog ground plane. It is our experience that this gives the best performance. The power supply pins should be bypassed using 100 nF surface mounted capacitors as close to the package pins as possible. Analog and digital supply pins should be separately filtered. VIHD VICM VILD VID Figure 4 – Driving Differential Inputs with a Single-Ended Configuration VIH VICM VIL Figure 5 – Timing Diagram N–1 AIN Clock Clock tAP N N+1 N+2 N+3 tH tD Data Data N–1 Data N Data N+1 Data N+2 SPT7864 6 11/20/01 PACKAGE OUTLINE 28-Lead SSOP INCHES 28 MILLIMETERS MIN 9.90 0.05 0.22 0.09 1.65 0.55 7.40 5.00 MAX 10.50 0.20 0.38 0.25 1.85 0.95 8.20 5.60 SYMBOL A IH MIN 0.390 0.002 0.009 0.004 0.065 0.022 0.291 0.197 MAX 0.413 0.008 0.015 0.010 0.073 0.037 0.323 0.220 B C D 0.026 typ 0.65 BSC 1 E F G A F H I B C H D G E SPT7864 7 11/20/01 PIN ASSIGNMENTS PIN FUNCTIONS Name Function GND Analog ground VDD Analog +5 V OGND Output ground OVDD REFL Supply voltage for digital outputs 3 V/5 V Reference pin low, input for exter nal reference, bypass with capacitor (10 µF) when internal reference is selected. REFH Reference pin high, input for external reference, bypass with capacitor (10 µF) when internal voltage is selected. VCM 2.5 V common mode voltage reference output VIN Non-inver ted analog input VIN Inver ted analog input CLK Clock input pin CLK Complement of clock input pin, internally biased to 1.5 V; if single-ended clock is used, bypass to GND with 10 µF D0–D9 Digital outputs; D0 = LSB; 3 V/5 V compatible OR Out-of-range bit; 3 V/5 V compatible EXT/INT EXT/INT = 1, external reference used; internal reference powered down EXT/INT = 0, internal reference used; internally pulled down Sleep Sleep = 1, nor mal operation; internally pulled up Sleep = 0, powered-down mode GND VDD REFL REFH EXT/INT VCM GND VDD VIN 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 D0 D1 D2 D3 D4 OGND OVDD OGND OVDD D5 D6 D7 D8 D9 (MSB) SPT7864 28L SSOP 22 21 20 19 18 17 16 15 VIN 10 Sleep 11 CLK 12 CLK 13 OR 14 ORDERING INFORMATION PART NUMBER SPT7864SCR TEMPERATURE RANGE 0 to +70 °C PACKAGE TYPE 28L SSOP SPT7864 8 11/20/01