SPT7922SCJ

SPT7922 12-BIT, 30 MSPS, TTL, A/D CONVERTER FEATURES • • • • • • • • Monolithic 12-Bit 30 MSPS Converter 64 dB SNR @ 3.58 MHz Input On-Chip Track/Hold Bipolar ±2.0 V Analog Input Low Power (1.1 W Typical) 5 pF Input Capacitance TTL Outputs APPLICATIONS • • • • • • • • Radar Receivers Professional Video Instrumentation Medical Imaging Electronic Warfare Digital Communications Digital Spectrum Analyzers Electro-Optics GENERAL DESCRIPTION The SPT7922 A/D converter is the industry's first 12-bit monolithic analog-to-digital c onverter capable of sample rates of greater than 30 MSPS. On board input buffer and track/hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Logic inputs and outputs are TTL. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.1 watts with power supply voltages of +5.0 and -5.2 volts. The SPT7922 also provides a wide input voltage range of ±2.0 volts. The SPT7922 is available in 32-lead ceramic sidebrazed D I P and 44-lead cerquad packages over the commercial temperature range. C onsult the factory for availability of die, military temperature and /883 versions. BLOCK DIAGRAM VIN Input Buffer 4-Bit Flash Converter 4 Error Correction, Decoding and Output TTL Drivers Digital Output 12 Analog Gain Compression Processor Track-and-Hold Amplifiers Asynchronous SAR 8 ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VCC ...........................................................................+6 V VEE ........................................................................... -6 V Input Voltages Analog Input .............................................. VFB≤VIN≤VFT VFT, VFB. ................................................... +3.0 V, -3.0 V Reference Ladder Current ....................................... 12 m CLK IN ...................................................................... VCC Note: Output Digital Outputs .............................................. 0 to -30 mA Temperature Operating Temperature ................................. 0 to +70 °C Junction Temperature ......................................... +175 °C Lead Temperature, (soldering 10 seconds) ....... +300 °C Storage Temperature ...............................-65 to +150 °C 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=30 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error Reference Input Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN=500 kHz fIN=1 MHz fIN=3.58 MHz Signal-To-Noise Ratio (without Harmonics) fIN=500 kHz fIN=1 MHz fIN=3.58 MHz TEST CONDITIONS TA=+25 °C ± Full Scale 100 kHz Sample Rate fCLK=1 MHz TA=+25 °C TA=+25 °CVIN=0 V 3 dB Small Signal VI I I V V V V VI V VI V IV V V V TEST LEVEL MIN 12 SPT7922 TYP MAX UNITS Bits LSB LSB V V VI ±2.0 ±0.8 Guaranteed ±2.0 30 300 5 120 ±5.0 ±5.0 800 0.8 40 20 14 1 5 1 18 60 100 V µA kΩ pF MHz LSB LSB Ω Ω/°C MHz ns Clock Cycle fCLK=1 MHz 500 30 TA=+25 °C TA=+25 °C TA=+25 °C ns ns ps-RMS 10.0 9.8 9.5 Bits Bits Bits TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX I IV I IV I IV 63 58 63 58 62 58 66 61 65 60 64 60 dB dB dB dB dB dB SPT7922 2 3/10/97 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=30 MHz, 50% clock duty cycle, unless otherwise specified. TEST CONDITIONS TEST LEVEL SPT7922 TYP PARAMETERS Dynamic Performance Harmonic Distortion fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Signal-to-Noise and Distortion (SINAD) fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Spurious Free Dynamic Range1 Differential Phase2 Differential Gain2 Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) Digital Outputs Logic 1 Voltage Logic 0 Voltage Power Supply Requirements Voltages VCC DVCC -VEE Currents ICC DICC -IEE Power Dissipation Power Supply Rejection MIN MAX UNITS TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=TMIN to TMAX TA=+25 °C TA=+25 °C TA=+25 °C fCLK=1 MHz TA=+25 °C TA=+25 °C TA=+25 °C TA=+25 °C I IV I IV I IV 63 59 62 58 59 57 65 61 64 60 61 59 dB dB dB dB dB dB I IV I IV I IV V V V I I I I IV IV I I IV IV IV I I I VI V 60 55 59 55 57 54 62 57 61 57 59 56 74 0.2 0.7 4.5 0.8 +20 +20 300 dB dB dB dB dB dB dB Degree % V V µA µA ns ns V V V V V mA mA mA W LSB 2.4 0 0 15 15 2.4 +5 +5 fCLK=1 MHz TA=+25 °C TA=+25 °C 0.6 4.75 4.75 -4.95 5.0 5.0 -5.2 135 40 45 1.1 1.0 5.25 5.25 -5.45 150 55 70 1.3 TA=+25 °C TA=+25 °C TA=+25 °C 5 V ±0.25 V, -5.2 ±0.25 V Typical thermal impedances (unsoldered, in free air): 32L sidebrazed DIP: θja = +50 °C/W 44L cerquad: θja = +78 °C/W θja at 1 M/s airflow = +58 °C/W θjc = +3.3 °C/W 1fIN = 1 MHz. 2fIN = 3.58 and 4.35 MHz. SPT7922 3 3/10/97 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Figure 1A: Timing Diagram N N+1 N+2 t pwH CLK t pwL td OUTPUT DATA N-2 N-1 DATA VALID N DATA VALID N+1 Figure 1B: Single Event Clock CLK td OUTPUT DATA DATA VALID Table I - Timing Parameters PARAMETERS DESCRIPTION MIN TYP MAX UNITS td tpwH tpwL CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width 15 15 14 - 18 300 - ns ns ns SPT7922 4 3/10/97 SPECIFICATION DEFINITIONS APERTURE DELAY Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels that is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. DIFFERENTIAL NONLINEARITY (DNL) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) INTEGRAL NONLINEARITY (INL) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal. N= SINAD - 1.76 6.02 +/- FULL-SCALE ERROR (GAIN ERROR) Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage. SPT7922 5 3/10/97 PERFORMANCE CHARACTERISTICS SNR vs Input Frequency 80 80 THD vs Input Frequency 70 70 fs = 30 MSPS Total Harmonic Distortion (dB) fs = 30 MSPS 60 Signal-to-Noise Ratio (dB) 60 50 50 40 40 30 30 20 100 101 102 20 100 101 102 Input Frequency (MHz) Input Frequency (MHz) SINAD vs Input Frequency 80 80 SNR, THD, SINAD vs Sample Rate Signal-to-Noise and Distortion (dB) 70 70 SNR, THD SNR, THD, SINAD (dB) fs =30 MSPS 60 60 SINAD 50 50 fIN = 1 MHz 40 40 30 30 20 100 101 102 20 100 101 102 Input Frequency (MHz) Sample Rate (MSPS) Spectral Response 0 dB 75 SNR, THD, SINAD vs Temperature -30 dB 70 S NR, THD, SINAD (dB) Amplitude (dB) SNR 65 -60 dB THD 60 -90 dB fS = 30 MSPS fIN = 1 MHz 55 SINAD -120 dB 0 1 2 3 Frequency (MHz) 4 5 50 25 0 +25 +50 +75 Temperature SPT7922 6 3/10/97 TYPICAL INTERFACE CIRCUIT The SPT7922 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7922 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7922 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog VCC. These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7922 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 µF for VEE and VCC, and 0.01 µF for DVCC (chip caps are preferred). AGND and DGND are the two grounds available on the SPT7922. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DV CC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7922. VOLTAGE REFERENCE The SPT7922 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. The +2.5 V voltage source for reference VFT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are five reference ladder taps (VST, VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRT2 is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). VRT1 and VRT3 are quarter point ladder taps (+1.0 and -1.0 V typical, respectively). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). VST and VSB should be used to monitor the actual full scale input voltage of the device. VRT1, VRT2 and VRT3 should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 µF connected to AGND from each tap is recommended to minimize high frequency noise injection. Figure 2 - Typical Interface Circuit R1 CLK (TTL) 17 CLK 100 Ω D12 VIN 14 (OVERRANGE) 13 12 11 10 9 8 7 6 5 4 3 2 (LSB) (MSB) VIN (±2 V) ± 2.5 V Max 24 COARSE A/D 4 D11 D10 D9 D I G IT A L O UT P UT S D E C O D I N G N ETW O R K + 5V C19 1 µF 2 + VIN IC1 6 VOUT +2.5 V 21 VFT D8 D7 D6 D5 D4 D3 D2 D1 (REF-03) 4 GND Trim 5 10 kΩ + 1 µF 30 kΩ C1 .01 µF C2 .01 µF C3 .01 µF C4 .01 µF 22 VST 23 VRT3 25 VRT2 R ANALOG PRESCALER 2R 2R 2R SUCCESSIVE INTERPOLATION STAGE # 1 3 1 10 kΩ 2 4 +IC2 OP-07 8 7 - 5.2 V C5 .01 µF C17 .01 µF 30 kΩ C6 .01 µF 26 VRT1 2R 27 VSB R SUCCESSIVE INTERPOLATION STAGE # N +5 V C18 .01 µF D0 6 -2.5 V C16 1 µF C7 .01 µF 28 VFB DGND AGND DVCC + 18 31 19 C8 .1 µF C9 .1 µF 30 20 C10 C11 29 16 32 DVCC 1 15 C12 .01 µF C13 .01 µF Notes to prevent latch-up due to power sequencing: 1) D1 = Schottky or hot carrier diode, P/N IN5817. 2) FB = Ferrite bead, Fair Rite P/N 2743001111 to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C13 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for VCC and DVCC is not recommended. 5) R1 provides current limiting to 45 mA. 6) C8, C9, C10 and C11 should be ten times larger than C12 and C13. 7) C10 = C11 = 0.1 µF cap in parallel with a 4.7 µF cap. DGND FB AGND VCC VEE VEE VCC D1 C15 10 µF C14 10 µF + + FB -5.2 V (Analog) AGND +5 V (Analog) FB DGND SPT7922 7 3/10/97 Figure 3 - Analog Equivalent Input Circuit VCC CLOCK INPUT The SPT7922 is driven from a single-ended TTL input (CLK). The CLK pulse width (tpwH) must be kept between 15 ns and 300 ns to ensure proper operation of the internal track-andhold amplifier. (See timing diagram.) When operating the SPT7922 at sampling rates above 3 MSPS, it is recommended that the clock input duty cycle be kept at 50% to optimize performance. (See figure 4.) The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH ≤4.5 V, TRISE +2.0 V + 1/2 LSB +2.0 V -1 LSB 0.0 V -2.0 V +1 LSB