SPT7936

SPT7936 12-BIT, 28 MSPS SAMPLING A/D CONVERTER FEATURES • • • • • • • 3.0-3.6 V Power Supply Typical SINAD: 60 dB for (fIN = 10 MHz) Low power: (260 mW @3.3 V) Sample Rate: 28 MSPS Internal Sample/Hold Differential Input Sleep Mode (Power Down) APPLICATIONS • • • • • Imaging Test Equipment Computer Scanners Communications Set-Top Boxes GENERAL DESCRIPTION The SPT7936 is a compact, high-speed, low power 12-bit monolithic analog-to-digital converter, implemented in a 0.5 µm CMOS process. The converter includes sample and hold. The full scale range can be set between ±0.6 V and ±1.2 V using external references. It operates from a single 3.0-3.6 V supply-compatible with modern digital systems. Most converters in this performance range demand at least a +5 V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The SPT7936 has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The device is available in a 44L TQFP package over the commercial temperature range of 0 to +70 °C. BLOCK DIAGRAM BGAP Bias 0 Bias 1 CM Ref Buff Ref Buff BGREF BIAS CELL Ext Ref VREF+ VREFVIN+ VIN- THA Stage 1 Stage 2 Stage 3 Stage 10 Stage_Last (2-Bit Flash) Clock Clock Driver Digital Delays, Error Correction and Output Register OR Bit 75 dB - Gain bandwidth product >50 MHz - Total harmonic distortion ≤-75 dB - Signal to Noise ratio >75 dB REFERENCES The SPT7936 can use either an internal or external voltage reference. When the digital input EXTREF is high, the external reference is used. When EXTREF is low, the internal reference is used. INTERNAL REFERENCE The internal references are set at +1.0 V and +2.0 V. When the internal reference is used, the full-scale range of the analog input is set at ±1.0 V differential. Do not connect external references when the internal reference is used. EXTERNAL REFERENCE When external references are used, the voltages applied to the VREF+ and VREF- pins determine the input voltage range which is equal to ±(VREF+ - VREF-). Externally generated reference voltages must be connected to these pins and should be symmetric about the common mode voltage. (See figure 2, Typical Interface Circuit.) COMMON MODE OUTPUT VOLTAGE REFERENCE CIRCUIT The SPT7936 has an on-board common mode voltage reference circuit (VCM). It is set at +1.5 V and can drive loads of up to 20 µA. This circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Figure 3 - DC-Coupled Single-Ended-to-Differential Conversion (Power Supplies are Not Shown) R3 VCM (R3)/2 _ + Input Voltage (±0.5 V) R2 + 15 pF R2 51 Ω R R + _ R VIN– 51 Ω R3 R _ 51 Ω VIN+ R ADC BIAS CIRCUITS The best AC performance is achieved when the bias currents are optimized for the selected sample rate. Two digital input pins are provided to control the optimum internal bias currents. Table I shows the settings for Bias 0 and Bias 1 at selected frequencies. Table I - Frequencies for Biases 0 and 1 Typical Power Bias 1 Bias 0 0 0 0 1 1 0 1 1 *Clock = 28 MHz POWER SUPPLIES AND GROUNDING The SPT7936 is operated from a single power supply in the range of 3.0 to 3.6 volts. Nominal operation is suggested to be 3.3 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. Dissipation Description Ext. Ref. Int. Ref. Sleep mode (power save)* 25 mW 36 mW ≤5 MHz sampling 61 mW 73 mW ≤20 MHz sampling 172 mW 184 mW ≤28 MHz sampling 248 mW 260 mW SPT7936 6 8/1/00 CLOCK The SPT7936 accepts a +3.3 V CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non-50% duty cycle reduces the settling time available for every other stage, thus potentially causing a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 3 ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed. 8 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up. OUT OF RANGE OUTPUT (OR) The digital output OR goes to a logic high to indicate that the analog input is out of range. EVALUATION BOARD The EB7936 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7936. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-todifferential input buffers with adjustable levels, a single-todifferential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7936) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability. DIGITAL OUTPUTS The digital output data appears in an offset binary code at 3.3 V CMOS logic levels. A negative full scale input results in an all zeros output code (000…0). A positive full scale input results in an all 1’s code (111…1). The output data is available PACKAGE OUTLINE 44L TQFP A B INCHES SYMBOL A B C D C D MILLIMETERS MAX MIN 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.018 0.057 0.006 0.030 0.300 1.35 0.05 0.450 1.00 Typ 0-7° 0.45 1.45 0.15 0.750 MAX MIN 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.039 Typ 0-7° E F G H I J K Index Pin 1 E F G I H J K SPT7936 7 8/1/00 PIN ASSIGNMENTS D0 (LSB) 43 VDD2 44 D6 D8 D1 42 D3 40 D4 D7 D9 D5 D2 41 EXTREF Digital input: Reference select. EXTREF=1: Use external reference. Internal reference powered down. EXTREF=0: Internal reference is used. 38 37 36 39 35 34 GND CLK GND VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VREF– VREF+ 1 2 3 4 5 6 7 8 9 10 11 15 14 16 17 18 19 12 N/C 13 EXTREF 20 21 22 33 32 31 30 29 28 27 26 25 24 23 D10 D11 OR GND GND GND GND GND GND GND GND BIAS0, BIAS1 Digital inputs for maximum sampling rate programming. BIAS1=0, BIAS0=0: Sleep mode (power save) BIAS1=0, BIAS0=1: Max. 5 MHz sampling BIAS1=1, BIAS0=0: Max. 20 MHz sampling (Default by internal pull up/pull down) BIAS1=1, BIAS0=1: Max. 28 MHz sampling CLOCK CM D11-DØ Clock input Common mode voltage output. (1.5 V typ) Digital outputs ( MSB to LSB) Out-of-Range digital output. OR=1 indicates input out of range Analog power supply Digital power supply Analog Ground No Connect Pins. Recommended to connect to analog ground. Internal Bandgap Reference Output: Bypass to ground for normal operation. GND GND PIN FUNCTIONS Name VIN+, VINVREF+, VREFFunction Differential input signal pins. Reference input pins. Bypass with 100 nF capacitors close to the pins. See Application Information. ORDERING INFORMATION PART NUMBER SPT7936SCT TEMPERATURE RANGE 0 to +70 °C PACKAGE TYPE 44L TQFP BGAP GND VIN– Bias0 Bias1 VIN+ CM OR VDD1 VDD2 GND N/C BGAP SPT7936 8 8/1/00