SPT7938SIR

SPT7938 12-BIT, 40 MSPS, 170 mW A/D CONVERTER FEATURES • • • • • • • Monolithic 40 MSPS Analog-to-Digital Converter 170 mW Power Dissipation On-Chip Track-and-Hold Single +5 V Power Supply TTL/CMOS Outputs 20 pF Input Capacitance Selectable +3 V or +5 V Logic I/O APPLICATIONS • All High-Speed Applications Where Low Power Dissipation Is Required • Video Imaging • Medical Imaging • Radar Receivers • IR Imaging • Digital Communications GENERAL DESCRIPTION The SPT7938 is a 12-bit monolithic, low-cost, low-power analog-to-digital converter capable of minimum word rates of 40 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the SPT7938’s low input capacitance of only 20 pF. Power dissipation is extremely low at only 170 mW typical at 40 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. The SPT7938 has incorporated proprietary circuit design and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7938 is available in a 28-lead SSOP package over the industrial temperature range. BLOCK DIAGRAM ADC Section 1 AIN 1:18 Mux T/H AutoZero CMP 13-Bit SAR 13 13 D12 Out of Range D11 (MSB) D10 P1 P2 CLK In Timing P17 and Control P18 DAC D9 ADC Section 2 13 D8 13-Bit 18:1 Mux/ Error Correction D7 D6 D5 D4 D3 D2 D1 Reference Ladder EN DØ (LSB) . . . . . . . . . . . . ADC Section 17 ADC Section 18 T/H AutoZero CMP 13 13-Bit SAR 13 DAC 13 VRHF VRHS VRLS VRLF ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VDD ............................................................................ +6 V Input Voltages Analog Input .................................... –0.5 V to VDD +0.5 V CLK Input ................................................................... VDD AGND – DGND .................................................. ±100 mV Output Digital Outputs ....................................................... 10 mA Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Temperature Operating Temperature ............................. –40 to +85 °C Junction Temperature ......................................... +175 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C ELECTRICAL SPECIFICATIONS T A=TMIN to TMAX, V DD =+5.0 V, ƒS=40 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth –Full-Scale Error1 +Full-Scale Error1 Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Over-Voltage Recovery Time2 Reference Input Resistance Voltage Range VRHS VRLS VRHS – VRLS Dynamic Performance Effective Number of Bits ƒIN=3.58 MHz ƒIN=3.58 MHz Signal-to-Noise Ratio (without Harmonics) ƒIN=3.58 MHz ƒIN=3.58 MHz 1 The 2 TEST CONDITIONS TEST LEVEL MIN 12 SPT7938 TYP MAX UNITS Bits V V VI VI V V V V V VI V IV V V VRLS ±3 ±1 Guaranteed VRHS 25 5.0 250 0.035 –0.12 40 1 14 1.0 5.0 25 LSB LSB VIN = 2 VPP V kΩ pF MHz %FS %FS MHz MHz Clock Cycles ns ps(p-p) ns Ω V V V VI IV IV V 420 3.0 0.0 2.0 465 520 VDD 2.0 5.0 4.0 TA = +25 °C TA = TMIN to TMAX TA = +25 °C TA = TMIN to TMAX I IV 9.9 9.4 10.1 10.1 Bits Bits I IV 61.2 58.0 62.5 62.5 dB dB full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion. Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒCLK = 40 MHz). SPT7938 2 5/24/00 ELECTRICAL SPECIFICATIONS T A =TMIN to TMAX, V DD =+5.0 V, ƒS=40 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Harmonic Distortion ƒIN=3.58 MHz ƒIN=3.58 MHz Signal-to-Noise and Distortion (SINAD) ƒIN=3.58 MHz ƒIN=3.58 MHz Spurious Free Dynamic Range ƒIN=3.58 MHz Differential Phase Differential Gain Clock Input Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Input Duty Cycle Output Enable Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Output Enable to Data Output Delay Power Supply Requirements Voltages OVDD VDD Currents IDD Power Dissipation Power Supply Rejection Ratio IOH = 0.5 mA IOL = 1.6 mA 20 pF load IV IV IV IV VI VI 3.0 4.75 TEST CONDITIONS TEST LEVEL MIN SPT7938 TYP MAX UNITS TA = +25 °C TA = TMIN to TMAX TA = +25 °C TA = TMIN to TMAX I IV –62.5 –62.0 –71 –71 dB dB I IV V V V VI VI VI VI V V VI VI VI VI 60.2 57.5 62 62 73 0.25 0.5 dB dB dB Degree % V V µA µA pF % V V µA µA V V ns ns V V mA mW dB 2.0 –10 –10 45 3.5 –10 –10 VDD–0.5 0.42 15 10 5.0 5.25 40 200 1.5 +10 +10 5 50 0.8 +10 +10 55 5.0 34 170 60 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT7938 3 5/24/00 Figure 1A – Timing Diagram 1 1 1 1 3 9 13 17 5 7 15 ANALOG IN CLOCK IN SAMPLING CLOCK (Internal) INVALID VALID DATA OUTPUT DATA VALID 1 2 3 Figure 1B – Timing Diagram 2 tCLK tC tCH CLOCK IN tCL DATA OUTPUT Data Ø Data 1 Data 2 Data 3 tOD tS DATA VALID tCH tS tCL SPT7938 4 5/24/00 Figure 2 – Typical Interface Circuit CLK IN DOVSS FB2 OTR D11 D10 D9 Out of Range Bit MSB DVSS CLK DVDD AVSS VINR FB3 + SPT7938 +A5 + AVDD D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB AIN +A5 U1 + VIN RVSS VRHS VRHF VRLF VRLS 28 TK11240B Ext VREF (+4 V) EN DOVDD 1 FB1 + +D3/5V +A5 + 10 +A5 AGND +D3/5V +D3/5 + 10 +D3/5 DGND Notes: 1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad surface-mount chip capacitors. They need to be placed as close to the pin as possible. 2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors. 3) FB1, FB2 and FB3 are ferrite beads. Place FB1 as close to the SPT7938 as possible. 4) U1 is a TOKO regulator, TK112XXB. XX is the regulated output voltage ranging from 1.3 V to 4.8 V with 100 mV increment. For example, TK11240B is a 4.0 V regulator. TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7938 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING CADEKA suggests that both the digital (DV ) and the anaDD log (AVDD) supply voltages on the SPT7938 be derived from a single analog supply as shown in figure 2. A separate digital supply should be used for the digital output driver supply (OVDD) and all interface circuitry. CADEKA suggests using this power supply configuration to prevent a possible latchup condition on power up. In addition, the power supplies must be powered up before the analog input is applied. SPT7938 5 5/24/00 Interfacing Logic OPERATING DESCRIPTION The general architecture for the CMOS ADC is shown in the block diagram. The design contains 18 identical successive approximation ADC sections (all operating in parallel), an 18-phase clock generator, a 13-bit 18:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 18 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II – Clock Cycles Clock 1 2 3 4 5-17 18 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 13-bit SAR conversion Data transfer VOLTAGE REFERENCE The SPT7938 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage fullscale range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. For optimum performance the full-scale voltage range (VRHS–VRLS) should be between 3 V to 5 V. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±3 LSB can be obtained. Figure 3 – Ladder Force/Sense Circuit 1 AGND + – 2 VRHF 3 VRHS 6 + – The 18-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one ADC section. After 18 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 14 clock cycles. • Since only 18 comparators are used, a huge power savings is realized. • The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator’s response to a reference zero. • The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. • Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. • The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. 4 5 N/C VRLS 6 VRLF 7 VIN All capacitors are 0.01 µF SPT7938 5/24/00 Figure 4 – Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit +4.0 V External Reference VRHS (+3.98 V) ANALOG INPUT VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See the Voltage Reference section.) The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7938’s extremely low input capacitance of only 20 pF and very high input resistance in excess of 25 kΩ. 21 mV R/2 R R R R=30 Ω (typ) All capacitors are 0.01 µF R The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. To prevent possible latch-up condition, the power supplies must be powered up before the input is applied. Figure 5 – Recommended Input Protection Circuit +V AVDD R R VRLS (0.050 V) VRLF (AGND) 0.0 V 50 mV R/2 D1 Buffer 47 Ω D2 ADC In cases in which wider variations in offset and gain can be tolerated, VRef can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a 0.01 µF capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF – VRHS = 0.5% of (VRHF – VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 1.25% of (VRHF – VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 21 mV drop is seen at VRHS (= 3.98 V) and a 50 mV increase is seen at VRLS (= 0.050 V). –V D1 = D2 = Hewlett Packard HP5712 or equivalent CALIBRATION The SPT7938 uses a user-transparent, auto-calibration scheme to ensure 12-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 12-bit accuracy during device operation. Upon powerup, the SPT7938 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 12bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power-up of 250 µsec (for a 40 MHz clock). Once calibrated, the SPT7938 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7938 to remain in calibration. SPT7938 7 5/24/00 Figure 6 – On-Chip Protection Circuit VDD 120 Ω DIGITAL OUTPUTS Analog 120 Ω Pad The digital outputs (D0–D12) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7938’s TTL/CMOS-compatible outputs with the user’s logic system supply. The format of the output data (D0–D11) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing EN high. Table III – Output Data Information ANALOG INPUT +F.S. + 1/2 LSB +F.S. –1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V OVERRANGE D12 1 0 0 0 0 OUTPUT CODE D11–D0 11 1111 1111 11 1111 111Ø ØØ ØØØØ ØØØØ 00 0000 000Ø 00 0000 0000 INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. (Ø indicates the flickering bit between logic 0 and 1). OVERRANGE OUTPUT The Overrange Output (D12) is an indication that the analog input signal has exceeded the positive full-scale input voltage by 1 LSB. When this condition occurs, D12 will switch to logic 1. All other data outputs (D0 to D11) will remain at logic 1 as long as D12 remains at logic 1. This feature makes it possible to include the SPT7938 in higher resolution systems. CLOCK INPUT The SPT7938 is driven from a single-ended TTL-input clock. The duty cycle of the clock should be kept as close to 50% (±5%) as possible. EVALUATION BOARD The EB7938 evaluation board is available to aid designers in demonstrating the full performance of the SPT7938. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7938) describing the operation of this board, as well as information on the testing of the SPT7938, is also available. Contact the factory for price and availability. SPT7938 8 5/24/00 PACKAGE OUTLINE 28-Lead SSOP INCHES SYMBOL A B 28 MILLIMETERS MIN 10.07 0.05 0.25 0.09 1.68 0.63 7.65 5.20 MAX 10.33 0.21 0.65 typ 0.38 0.20 1.78 0.95 7.90 5.38 MIN 0.397 0.002 0.010 0.004 0.066 0.025 0.301 0.205 MAX 0.407 0.008 0.0256 typ 0.015 0.008 0.070 0.037 0.311 0.212 C D IH E F G H I 1 A F B C D E H G SPT7938 9 5/24/00 PIN ASSIGNMENTS DOVDD D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 (MSB) OTR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 EN VRLS VRLF VRHF VRHS RGND VIN VINR AGND AVDD DVDD1 CLK DGND DOGND PIN FUNCTIONS Name DOVDD D0–D11 OTR DOGND DGND CLK DVDD1 AVDD AGND VINR VIN RGND VRHS VRHF VRLS VRLF EN Function Digital Output Driver Supply Data Output, Bits 0 – Bit 11 Out of Range Digital Output Driver Ground Digital Ground Input Clock Digital VDD Analog VDD Analog Ground Analog Input Return Analog Input, Full Scale from VRLS to VRHS Analog Ground Shield (Junction Isolated) Reference High Sense Reference High Force (VRHF≤AVDD) Reference Low Sense Reference Low Force Output Enable (Active Low) 28L SSOP 21 20 19 18 17 16 15 ORDERING INFORMATION PART NUMBER SPT7938SIR TEMPERATURE RANGE –40 to +85 °C PACKAGE TYPE 28L SSOP SPT7938 10 5/24/00