SPT9712

SPT9712 12-BIT, 100 MWPS ECL D/A CONVERTER TECHNICAL DATA FEBRUARY 15, 2001 FEATURES • 12-Bit, 100 MWPS digital-to-analog conver ter • ECL compatibility • Low power: 600 mW • 1/2 LSB DNL • 40 MHz multiplying bandwidth • Industrial temperature range • Superior performance over AD9712 – Improved settling time of 13 ns – Improved glitch energy 15 pV-s – Master-slave latches APPLICATIONS • Fast frequency hopping spread spectrum radios • Direct sequence spread spectrum radios • Microwave and satellite modems • Test & measurement instrumentation GENERAL DESCRIPTION The SPT9712 is a 12-bit, 100 MWPS digital-to-analog conver ter designed for direct digital synthesis, high resolution imaging, and arbitrary waveform generation applications. This device is pin-for-pin compatible with the AD9712 with significantly improved perfor mance. The only difference between the SPT9712 and the AD9712 is that the Latch Enable (LE, pin 26) for the SPT9712 is rising-edge triggered (see figure 1), whereas the Latch Enable (LE, pin 26) for the AD9712 functions in the transparent mode. The SPT9712 is an ECL-compatible device. It features a fast settling time of 13 ns and low glitch impulse energy of 15 pV-s, which results in excellent spurious-free dynamic range characteristics. The SPT9712 is available in a 28-lead PLCC package in the industrial temperature range (–40 to +85 °C). BLOCK DIAGRAM RSet Control Amp In Ref Out Latch Enable (MSB) + – Control Amp Internal Voltage Reference Control Amp Out Ref In Digital Inputs D1 through D12 Decoders and Drivers IOut Latches Switch Network IOut (LSB) ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Negative Supply Voltage (VEE) .............................. –7 V A/D Ground Voltage Differential ........................... 0.5 V Input Voltages Digital Input Voltage (D1–D12, Latch Enable) ............................... 0 V to VEE Control Amp Input Voltage Range ............... 0 V to –4 V Reference Input Voltage Range (VREF) ........ 0 V to VEE Output Currents Internal Reference Output Current .................... 500 µA Control Amplifier Output Current ..................... ±2.5 mA Temperature Operating Temperature .......................... –40 to +85 °C Junction Temperature ...................................... +150 °C Lead, Soldering (10 seconds) ......................... +300 °C Storage ................................................ –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = TMIN – TMAX, VEE = –5.2 V, RSet = 7.5 kΩ, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified. PARAMETERS DC Performance Resolution Differential Linearity Differential Linearity Integral Linearity Integral Linearity Output Capacitance Gain Error1 Gain Error Tempco Zero-Scale Offset Error Offset Drift Coefficient Output Compliance Voltage Equivalent Output Resistance Dynamic Performance Conversion Rate Settling Time tST2 Output Propagation Delay tD3 Glitch Energy4 Full Scale Output Current5 Spurious-Free Dynamic Range6 1.23 MHz; 10 MWPS 5.055 MHz; 20 MWPS 10.1 MHz; 50 MWPS 16 MHz; 40 MWPS Rise Time / Fall Time Power Supply Requirements Negative Supply Voltage Negative Supply Current (–5.2 V) Nominal Power Dissipation Power Supply Rejection Ratio 1Gain TEST CONDITIONS TEST LEVEL SPT9712A MIN TYP MAX 12 ±0.5 SPT9712B MIN TYP MAX 12 ±1.0 ±1.0 10 1.0 150 0.5 0.01 –1.2 0.8 100 1.0 +2.0 1.2 UNITS Bits LSB LSB LSB LSB pF % FS % FS PPM/°C µA µA µA/°C V kΩ MWPS ns ns pV-s mA dBc dBc dBc dBc ns Max at Full Temp. Best Fit Max at Full Temp. +25 °C +25 °C Full Temp. Full Temp. +25 °C Full Temp. Full Temp. +25 °C +25 °C +25 °C +25 °C +25 °C +25 °C +25 °C +25 °C 2 MHz Span 2 MHz Span 2 MHz Span 10 MHz Span RL = 50 Ω I VI I VI V I VI V I VI V IV IV IV V V V V V V V V V IV I VI V I –1.2 0.8 100 ±0.75 ±1.5 ±0.75 ±1.0 ±1.75 10 1.0 5.0 8.0 150 0.5 2.5 5.0 0.01 +2.0 1.0 1.2 ±1.25 ±2.0 ±1.5 ±2.0 5.0 8.0 2.5 5.0 13 1 15 20.48 70 68 68 68 2 –5.46 –5.2 115 600 30 –4.94 140 148 100 –5.46 13 1 15 20.48 70 68 68 68 2 –5.2 115 600 30 –4.94 140 148 100 +25 °C Full Temp ±5% of VEE External Ref, +25 °C V mA mA mW µA/V is measured as a ratio of the full-scale current to ISet. The ratio 2Measured as voltage at mid-scale transition to ±0.024%; RL=50 Ω. 4Glitch is measured as the largest single transient. 5Calculated is nominally 128. 3Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band. using IFS = 128 x (Control Amp In / RSet) 6SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. SPT9712 2 2/15/01 ELECTRICAL SPECIFICATIONS TA = TMIN – TMAX, VEE = –5.2 V, RSET = 7.5 kΩ, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified. PARAMETERS Voltage Input and Control Reference Input Impedance Ref. Multiplying Bandwidth Internal Reference Voltage Internal Reference Voltage Drift Amplifier Input Impedance Amplifier Input Bandwidth Digital Inputs Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time – tS Input Setup Time – tS Input Hold Time – tH Input Hold Time – tH Latch Pulse Width – tPWL, tPWH TEST CONDITIONS +25 °C +25 °C +25 °C +25 °C Full Temp. Full Temp. Full Temp. Full Temp. +25 °C +25 °C Full Temp. +25 °C Full Temp. +25 °C TEST LEVEL V V VI V V V VI VI VI VI V IV IV IV IV IV SPT9712A MIN TYP MAX 3 40 –1.15 –1.20 –1.25 50 3 1 –1.0 –0.8 –1.7 3 2 0 4.0 SPT9712B MIN TYP MAX 3 40 –1.15 –1.20 –1.25 50 3 1 –1.0 –0.8 –1.7 3 2 0 4.0 UNITS kΩ MHz V ppm/°C MΩ MHz V V µA µA pF ns ns ns ns ns –1.5 20 10 3 3.5 0.5 0.5 5.0 –1.5 20 10 3 3.5 0.5 0.5 5.0 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT9712 3 2/15/01 THEORY OF OPERATION The SPT9712 uses a segmented architecture incorporating most significant bit (MSB) decoding. The four MSBs (D1–D4) are decoded to thermometer code lines to drive 15 discrete current sinks. For the eight least significant bits (LSBs), D5 and D6 are binary weighted and D7–D12 are applied to the R-2R network. The 12-bit decoded data is input to internal master/slave latches. The latched data is input to the switching network and is presented on the output pins as complementary current outputs. VOLTAGE REFERENCE When using the internal reference, Ref Out should be connected to Control Amp In and decoupled with a 0.1 µF capacitor. Control Amp Out should be connected to Ref In and decoupled to the analog supply. (See figure 2.) Full-scale output current is determined by Control Amp In and RSet using the following formula: IOut (FS) = (Control Amp In / RSet) x 128 (Current Out is a constant 128 factor of the reference current) The internal reference is typically –1.20 V with a tolerance of ±0.05 V and a typical drift of 50 ppm/°C. If greater accuracy or temperature stability is required, an external reference can be utilized. TYPICAL INTERFACE CIRCUIT The SPT9712 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT9712 in normal circuit operation. The following sections provide descriptions of the pin functions and outline critical performance criteria to consider for achieving optimal device performance. OUTPUTS The output of the SPT9712 is comprised of complementary current sinks, IOut and IOut. The output current levels at either IOut or IOut are based upon the digital input code. The sum of the two is always equal to the full-scale output current minus one LSB. By terminating the output current through a resistive load to ground, an associated voltage develops. The effective resistive load (REff) is the output resistance of the device (ROut) in parallel with the resistive load (RL). The voltage which develops can be determined using the following formulas: Control Amp Out = –1.2 V, and RSet = 7.5 kΩ IOut (FS) = (–1.2 V / 7.5 kΩ) x 128 = –20.48 mA RL = 51 Ω ROut = 1.0 kΩ REff = 51 Ω || 1.0 kΩ = 48.52 Ω VOut = REff x IOut (FS) = 48.52 Ω x –20.48 mA = –0.994 V The resistive load of the SPT9712 can be modified to incorporate a wide variety of signal levels. However, optimal device performance is achieved when the outputs are equivalently loaded. POWER SUPPLIES AND GROUNDING The SPT9712 requires the use of a single –5.2 V supply. All supplies should be treated as analog supply sources. This means the ground returns of the device should be connected to the analog ground plane. All supply pins should be bypassed with .01 µF and 10 µF decoupling capacitors as close to the device as possible. The two grounds available on the SPT9712 are DGND and AGND. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of the SPT9712. All ground, reference and analog output pins should be tied directly to the DAC ground plane. The DAC and system ground planes should be separate from each other and only connected at a single point through a ferrite bead to reduce ground noise pickup. DIGITAL INPUTS AND TIMING The SPT9712 uses single-ended, 10K ECL-compatible inputs for data inputs D1–D12 and Latch Enable. It also employs master/slave latches to simplify digital interface timing requirements and reduce glitch energy by synchronizing the current switches. This is an improvement over the AD9712, which typically requires external latches for digital input synchronization. Referring to figure 1, data is latched into the DAC on the rising edge of the latch enable clock with the associated setup and hold times. The output transition occurs after a typical 1 ns propagation delay and settles to within ±1 LSB in typically 13 ns. Because of the SPT9712’s rising-edge triggering, no timing changes are required when replacing an AD9712 operating in the transparent mode. SPT9712 4 2/15/01 Figure 1 – Timing Diagram Latch Enable –1.3 V tPWL tS Data Inputs tH tPWH –1.3 V tD 1 LSB OUT– OUT+ tST 1/2 LSB Figure 2 – Typical Interface Circuit –5.2 V 10 µF 0.1 µF 0.1 µF 0.001 µF 23 N/C 28 1 2 3 4 5 6 7 8 9 10 11 Clock Input System GND 26 D1 (MSB) D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 (LSB) LE DGND 27 IOut AGND Ref GND 13 22 14 0.001 µF 12,21 DVEE 15,25 AVEE Ref In 17 0.1 µF 20 W Control 18 Amp Out Ref Out 20 ECL Logic Drivers Digital Inputs SPT9712 Control 19 Amp In RSet IOut 24 RSet 16 RL RL VOut 0.1 µF SPT9712 5 2/15/01 PACKAGE OUTLINE 28-Lead PLCC C Pin 1 H Pin 1 TOP VIEW G I F BOTTOM VIEW A B D E INCHES SYMBOL A B C D E F G H I MIN 0.452 0.485 30° 0.170 0.020 0.031 0.013 0.048 0.410 0.179 0.025 0.035 0.021 0.052 0.430 MAX 0.456 0.495 MILLIMETERS MIN MAX 11.48 11.58 12.32 12.57 30° 4.32 4.55 0.51 0.64 0.79 0.89 0.33 0.53 1.22 1.32 10.41 10.92 SPT9712 6 2/15/01 PIN ASSIGNMENTS Latch Enable (MSB) D1 PIN FUNCTIONS Name Out+ Out– D1–D12 Latch Enable Ref In 25 24 23 Function Analog Current Output Complementary Analog Current Output Digital Input Bits (D12 is the LSB) Latch Control Line Voltage Reference Input Inter nal Voltage Reference Output Normally Connected to Control Amp In Ground Return For Inter nal Voltage Reference and Amplifier Normally Connected to Ref Out If Not Connected to External Reference DGND D5 4 D4 3 D3 2 D2 1 28 27 26 D6 D7 D8 D9 D10 D11 (LSB) D12 5 6 7 8 9 10 11 Analog VEE RSet N/C Ref GND Digital VEE Ref Out Control Amp In Ref Out Ref GND Control Amp In PLCC 22 21 20 19 Control Amp Out Output of Internal Control Amplifier Normally Connected to Ref In RSet1 Connection for Exter nal Resistance Reference When Using Internal Amplifier Nominally 7.5 kΩ Analog Return Ground Analog Negative Supply (–5.2 V) Digital Negative Supply (–5.2 V) Digital Ground Return Not Connected ORDERING INFORMATION PART NUMBER SPT9712AIP SPT9712BIP DNL/INL ±0.75/±1.0 ±1.25/±1.5 TEMPERATURE RANGE –40 to +85 °C –40 to +85 °C PACKAGE 28L PLCC 28L PLCC 12 13 14 15 16 17 18 Analog Return Analog VEE Digital VEE DGND N/C IOut Ref In Control Amp Out Digital VEE Analog Return Analog VEE IOut 1Full-Scale Current Out = 128 (Control Amp In / RSet) SPT9712 7 2/15/01