TMC2192

www.cadeka.com TMC2192 10 Bit Encoder Features • Multiple input formats – 20 bit CCIR601 – 10 bit CCIR656 – 10 bit Digital Composite • Synchronization modes – Master – Slave – Genlock – CCIR656 • Subcarrier modes – Free-run – Subcarrier reset – Genlock – DRS-lock • Ancillary Data Control (ANC) • Pixel rates from 10 MHz to 15 MHz • Programmable horizontal timing • Programmable vertical blanking interval (VBI) • Line-by-line pedestal enable • Programmable pedestal height from -20 IRE to 20 IRE • Programmable burst amplitude and phase • Controlled edge rates for – Sync – Burst – Active video • • • • • • • • • • • Programmable color space matrix 8:8:8 video reconstruction Three 10 bit D/A’s with independent trim Individual power down modes for each D/A Multiple output formats – S-video – Composite – Digital composite output Pin-driven and data-driven, window keying Closed Caption waveform generation (13.5 MHz only) Sin(X)/X compensation filter 5 bit VBI line counter 3 bit field counter Internal test pattern generation – 100% Color Bars – 75% Color Bars – Modulated Ramp Applications • Broadcast Television • Nonlinear Video Processing Block Diagram PD[23:0] C BYP LUMA PREPROCESSER OL[4:0] KEY OVERLAY MIXER y cb cr U Gain Adjustment V Chroma Modulator INTERP. LUMA R REF C BYP LUMA LUMA Y INTERP. CHROMA R REF CHROMA COMP CC CVBS[9:0] SYNC INSERT + C BYP KEY MIX INTERP. COMPOSITE RREF COMP DAC REF. FVHGEN MPU PDCIN/PDCOUT HSOUT VSOUT LINE[4:0] FLD[2:0] VSIN DCVEN\ PXCK RESET A[1:0]/SA[1:0] SERB D[7:0] R/W\/SDA CS/SCL 2194001a VREF HSIN REV. 1.0.0 8/13/03 TMC2192 PRODUCT SPECIFICATION Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications. . . . . . . . . . . . . . . . . . . . . . . . .1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .1 10 Bit Encoder . . . . . . . . . . . . . . . . . . . . . . .1 List of Figures . . . . . . . . . . . . . . . . . . . . . . .3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . .4 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .4 Functional Description . . . . . . . . . . . . . . . .7 Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Color Space Matrix . . . . . . . . . . . . . . . . . . . . . . 9 Synchronization Modes . . . . . . . . . . . . . . . . . 10 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 10 Blanking Control . . . . . . . . . . . . . . . . . . . . . . . 11 Pixel Data Control . . . . . . . . . . . . . . . . . . . . . . 11 Edge Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Horizontal Programming. . . . . . . . . . . . . . . . . 12 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chrominance Processor . . . . . . . . . . . . . . . . . Subcarrier Programming . . . . . . . . . . . . . . . NTSC Subcarrier . . . . . . . . . . . . . . . . . PAL Subcarrier . . . . . . . . . . . . . . . . . . . PAL-M Subcarrier . . . . . . . . . . . . . . . . . Subcarrier Synchronization. . . . . . . . . . . . . SCH Phase Error Correction. . . . . . . . . . . . Burst Envelope . . . . . . . . . . . . . . . . . . . . . . Color-Difference Low-Pass Filters. . . . . . . . Sync and Pedestal Insertion. . . . . . . . . . . . . . Pedestal Enable . . . . . . . . . . . . . . . . . . . . . Pedestal Height . . . . . . . . . . . . . . . . . . . . . . Sync and Blank Insertion . . . . . . . . . . . . . . Closed Caption Insertion . . . . . . . . . . . . . . . . Line Selection . . . . . . . . . . . . . . . . . . . . . . . Parity Generation . . . . . . . . . . . . . . . . . . . . Operating Sequence . . . . . . . . . . . . . . . . . . 21 21 21 21 21 22 22 23 23 23 23 24 24 24 24 24 24 Interpolation Filters . . . . . . . . . . . . . . . . . . . . . 25 x/Sin(x) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Data Formats. . . . . . . . . . . . . . . . . . . . 25 Digital Composite Output . . . . . . . . . . . . . . . . 26 Ancillary Data. . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating Modes. . . . . . . . . . . . . . . . . . . . . 27 Layering Engine. . . . . . . . . . . . . . . . . . . . . . . . 28 Overlay Mixer . . . . . . . . . . . . . . . . . . . . . . . 28 Hardware Keying . . . . . . . . . . . . . . . . . . . . . . . 29 Data Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Parallel Microprocessor Interface . . . . . . . . . 29 Serial Control Port (R-Bus) . . . . . . . . . . . . . . . 31 Data Transfer via Serial Interface . . . . . . . . 31 Serial Interface Read/Write Examples . . . . 31 Control Register Map . . . . . . . . . . . . . . . . 33 Control Register Definitions . . . . . . . . . . 35 Absolute Maximum Ratings . . . . . . . . . . . 60 Operating Conditions . . . . . . . . . . . . . . . . 60 Electrical Characteristics . . . . . . . . . . . . . 62 Switching Characteristics . . . . . . . . . . . . 62 System Performance Characteristics . . . 63 Applications Discussion . . . . . . . . . . . . . 63 Layout Considerations . . . . . . . . . . . . . . . . . . 64 Output Low-Pass Filters . . . . . . . . . . . . . . . . . 67 Mechanical Dimensions . . . . . . . . . . . . . . 71 100-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 71 Ordering Information . . . . . . . . . . . . . . . . 72 Life Support Policy . . . . . . . . . . . . . . . . . . 72 2 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Input Formats . . . . . . . . . . . . . . . . . . . . . .7 24 bit Input Format . . . . . . . . . . . . . . . . . .7 CCIR656 Input Format . . . . . . . . . . . . . . .8 10 bit Input Format . . . . . . . . . . . . . . . . . .8 20 bit 4:2:2 Input Format . . . . . . . . . . . . .8 20 bit 4:4:4 Input Format . . . . . . . . . . . . .8 Propagation Delay through the Encoder . . . . . . . . . . . . . . . . . . . . . . . . .10 Horizontal Timing . . . . . . . . . . . . . . . . . .13 Horizontal Timing – Vertical Blanking . . .13 Horizontal Timing – 1st Half-line. . . . . . .14 Horizontal Timing – 2nd Half-line . . . . . .14 NTSC Vertical Interval . . . . . . . . . . . . . .15 PAL Vertical Interval . . . . . . . . . . . . . . . .17 PAL-M Vertical Interval . . . . . . . . . . . . . .19 Burst Envelope . . . . . . . . . . . . . . . . . . . .23 Gaussian Filter Response . . . . . . . . . . .23 Interpolation Filter. . . . . . . . . . . . . . . . . .25 Interpolation Filter – Passband Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .25 X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .25 Layering Engine . . . . . . . . . . . . . . . . . . .28 Overlay Outputs . . . . . . . . . . . . . . . . . . .29 Data Keying . . . . . . . . . . . . . . . . . . . . . .29 Microprocessor Parallel Port – Write Timing . . . . . . . . . . . . . . . . . . . . . .30 Microprocessor Parallel Port – Read Timing . . . . . . . . . . . . . . . . . . . . . .30 Serial Port Read/Write Timing . . . . . . . .31 Serial Interface – Typical Byte Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .32 Serial Interface – Chip Address . . . . . . .32 Typical Analog Reconstruction Filter . . .63 Overall Response . . . . . . . . . . . . . . . . . .63 Typical Layout . . . . . . . . . . . . . . . . . . . . .65 ST-163E Layout . . . . . . . . . . . . . . . . . . .66 Pass Band . . . . . . . . . . . . . . . . . . . . . . .67 Stop Band. . . . . . . . . . . . . . . . . . . . . . . .67 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .67 Group Delay . . . . . . . . . . . . . . . . . . . . . .67 List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. CSM Coefficient Range . . . . . . . . . . . . . 9 Expected Output Values for the CSM with YCBCR Inputs . . . . . . . . . . . . 9 PDC Edge Control . . . . . . . . . . . . . . . . 11 Horizontal Line Equations. . . . . . . . . . . 12 Horizontal Timing Specifications. . . . . . 13 Vertical Interval Timing Specifications . . . . . . . . . . . . . . . . . . . . 14 Default Horizontal Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 15 NTSC Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 16 PAL Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 18 PAL-M Field/Line Sequence and Identification . . . . . . . . . . . . . . . . . . . . . 20 Standard Subcarrier Parameters . . . . . 22 Line by Line Pedestal Enable . . . . . . . . 23 Closed Caption Line Selection . . . . . . . 24 D/A Outputs . . . . . . . . . . . . . . . . . . . . . 25 Ancillary Data Format . . . . . . . . . . . . . . 26 Ancillary Data Control – Phase . . . . . . 27 Ancillary Data Control Frequency. . . . . 27 Field Identification and Subcarrier Reset Modes . . . . . . . . . . . . . . . . . . . . 27 Layering and Keying Modes . . . . . . . . . 28 Overlay Address Map . . . . . . . . . . . . . . 29 Parallel Port Control . . . . . . . . . . . . . . . 30 Serial Port Addresses. . . . . . . . . . . . . . 31 Control Register Map . . . . . . . . . . . . . . 33 REV. 1.0.0 8/13/03 3 TMC2192 PRODUCT SPECIFICATION Pin Assignments 100 1 81 80 Pin 1 2 3 4 5 6 7 8 9 10 11 12 30 31 50 51 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VDDA COMP CBYPCOMP Pin 31 32 33 34 Function PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 VDD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function PD1 PD0 DGND VDD VSIN HSIN DCVEN SER CS\/SCL R/W\/SDA A1/SA1 A0/SA0 D7 D6 D5 D4 D3 D2 D1 D0 DGND VDD PDC HSOUT VSOUT LINE4 LINE3 LINE2 LINE1 LINE0 Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function FLD2 FLD1 FLD0 CVBS9 CVBS8 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 RESET PXCK VDD DGND VREF RREFCOMP AGND AGND CHROMA 35 CBYPCHROM 36 VDDA 37 RREFCHROM 38 AGND 39 LUMA 40 CBYPLUMA 41 VDDA RREFLUMA AGND AGND VDDA VDDA AGND AGND KEY OL4 OL3 OL2 OL1 OL0 DGND PD23 PD22 PD21 PD20 42 43 44 45 46 47 48 49 50 65-6294-14 Pin Definitions Pin Name DCVEN Pin Number 57 Value TTL Description Digital CVBS Output Enable. When DCVEN is LOW, the Comp2 output prior to the D/A is routed to D7-0, FLD2-1 providing a digital composite output. When DCVEN is HIGH, D7-0 and FLD2-1 operate in their normal mode. Horizontal Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new horizontal line with each falling edge of HSIN. Hard Key selection. When the control register bit HKEN is set HIGH and the hardware KEY pin is high, the video data considered to be the foreground. is routed to the COMP2 output. This control signal is data aligned so that the pixel that is present on the PD port when KEY signal is latched is at the midpoint of the key transition. When HKEN is LOW, Key is ignored. CLOCK, SYNC, & CONTROL INPUTS (6 pins) HSIN 56 TTL KEY 20 TTL 4 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Pin Definitions (continued) Pin Name PXCK Pin Number 95 Value TTL Description Pixel Clock Input. PXCK is a clock signal that period is twice the sample rate of the pixel data. The operating range is 20 to 30 MHz. The clock is internally divided by 2 to generate the internal pixel clock, PCK. PXCK drives the entire TMC2192 except the asynchronous microprocessor interface. Master Chip Reset. When LOW, All outputs are tri-stated and the internal state machines and control registers are reset. At rising edge of RESET, all outputs are active, the preset values will be loaded into the control registers and the internal states machines start to operate. Vertical Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new vertical field with each falling edge of VSIN that is coincident with HSIN. Field Identifier. Field Identifier outputs the current field number. For all video standards the field identifier will cycle through the eight counts. Horizontal Sync Output. The alignment of HSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Vertical Blanking Interval Line Identifier. LINE identifies the current line number for the first 31 lines. If the line count is greater than 31 then LINE is 11111b. The first line with a vertical serration is considered to be line 0. Pixel Data Control. When PDCDIR = LOW: At a rising edge, The next pixel starts a controlled ramp of the PD data. At a falling edge, the pixel prior is the last PD used in the ramp. The rising edge is determined by the PDCCNT control register, the falling edge of PDC is determined by the horizontal timing registers. When PDCDIR = HIGH: PDCIN is used to override the internal PDC. When HIGH, the internal PDC controls the blank and unblank window. When LOW, the video remains blanked regardless of the internal PDC. All edges have the same ramp control as the internal PDC. VSOUT 75 TTL Vertical Sync Output. The alignment of VSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Composite Data Input Overlay Control Component Data Input Luma Chroma Composite D/A with optional keying RESET 94 TTL VSIN 55 TTL SYNC & CONTROL OUTPUTS (11 pins) FLD[2:0] 81–83 TTL HSOUT 74 TTL LINE[4:0] 76–80 TTL PDC 73 TTL DATA INPUTS (39 pins) CVBS[9:0] OL[4:0] PD[23:0] LUMA CHROMA COMP 84–93 21–25 27–38, 41–52 10 5 2 TTL TTL TTL 1.35Vp-p 1.35Vp-p 1.35Vp-p ANALOG INTERFACE – Video Out (5 pins) REV. 1.0.0 8/13/03 5 TMC2192 PRODUCT SPECIFICATION Pin Definitions (continued) Pin Name CBYPLUMA CBYPCHROM CBYPCOMP RREFLUMA Pin Number 11 6 3 13 Value 0.1 µF 0.1 µF 0.1 µF 1210 Ohm Description Reference Bypass Capacitor for LUMA DAC. Connection point for 0.1 µF Capacitor. Reference Bypass Capacitor for CHROMA DAC. Connection point for 0.1 µF Capacitor. Reference Bypass Capacitor for COMPOSITE DAC. Connection point for 0.1 µF Capacitor. Current Setting Resistor. Connection point for external current setting resistor for LUMA DAC. The resistor is connected between RREFLUMA and GND. Output video levels are inversely proportional to the value of RREF2. Current Setting Resistor. Connection point for external current setting resistor for CHROMA DAC. The resistor is connected between RREFCHROM and GND. Output video levels are inversely proportional to the value of RREFCHROM. Current Setting Resistor. Connection point for external current setting resistor for COMPOSITE DAC. The resistor is connected between RREFCOMP and GND. Output video levels are inversely proportional to the value of RREFCOMP. Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235V. When SER (HIGH), OLUT/control/pointer address. When SER (LOW), SA[1:0] of serial chip address SA[6:0]. ANALOG INTERFACE – Support (9 pins) RREFCHROM 8 1210 Ohm RREFCOMP 99 1210 Ohm VREF 98 1.235 V MPU INTERFACE (13 pins) A[1:0]/SA[1:0] CS/SCL D[7:0] RW/SDA SER 61, 62 59 63–70 60 58 TTL TTL/R-BUS When SER (HIGH), microprocessor port clock. When SER (LOW), serial bus clock. TTL Bi-directional Data Bus. TTL/R-BUS When SER (HIGH), read/write control. When SER (LOW), serial bus bi-directional data. TTL Microprocessor Select. When LOW, the serial interface is enabled. When HIGH, the parallel interface is enabled. Analog ground Digital ground Digital positive power supply Analog positive power supply POWER & GROUND (17 pins) AGND DGND VDD VDDA 4, 9, 14, 15, 18, 19, 100 26, 40, 53, 71, 97 39, 54, 72, 96 1, 7, 12, 16, 17 0.0V 0.0V +5.0V +5.0V 6 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Functional Description Input Formats Control Registers for this section Address 0x05 0x05 0x06 Bit(s) 7 6-4 0 Name D1OFF INMODE TSOUT Demuxing of multiplexed data streams depends on which synchronization mode the encoder is operating in. For slave and genlock modes the falling edge of HSIN must be LOW prior to the CB data in order to demux the data correctly. For master mode synchronization the falling edge of HSOUT must be LOW prior to the Y data in order to demux the data correctly. Finally, in 656 mode the demuxing of the data stream is determined by the TRS codes, the first sample after the TRS is considered a CB sample of the CB Y CR YI packet. The control register D1OFF controls the formatting of the incoming luminance data at the pixel data port. When D1OFF is HIGH a blanking level of 6410 is subtracted from the luminance and when D1OFF is LOW the incoming the pixel data is passed through. The inversion of the MSB’s on the CB and CR components is controlled by the INMODE control register. The TMC2192 supports YCBCR component sources on the pixel data port. YCBCR input sources are supported in 10 bit 4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2 cases the color difference components are linearly interpolated to 4:4:4 internally. INMODE 00 01 1x 23 7 9 9 CB YC BC R YC BC R 16 0 15 7 0 0 PD CR 9 8 0 7 7 Y 0 0 1 0 9 Y 2 2192002A Figure 1. Input Formats 1. INMODE = 00, PD[7:0] = PD[23:16] = CB, PD[15:8] = CR n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2 PXCK tS tH PD[7:0] Yn-1 Yn Y0 Yx Yx+1 Yx+2 PD[23:16] CBn-1 CBn CB0 C Bx CBx+1 CBx+2 PD[15:8] CRn-1 CRn tSP CR0 CRx CRx+1 CRx+2 HSIN tDO tDO HSOUT (TSOUT = 1) 2192003A Figure 2. 24 Bit Input Format 2. INMODE = 01, PD[23:14] = YCBCR running at 27MHz. data value, after the SAV preamble, is treated as a CB data point in the multiplexed CB, Y, CR Y , D1 data stream. Note: Figure 3, pixel numbering, reflects the SMPTE-125M pixel numbering. The PD port is clocked at twice the pixel rate, with the data organized as CB Y CR Y, with the cosited Y's following the CB's. In its CCIR-656 time base mode, the demuxed CB, Y, and CR data is synchronized to the SAV preamble. The first REV. 1.0.0 8/13/03 7 TMC2192 PRODUCT SPECIFICATION 0 128 (SY+BR+BU+CBP)*2 PXCK tS tH PD[23:14] CB718 Y718 CR718 Y719 FF 00 EAV 00 FV1 CB736 Y736 tDO tHS tDO FF 00 SAV 00 FV0 CB0 Y0 CR0 Y1 CB2 Y2 HSOUT (TSOUT = 1) 65-6294-04 Figure 3. CCIR656 Input Format n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2 PXCK tS tH PD[23:14] CBn Yn CRn Yn+1 tSP CB0 Y0 tHP CBx Yx CRx Yx+1 CBx+2 Yx+2 HSIN tDO tDO HSOUT (TSOUT = 1) 65-6294-05 Figure 4. 10 bit Input Format 3. INMODE = 11, PD[9:0] = Y, PD[23:14] = CB/CR n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2 PXCK tS tH PD[9:0] Yn Yn+1 Y0 Y1 Yx Yx+1 Yx+2 PD[23:14] CBn CRn tSP CB0 CR0 CBx CRx CBx+2 HSIN tDO tHS 65-6294-06 tDO HSOUT (TSOUT = 1) Figure 5. 20 bit 4:2:2 Input Format 4. INMODE = 10, PD[9:0] = Y at PCK, PD[23:14] = CB-CR at PXCK n = (SY+BR+BU+CBP+AV)*2 0 128 x = (SY+BR+BU+CBP)*2 PXCK tS tH PD[9:0] Yn Yn+1 Y0 tS Yx tH PD[23:14] CBn CRn CBn+1 CRn+1 tSP CB0 CR0 CBx C Rx HSIN tDO tDO HSOUT (TSOUT = 1) 65-6294-07 Figure 6. 20 bit 4:4:4 Input Format 8 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Color Space Matrix Control Registers for this section Address 0x30 0x33 0x35 0x3A 0x3B 0x3C Bit(s) 7-0 7-0 7-0 7-4 2-0 2-0 Name MCF1L MCF2L MCF3L MCF1M MCF2M MCF3M Matrix configuration: Ycomposite = MCF1 * Yin U = MCF2 * CB V = MCF3 * CR The color space matrix consists of 3 multipliers with independently adjustable coefficients, and a resolution of 0.00049 (1/2048). The amount of gain varies among coefficients, Table 1 summarizes the gain for each coefficient. Table 1. CSM Coefficient Range Coefficient MCF1 MCF2 MCF3 Gain Range 0 to 2 0 to 1 0 to 1 11 bit coefficient. 11 bit coefficient. processing block and prior to the sync and pedestal insertion. The blank, pedestal, and sync values are given as a reference. Table 4 gives the default coefficients values for the CSM. Comment To aid in the programming of the color space matrix Table 2 provides a set of default input and output values for 100% color bars. The component values given will be after the pre- Table 2. Expected Output Values for the CSM with YCBCR Inputs Inputs Color White Yellow Cyan Green Magenta Red Blue Black Blank Pedestal Sync Y 876 776 614 514 362 262 100 0 64 CB 0 -448 151 -297 297 -151 448 0 CR 0 73 448 -375 375 448 -73 0 Y 536 475 376 315 222 160 61 0 240 44 8 5:2 Outputs U 0 -235 79 -156 156 -79 235 0 V 0 54 -332 -278 278 332 -54 0 Y 568 503 407 340 240 173 66 0 256 0 12 7:3 Outputs U 0 -249 84 -165 165 -84 249 0 V 0 57 -351 -294 294 351 -57 0 REV. 1.0.0 8/13/03 9 TMC2192 PRODUCT SPECIFICATION Synchronization Modes Control Registers for this section Address 0x06 0x06 0x06 Bit(s) 5-3 1 0 Name MODE TOUT TSOUT CCIR656 The TMC2192 derives all synchronization from the embedded TRS (timing reference signals) information. Blanking of selected lines is determined by the v bit of the TRS. However the control registers VBIENx can override and blank the active video portion of VBI lines regardless of the state of the v-bit. Genlock The TMC2192 offers a variety of synchronization modes; these are master, slave, genlock, 656 mode, and DRS-Lock. In master mode, the TMC2192 generates its own timing and the synchronization is supplied externally by HSOUT and VSOUT signals. In slave and genlock modes the TMC2192 derives its timing from the input pins HSIN, VSIN. In 656 mode the timing is driven by the synchronization codes embedded into the data stream. Master The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. The TMC2192 collects GRS data and resets its subcarrier phase and frequency to the data embedded in the GRS stream. The GRS detection occurs only on the CBVS port. DRS The TMC2192 drives the output pins HSOUT and VSOUT to synchronize the incoming video. A new color frame starts at the rising edge of RESET. The encoder always starts at the 1st vertical serration in field 8 and will freerun the field and line sequence. The control register bit SRESET can be used to synchronize the start of the field and line sequence in master mode by resetting the FVHGEN state machine. Output synchronization signal VSOUT can operate in a traditional sync mode or in a MPEG style field toggle mode. Slave The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. Subcarrier phase adjustment is determined by the DRS data. The DRS detection can occur on either the CBVS port or the pixel data port. The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. Propagation Delay The propagation delay from the pixel data (PD) input to the D/A output is 64 PXCK’s. Figure 8 shows the propagation delay for both master and slave synchronization modes. For CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the midpoint of sync and is 32 PXCK’s (24 PXCK’s in PAL) after the EAV TRS. n = (SY+BR+BU+CBP+AV)*2 0 63 65 128 PXCK PD[23:14] CBn Yn CRn Yn+1 CB0 Y0 HSIN tDO HSOUT (TSOUT = 1) DACx (ANALOG) DCVBS (D[7:0],FLD[2:1]) tDO COMP0 COMP1 65-6294-09 Midpoint of the Falling Edge of Sync Figure 7. Propagation Delay through the Encoder 10 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Blanking Control Control Registers for this section Address 0x04 0x06 0x18 0x19 0x1F Bit(s) 1-0 2 4-0 4-0 7-0 Name PDRM PDCDIR VBIENF1 VBIENF2 PDCCNT Pixel Data Control The pixel data control has two modes of operation, as an input or as an output. The mode of operation is determined by the PDCDIR control register. When PDC is an input the internally generated PDC is ANDed with the PDC pin. This allows the user to blank any active video regions. When PDC is an output, the internally generated PDC is the output for the PDC pin. The internal PDC control will toggle to a logic HIGH at the pixel specified by PDCNT and toggle to a logic LOW four pixels prior to the end of the active video region. The starting point and ending point of the active video region (VA) are determined by the control registers 10h to 1Fh. When PDC is used as an input, the sloped edge of the active video region will occur on the next four pixels following the toggle point. The content of VBIENFx[4:0] selects the first line to contain an active video region in each field, all subsequent lines for the remainder of the field are active. To blank an entire field, the user zeroes the VBIENFx[4:0] control register. In CCIR656 slave mode, the user can selectively blank any enabled line by setting its TRS V bit HIGH. For 525-line systems, NTSC line numbering is employed, with the first vertical serration starting on line 4. PAL line numbering is used with 625-line systems, with each field's line 1 being the start of the first vertical serration. Any line(s) enabled by the closed caption control are automatically unblanked for the closed caption waveform, irrespective of the corresponding values of VBIENF. Table 3. PDC Edge Control PDRM[1:0] 00 Slope type at PDC (HIGH) Edge Shaping The TMC2192 has three modes of sloped edges on the active video region and are controlled by PDRM control register. Slope type at PDC (LOW) The following four pixels have the weighting of 1, 7/8, 1/2, and 1/8 for NTSC and 7/8, 5/8, 3/8, and 1/8 for PAL. The fifth pixel s sampled and scaled 1, 7/8, 1/2 and 1/8 over the next four pixels for NTSC and 7/8, 5/8, 3/8, and 1/8 over the next four pixels for PAL. Slope is off, edge control is dictated by the PD stream to active video end The following four pixels have the weighting of 1/8, 1/2, 7/8 and 1 for NTSC and 1/8, 3/8, 5/8, and 7/8 for PAL. The fifth pixel is sampled and scaled 1/8, 1/2, 7/8 and 1 over the next four pixels for NTSC and 1/8, 3/8, 5/8, and 7/8 over the next four pixels for PAL. Slope is off, edge control is dictated by the PD stream from active video start 01 1x REV. 1.0.0 8/13/03 11 TMC2192 PRODUCT SPECIFICATION Horizontal Programming Control registers for this section Address 0x06 0x19 0x19 0x19 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2D 0x2D 0x2D Bit(s) 7-6 7 6 5 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-6 5-4 3-2 1-0 FORMAT SHORT T512 HALFEN SY BR BU CBP XBP VA VC VB EL EH SL SH FP XBP (MSB’s) VA (MSB’s) VB (MSB’s) VC (MSB’s) Name Horizontal interval timing is fully programmable and is established by loading the timing registers with the duration of each horizontal element. The duration is expressed in PCK clock cycles. In this way, any pixel clock rate between 10 MHz and 15 MHz can be accommodated, and any desired standard or non-standard horizontal video timing may be produced. Horizontal timing parameters can be calculated as follows: t = N x ( PCK period ) = N x ( 2 x PXCK period ) where N is the value loaded into the appropriate timing register, and PCK is the pixel clock period. When programming horizontal timing, subtract 5 PCK periods from the calculated values of CBP and add 5 PCK periods to the calculated value for VA. The control register HALFEN enables the 1st half line (UBV) on line 283 for NTSC, PAL-M and line 23 for all other PAL standards when it is LOW. Table 4. Horizontal Line Equations Line Type EE SE SS ES EB UBB, -BB UVV, -VV UVE, -VE UBV Line ID 00 02 03 01 10 0D, 05 0F, 07 0C, 04 0E Line Length Equals EL + EH + EL + EH SL + SH + EL + EH SL + SH + SL + SH EL + EH + SL + SH EL + EH + EL + EH SY + BR + BU + CBP + VA + FP SY + BR + BU + CBP + VA + FP SY + BR + BU + CBP + VC + FP + EL + EH SY + BR + BU + XBP + VB + FP 12 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 SY BR BU CBP VA FP 65-6294-10 Figure 8. Horizontal Timing Table 5. Horizontal Timing Specifications Parameter FP SY BR BU CBP VA H NTSC-M (µs) 1.5 4.7 0.6 2.5 1.6 52.6556 63.5556 PAL-I (µs) 1.65 4.7 0.9 2.25 2.55 51.95 64.0 PAL-M (µs) 1.9 4.95 0.9 2.25 1.8 51.692 63.492 ming, any pixel rate between 10 and 15 Mpps can be accommodated, and any desired standard or non-standard vertical video timing may be produced. Like horizontal timing parameters, vertical timing parameters are calculated as follows: t = N x ( PCK period ) = N x ( 2 x PXCK period ) where N is the value loaded into the appropriate timing register, and PCK is the pixel clock period. The vertical interval comprises several different line types based upon H, the Horizontal line time. H = (2 x SL) + (2 x SH) [Vertical sync pulses] = (2 x EL) + (2 x EH) [Equalization pulses] Vertical interval timing is also fully programmable, and is established by loading the timing registers with the duration’s of each vertical timing element, the duration expressed in PCK clock cycles. In this way as with horizontal program- H H/2 EL EH SL SH 65-6294-11 Figure 9. Horizontal Timing – Vertical Blanking The VB and VC control registers are added to produce the half-lines needed in the vertical interval at the beginning and end of some fields. These must properly mate with components of the normal lines. REV. 1.0.0 8/13/03 13 TMC2192 PRODUCT SPECIFICATION H/2 SY BR BU XBP VB FP 65-6924-12 Figure 10. Horizontal Timing – 1st Half-line H/2 SY BR BU CBP VC FP EL EH 65-6294-13 Figure 11. Horizontal Timing – 2nd Half-line Table 6. Vertical Interval Timing Specifications Parameter H EH EL SH SL NTSC-M (µs) 63.5556 29.4778 2.3 4.7 27.1 PAL-I (µs) 64 29.65 2.35 4.7 27.3 PAL-M (µs) 63.492 29.45 2.3 4.65 27.1 14 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Table 7. Default Horizontal Timing Parameters Timing Register (hex) Field Rate (Hz) 59.94 59.94 59.94 50.00 50.00 50.00 60.00 60.00 60.00 Horizontal Freq. (KHz) 15.734266 15.734266 15.734266 15.625000 15.625000 15.625000 15.750000 15,750000 15,750000 Pixel Rate (Mpps) 12.27 13.50 14.32 14.75 13.50 15.00 12.50 13.50 14.30 PXCK Freq. (MHz) 24.54 27.00 28.64 29.50 27.00 30.00 25.01 27.00 28.60 SY 20 3A 40 43 45 40 46 3E 44 47 BR 21 07 08 09 0D 0C 0D 0B 0C 0D BU 22 1F 22 24 21 1E 22 1C 1E 20 CBP XBP 23 0F 11 12 21 22 21 13 13 15 24 23 44 54 6D 4D 73 26 26 4C VA 25 8B CB F7 03 BE 11 86 Bf E8 VC 26 05 1E 30 2B 0E 31 FE 12 22 VB 27 77 98 B5 B7 93 BF 8B 99 AC EL 28 1C 1F 21 23 20 23 1D 1F 21 EH2 29 6A 8E A6 B5 90 BD 70 8E A5 SL2 2A 4C 6D 84 93 70 9A 53 6E 84 SH 2B 3A 40 43 45 40 47 3A 3F 42 FP 2C 12 14 15 19 16 19 18 1A 1B Note CBL 2D 65 65 65 75 65 75 61 65 65 2F 52 59 5F 61 59 62 52 57 5D Standard NTSC sqr. pixel NTSC CCIR-601 NTSC 4x FSC PAL sqr. pixel PAL CCIR-601 PAL 15 Mpps PAL-M sqr.pixel PAL-M CCIR-601 PAL-M 4x FSC Notes: 1. XBP, VA, VC, and VB are 10 bit values. The 2 MSBs for these four variables are in Timing Register 2D. 2. EH and SL are 9 bit values. A most significant "1" is forced by the TMC2192 since EH and SL must range from 256 to 511. EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 29 and 2A. 3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256. Vertical Timing The vertical timing is controlled by the FORMAT control register, which dictates the field and line sequence. 524 525 1 2 3 FIELDS 1 AND 3 4 5 6 7 8 9 10 ••• 19 20 21 22 UVV HSOUT UVV EE EE EE SS SS SS EE EE EE UBB UBB UBB UVV UVV VSOUT (TOUT = 1) VSOUT (TOUT = 0) 262 263 264 265 FIELDS 2 AND 4 266 267 268 269 270 271 272 273 ••• 282 283 284 285 UVV HSOUT UVE EE EE ES SS SS SE EE EE EB UBB UBB UBV UVV UVV VSOUT (TOUT = 1) VSOUT (TOUT = 0) 65-6294-15 Figure 12. NTSC Vertical Interval REV. 1.0.0 8/13/03 15 TMC2192 PRODUCT SPECIFICATION Table 8. NTSC Field/Line Sequence and Identification Field 1 FIELD ID = x00 Line 4 5 6 7 8 9 10 … 19 20 21 22 … 262 263 264 265 ID SS SS SS EE EE EE UBB UBB UBB UBB UVV UVV UVV UVV UVE EE EE LTYPE 03 03 03 00 00 00 0D 0D 0D 0D 0F 0F 0F 0F 0C 00 00 Field 2 FIELD ID = x01 Line 266 267 268 269 270 271 272 273 … 282 283 284 … 524 525 1 2 3 EE SE SS ES EB UBB UVV UVE UBV Field 3 FIELD ID = x10 Line 4 5 6 7 8 9 10 … 19 20 21 22 … 262 263 264 265 ID SS SS SS EE EE EE UBB UBB UBB UBB UVV UVV UVV UVV UVE EE EE LTYPE 03 03 03 00 00 00 0D 0D 0D 0D 0F 0F 0F 0F 0C 00 00 01 03 03 02 00 00 10 0D 0D 0D 0E 0F 0F 0F 0F 00 00 00 Field 4 FIELD ID = x11 Line 266 267 268 269 270 271 272 273 … 282 283 284 … 524 525 1 2 3 ID ES SS SS SE EE EE EB UBB UBB UBB UBV UVV UVV UVV UVV EE EE EE LTYPE 01 03 03 02 00 00 10 0D 0D 0D 0E 0F 0F 0F. 0F 00 00 00 ID ES SS SS SE EE EE EB UBB UBB UBB UBV UVV UVV UVV UVV EE EE EE LTYPE Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Active video Half-line video, half-line equalization pulse half-line black, half-line video 16 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 622 623 FIELDS 1 AND 5 ••• 23 24 25 26 624 625 1 2 3 4 5 6 7 22 UVV HSOUT VSOUT (TOUT = 1) -VE EE EE SS SS SE EE EE -BB UBB ••• UBB UBV UVV UVV UVV VSOUT (TOUT = 0) 309 310 FIELDS 2 AND 6 311 312 313 314 315 316 317 318 319 320 ••• 334 335 336 337 UVV HSOUT VSOUT (TOUT = 1) -VV EE EE ES SS SS EE EE EB UBB UBB ••• UBB UBB UVV UVV VSOUT (TOUT = 0) 622 623 FIELDS 3 AND 7 ••• 23 24 25 26 624 625 1 2 3 4 5 6 7 22 -VV HSOUT VSOUT (TOUT = 1) -VE EE EE SS SS SE EE EE UBB UBB ••• UBB UBV UVV UVV UVV VSOUT (TOUT = 0) 309 310 FIELDS 4 AND 8 311 312 313 314 315 316 317 318 319 320 ••• 334 335 336 337 UVV HSOUT VSOUT (TOUT = 1) UVV EE EE ES SS SS EE EE EB -BB UBB ••• UBB UBB UVV UVV VSOUT (TOUT = 0) 65-6294-16 Figure 13. PAL Vertical Interval REV. 1.0.0 8/13/03 17 TMC2192 PRODUCT SPECIFICATION Table 9. PAL Field/Line Sequence and Identification Field 1 & 5 FIELD ID = 000, 100 Line 1 2 3 4 5 6 7 … 22 23 24 25 26 … 309 310 311 312 EE SE SS ES EB UBB -BB UVV -VV UVE -VE UBV Field 2 & 6 FIELD ID = 001, 111 Line 313 314 315 316 317 318 319 320 … 334 335 336 337 … 622 623 624 625 ID ES SS SS EE EE EB UBB UBB UBB UBB UBB UVV UVV UVV -VV -VE EE EE LTYPE 01 03 03 00 00 10 0D 0D 0D 0D 0D 0F 0F 0F 07 04 00 00 Field 3 & 7 FIELD ID = 010, 110 Line 1 2 3 4 5 6 7 … 22 23 24 25 26 … 309 310 311 312 ID SS SS SE EE EE UBB UBB UBB UBB UBV UVV UVV UVV UVV UVV UVV EE EE LTYPE 03 03 02 00 00 0D 0D 0D 0D 0E 0F 0F 0F 0F 0F 0F 00 00 Field 4 & 8 FIELD ID = 011, 111 Line 313 314 315 316 317 318 319 320 … 334 335 336 337 … 622 623 624 625 ID ES SS SS EE EE EB -BB UBB UBB UBB UVV UVV UVV UVV UVV -VE EE EE LTYPE 01 03 03 00 00 10 05 0D 0D 0D 0F. 0F 0F 0F 0F 04 00 00 ID SS SS SE EE EE -BB UBB UBB UBB UBV UVV UVV UVV UVV UVV -VV EE EE LTYPE 03 03 02 00 00 05 0D 0D 0D 0E 0F 0F 0F 0F 0F 07 00 00 Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Black burst with color burst suppressed Active video Active video with color burst suppressed Half-line video, half-line equalization pulse Half-line video, half-line equalization pulse, color burst suppressed. half-line black, half-line video 18 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 521 522 523 524 525 FIELDS 1 AND 5 1 2 3 4 5 6 7 8 9 ••• 17 18 UVV UVV EE EE EE SS SS SS EE EE EE -BB -BB UBB ••• UBB UVV HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) 259 260 261 262 FIELDS 2 AND 6 263 264 265 266 267 268 269 270 271 ••• 279 280 281 UVV -VE EE EE ES SS SS SE EE EE EB -BB UBB ••• UBB UBV UVV HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) 521 522 523 524 525 FIELDS 3 AND 7 1 2 3 4 5 6 7 8 9 ••• 17 18 UVV -VV EE EE EE SS SS SS EE EE EE -BB UBB UBB ••• UBB UVV HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) 258 259 260 261 262 FIELDS 4 AND 8 263 264 265 266 267 268 269 270 271 ••• 279 280 281 UVV -VV -VE EE EE ES SS SS SE EE EE EB UBB UBB ••• UBB UBV UVV HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) 65-6294-17 Figure 14. PAL-M Vertical Interval REV. 1.0.0 8/13/03 19 TMC2192 PRODUCT SPECIFICATION Table 10. PAL-M Field/Line Sequence and Identification Field 1 & 5 FIELD ID = 000, 100 Line 1 2 3 4 5 6 7 8 9 … 17 18 … 259 260 261 262 ID SS SS SS EE EE EE -BB -BB UBB … UBB UVV … UVV -VE EE EE LTYPE 03 03 03 00 00 00 05 05 0D … 0D 0F … 0F 04 00 00 Field 2 & 6 FIELD ID = 001, 111 Line 263 264 265 266 267 268 269 270 271 … 279 280 281 … 521 522 523 524 525 EE SE SS ES EB UBB -BB UVV -VV UVE -VE UBV Field 3 & 7 FIELD ID = 010, 110 Line 1 2 3 4 5 6 7 8 9 … 17 18 … 258 259 260 261 262 ID SS SS SS EE EE EE -BB UBB UBB … UBB UVV UVV UVV -VV -VE EE EE LTYPE 03 03 03 00 00 00 05 05 0D … 0D 0F 0F 0F 07 04 00 00 Field 4 & 8 FIELD ID = 011, 111 Line 263 264 265 266 267 268 269 270 271 … 279 280 281 … 521 522 523 524 525 ID ES SS SS SE EE EE EB UBB UBB … UBB UBV UVV … UVV UVV EE EE EE LTYPE 01 03 03 02 00 00 10 05 1D … 0D 0E. 0F … 0F 0F 00 00 00 ID ES SS SS SE EE EE EB -BB UBB … UBB UBV UVV … UVV -VV EE EE EE LTYPE 01 03 03 02 00 00 10 05 1D … 0D 0E. 0F … 0F 07 00. 00 00 Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Black burst Black burst with color burst suppressed Active video Active video with color burst suppressed Half-line video, half-line equalization pulse Half-line video, half-line equalization pulse, color burst suppressed. half-line black, half-line video 20 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Chrominance Processor Control registers for this section: Address 0x06 0x06 0x07 0x11 0x18 0x18 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A Bit(s) 7-6 5-3 5 7 6 5 3 7-0 7-0 7-0 7-0 7-4 3-0 7-4 3-0 7-4 3-0 7-4 Name FORMAT MODE DDSRST DRSSEL GLKCTL1 GLKCTL0 GAUSS_BYP FREQL FREQ3 FREQ2 FREQM SYSPHL SYSPHM BURPHL BURPHM BRSTFULL BRST1 BRST2 NTSC Subcarrier For NTSC encoding, the subcarrier synthesizer frequency has a simple relationship to the pixel clock period, repeating over 2 lines: The decimal value for the subcarrier phase step is: 455 ⁄ 2 32 FREQx = -------------------------- × 2 pixels ⁄ line Where the number of pixels/line is: PXCK Frequency pixels ⁄ line = -----------------------------------------H Period This value must be converted to binary and split into four 8 bit registers, FREQM, FREQ2, FREQ3, and FREQL. PAL Subcarrier The PAL relationship is more complex, repeating only once in 8 fields (the well-known 25 Hz offset): ( 1135 ⁄ 4 ) + ( 1 ⁄ 625 ) 32 FREQx = -------------------------------------------------- × 2 pixels ⁄ line This value must be converted to binary and split as described previously for NTSC. The number of pixels/line is found as in NTSC. PAL-M Subcarrier Subcarrier Programming 909 ⁄ 4 32 FREQ = -------------------------- × 2 pixels ⁄ line SYSPHx establishes the appropriate phase relationship between the internal synthesizer and the chroma modulator. The nominal value for SYSPHx is zero. Other values for SYSPHx must be converted to binary and split into two 8 bit registers, SYSPHM and SYSPHL. Burst Phase (BURPHx) sets up the correct relative NTSC modulation angle. The value for BURPH is: BURPHx = SYSPHx This value must be converted to binary and split into two 8 bit registers, BURPHM and BURPHL. The color subcarrier is produced by an internal 32 bit digital frequency synthesizer which is completely programmable in frequency and phase. Separate registers, FREQx, SYSPHx, BSTPHx, are provided for phase adjustment of the color burst and of the active video, permitting external delay compensation, color adjustment, etc. FREQx is the subcarrier phase step per pixel and SYSPHx is phase offset at field 1, line 1 (line 4 for NTSC), pixel 1. REV. 1.0.0 8/13/03 21 TMC2192 PRODUCT SPECIFICATION Table 11. Standard Subcarrier Parameters Subcarrier Register (hex) Field Rate (Hz) 59.94 59.94 59.94 50.00 50.00 50.00 60.00 60.00 60.00 Horizontal Freq. (kHz) 15.734266 15.734266 15.734266 15.625000 15.625000 15.625000 15.750000 15,750000 15,750000 Pixel Rate (Mpps) 12.27 13.50 14.32 14.75 13.50 15.00 12.50 13.50 14.30 PXCK Freq. (MHz) 24.54 27.00 28.64 29.50 27.00 30.00 25.01 27.00 28.60 Subcarrier Freq. (MHz) 3.57954500 3.57954500 3.57954500 4.43361875 4.43361875 4.43361875 3.57561149 3.57561149 3.57561149 BURPHM BURPHL SYSPHM 47 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 45 00 00 00 00 00 00 00 00 00 SYSPHL FREQM 44 00 00 00 00 00 00 00 00 00 43 4A 43 40 4C 54 4B 49 43 40 FREQ2 FREQ3 FREQL 42 AA E0 00 F3 13 AA 45 DF 10 41 AA F8 00 18 15 C6 00 3F 66 40 AB 3E 00 19 96 A1 51 D7 F5 Standard NTSC sqr. pixel NTSC CCIR-601 NTSC 4x FSC PAL sqr. pixel PAL CCIR-601 PAL 15 Mpps PAL-M sqr.pixel PAL-M CCIR-601 PAL-M 4x FSC Subcarrier Synchronization There are 5 modes of subcarrier synchronization in the TMC2192, freerun, subcarrier reset, Genlock, DRS-lock and Ancillary Data Control (ANC). • Freerun At the rising edge of RESET the DDS starts to generate the subcarrier reference and will continue to freerun the subcarrier. When setting the control register DDSRST is HIGH, the TMC2192 will reset the DDS to the SYSPH value on the next field 1, line 1 (line 4 for NTSC), pixel 1 occurrence and will reset this bit to be LOW. This allows the encoder to start with the correct SCH relationship. The phase of the subcarrier reference will drift over time since a 32 bit accumulator has a error of ±0.5 Hz when generating the subcarrier reference for NTSC 13.5 MHz. • Subcarrier Reset the TMC22x5y. The TMC22x5y produces a decoder reference signal (DRS) which contains field identification, PALODD status, relative phase and relative frequency of the composite or S-video input. The DRS is sampled on either the CVBS bus or the PD port, depending on DRSSEL, 60 PXCK’s after the falling edge of HSIN. The phase and frequency values are used to update the DDS on a line to line basis, thus synchronizing the subcarrier to an external composite reference. • Ancillary Data Control (ANC) Subcarrier synchronization in ANC mode is covered in the Ancillary Data Control section of this data sheet. SCH Phase Error Correction At the rising edge of RESET the DDS starts to generate the subcarrier reference and will reset the DDS to the SYSPH value every field 1, line 1 (line 4 for NTSC), pixel 1 occurrence. This enables the encoder to maintain the proper SCH relationship. • Genlock SCH refers to the timing relationship between the 50% point of the leading edge of horizontal sync and the positive or negative zero-crossing of the color burst subcarrier reference. SCH error is usually expressed in degrees of subcarrier phase. In PAL, SCH is defined for line 1 of field 1, but since there is no color burst on line 1, SCH is usually measured at line 7 of field 1. The need to specify SCH relative to a particular line in PAL is due to the 25 Hz offset of PAL subcarrier frequency. Since NTSC has no such 25 Hz offset, SCH applies to all lines. The SCH relationship is important in the TMC2192 when two video sources are being combined or if the composite video output is externally combined with another video source. In these cases, improper SCH phasing will result in a noticeable horizontal jump of one image with respect to another and/or a change in hue proportional to the SCH error between the two sources. SCH phasing can be adjusted by modifying BURPH and SYSPH values by equal amounts. SCH is advanced/delayed by one degree by increasing/decreasing the value of BURPH and SYSPH by approximately B6h. An SCH error of 15o is corrected with SYSPH and BURPH offsets of AAAh. The Genlock mode allows the TMC2192 to lock to a composite reference when used in conjunction with the TMC22071A Genlocking Video Digitizer. The TMC22071A produces a genlock reference signal (GRS) which contains field identification, PALODD status, relative phase and relative frequency of the composite reference. The GRS is sampled on the CVBS bus 60 PXCK’s after the falling edge of HSIN. The phase and frequency values are used to update the DDS on a line to line basis, thus synchronizing the subcarrier to an external composite reference. • DRS-Lock The DRS-Lock mode allows the TMC2192 to lock its composite output to the decoded composite or S-video input of 22 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Burst Envelope The TMC2192 includes the ability to adjust the burst amplitude and the shape of the burst. The Control Registers BRSTFULL, BRST1 and BRST2 hold the magnitude of the burst vector. BRSTFULL is the maximum amplitude of the burst vector. BRST1 and BRST2 determine the intermediate values of the burst vector for the burst envelope shaping. A 5 pixel burst envelope shaping occurs at the rising and falling edges of burst. At the rising edge of burst the next 5 pixels have the following weighting; BRSTFULL – BRST1, BRSTFULL – BRST2, BRSTFULL/2, BRST2, and BRST1. At the falling edge of burst the next 5 pixels have the following weighting; BRST1, BRST2, BRSTFULL/2, BRSTFULL – BRST2, and BRSTFULL – BRST1. With this flexibility the user determine the shape, amplitude and width of the burst signal. BRSTFULL BRST1 BRST2 BRSTFULL/2 BRSTFULL - BRST2 BRSTFULL - BRST1 BLANK 0 -10 Attenuation (db) -20 -30 -40 -50 65-6294-19 -60 -70 -80 0 0.1 0.2 0.3 0.4 Normalized Frequency (Pixel rate) 0.5 Figure 16. Gaussian Filter Response Sync and Pedestal Insertion Control Registers for this section Address 0x06 0x11 0x14 0x15 0x16 65-6294-18 Bit(s) 7-6 5 7-0 7-0 7-0 7-0 6-0 3 Name MODE COMP2DB VBIPEDEM VBIPEDEL VBIPEDOM VBIPENOL PEDHGT1 C2DB_OFF BU 0x17 0x1A 0x3F Figure 15. Burst Envelope Color-Difference Low-Pass Filters The chrominance portion of a composite video signal must be sufficiently bandlimited to avoid cross-color and crossluminance distortion, and to preclude exceeding the allowable bandwidth of a video channel. The color-difference low-pass filters on the TMC2192 establish chrominance bandwidths which meet the specifications outlined in CCIR Report 624-3, Table II, Item 2.6, for system I over a range of pixel rates from 12.27 Mpps to 14.75 Mpps. Equal bandwidth is established for both colordifference channels. Pedestal Enable The TMC2192 has the ability to independently select lines for pedestal insertion during the vertical blanking interval (VBI). For 525-line systems and using the NTSC line numbering convention, in which the first vertical serration is on line 4 for field 1 and line 266 for field 2, the vertical interval lines map to the control registers VBIPEDxy as shown in Table 15. Table 12. Line by Line Pedestal Enable Bit VBIPEDEL VBIPEDEM VBIPEDOL VBIPEDOM 7 17 25* 279 287* 6 16 24 278 286 5 15 23 277 285 4 14 22 276 284 3 13 21 275 283 2 12 20 274 282 1 11 19 273 281 280 0 10 18 REV. 1.0.0 8/13/03 23 TMC2192 PRODUCT SPECIFICATION Enabling the pedestal on line 25 enables it for the remainder of field 1, to line 262. Likewise, enabling the pedestal on line 288 enables it for the remainder of field 2. Pedestal Height Line Selection The line to contain CC data is selected by a combination of the CCFLD bit and the CCLINE bits. CCLINE is added to the offset shown in Table 16 to specify the line. Table 13. Closed Caption Line Selection Standard 525 625 Offset 12 274 16 328 Parity Generation PEDHGT1 determines the height of the pedestal for the luminance channel on the composite path. The range of the pedestal height is from -22.1 to 21.74 IRE in .345 IRE increments. Sync and Blank Insertion Field ODD EVEN ODD EVEN Lines 12-27 274-289 16-31 328-343 The composite paths blank and sync D/A codes are determined by the FORMAT control register. For NTSC and PAL-M formats the blank D/A code is 240 (295 mV) and the sync D/A code is 8 (9 mV). For all other PAL formats the blank D/A code is 256 (314 mV) and the sync D/A code is 12 (14 mV). In all cases the sync edges are sloped to insure the proper rise and fall times in all video standards. Closed Caption Insertion Control Registers for this section Standard Closed-Caption signals employ ODD parity, which may be automatically generated by setting CCPAR HIGH. Alternatively, parity may be generated externally as part of the bytes to be transmitted, and, with CCPAR LOW, the entire 16 bits loaded into the CCDx registers will be sent unchanged. Operating Sequence Address 0x1C 0x1D 0x1E 0x1E 0x1E 0x1E 0x1E Bit(s) 7-6 1-0 7 6 5 4 3–0 Name CCD1 CCD2 CCON CCRTS CCPAR CCFLD CCLINE A typical operational sequence for closed-caption insertion on line xx is: Read Register 1E and check that bit 7 is LOW, indicating that the CCDx registers are ready to accept data. If ready, write two bytes of CC data into registers 1C and 1D. Write into register 1E the proper combination of CCFLD and CCLINE. CCPAR may be written as desired. Set CCRTS HIGH. The CC data is transmitted during the specified line. The TMC2192 includes a flexible closed-caption processor. It may be programmed to insert a closed caption signal on any line within a range of 16 lines on ODD and/or EVEN fields. Closed Caption insertion overrides all other configurations of the encoder: if it is specified on an active video line, it takes precedence over the video data and removes NTSC setup if setup has been programmed for the active video lines. Closed Caption is only available when the TMC2192 is in a 13.5 MHz pixel rate. Closed caption is turned on by setting CCON HIGH. Whenever the encoder begins producing a line specified by CCFLD and CCLINE, it will insert a closed caption line in its place. If CCRTS is HIGH, the data contained in CCDx will be sent. IF CCRTS is LOW, Null bytes (hex 00 with ODD parity) will be sent. As soon as CCDx s transferred into the CC processor (and CCRTS goes LOW), new data may be loaded into registers 1C and 1D. This allows the user to transmit CC data on several consecutive lines by loading data for line n+1 while data is being sent on line n. 24 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Interpolation Filters Each video output on the TMC2192 is digitally filtered with sharp-cutoff low-pass interpolation filters. These filters ensure that the frequency band above base-band video and below the pixel frequency (fS/4 to 3fS/4, where fS is the PXCK frequency) are sufficiently suppressed. Since these are fixed-coefficient digital filters, their filter characteristics depend upon clock rate. 10 0 -10 Attenuation (db) -20 -30 -40 -50 -60 -70 -80 0 0.2 0.4 0.6 0.8 1 Frequency (Pixel rate) 65-6294-21 x/Sin(x) Filter Control Registers for this section Address 0x11 Bit(s) 4 Name SINEN The TMC2192 contains a selectable X/sin(X) filter prior to each DAC. The X/sin(X) filter boosts the high frequency data to negate the sin(X)/X roll-off associated with D/A converters. 1.5 1 Attenuation (db) 0.5 0 -0.5 65-6294-22 X/Sin(x) Filter Compensated D/A Output -1 -1.5 -2 0 0.1 Sin(x)/x D/A Roll-Off Figure 17. Interpolation Filter 0.2 0.3 0.4 0.5 Normalized Frequency (PXCK) Figure 19. X/SIN(X) Filter 0.5 0 Attenuation (db) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 0 0.1 0.2 0.3 0.4 Frequency (Pixel rate) 65-6294-20 Output Data Formats Control Registers for this section Address 0x10 0x10 0x10 0x3F 0x3F Bit(s) 5 6 7 7 4 Name LUMADIS CHROMADIS COMPDIS SEL_CLK SEL_PIX 0.5 Figure 18. Interpolation Filter – Passband Detail REV. 1.0.0 8/13/03 25 TMC2192 PRODUCT SPECIFICATION Analog outputs of the TMC2192 are driven by three 10 bit D/A converters, operating at twice the pixel rate. The outputs drive standard video levels into 37.5 or 75 Ohm loads. An internal voltage reference is used to provide reference current for the D/A converters. For more accurate levels, an external fixed or variable voltage reference source is accommodated. The video signal levels from the TMC2192 may be adjusted by varying the common Vref or the 3 independent Rrefs. Each video D/A converter has an independent reference resistor that can adjust the output gain. D/A Matching is achieved by trimming the each external reference resistor of each D/A. Ancillary Data Control Registers for this section Address 0x07 0x07 0x07 0x08 Bit(s) 2 1 0 7-0 Name ANCFREN ANCPHEN ANCTREN ANCID Digital Composite Output In addition, the TMC2192 supplies a 10 bit digital composite signal on pins D[7:0] and FLD[2:1]. The digital composite output can be either an interpolated signal on a non-interpolated signal, this controlled by the control register SEL_CLK. Table 14. Ancillary Data Format Word ID ANC2 ANC1 ANC0 TT MM LL FIELD PH1 PH0 FR4 FR3 FR2 FR1 FR0 Note: 1. P = odd parity bit, x = reserved bit will be ignored The TMC2192 is designed to accept 15 words of ancillary data after the active video pixels at the end of each horizontal line. Ancillary data may occur once per line, once per field, once per eight fields, on random lines, or not al all. The TMC2192 does not assume ancillary data is present on a regular basis. Description Ancillary Data Header (Timing Reference Signal) B7 0 1 1 TT6 0 0 x x PHV PH6 FRV FR27 FR20 FR13 FR6 B6 0 1 1 TT5 D11 D5 x x PH12 PH5 x FR26 FR19 FR12 FR5 B5 0 1 1 TT4 D10 D4 x x PH11 PH4 x FR25 FR18 FR11 FR4 B4 0 1 1 TT3 D9 D3 SVF x PH10 PH3 FR31 FR24 FR17 FR10 FR3 B3 0 1 1 TT2 D8 D2 F2 x PH9 PH2 FR30 FR23 FR16 FR9 FR2 B2 0 1 1 TT1 D7 D1 F1 x PH8 PH1 FR29 FR22 FR15 FR8 FR1 B1 0 1 1 TT0 D6 D0 F0 x PH7 PH0 FR28 FR21 FR14 FR7 FR0 B0 0 1 1 P P P P P P P P P P P P Data Type Word Count Field ID/Synchronous Video Flag reserved Subcarrier Phase Subcarrier Frequency The first three words of ancillary data comprise the TRS signal (ANC2-0) which indicates the end of active video. Also known as the Ancillary data header, the TRS signal is a 00h, FFh, FFh sequence. Except for the TRS words, ancillary data bit 0 (B0, LSB) is odd parity for B7-1. The data type word (TT) is used to specify the ancillary data type. The TMC2192 compares this 7 bit value with the contents of the ANCID control register. If there is a match, the ancillary data will be processed. If there is no match, the TMC2192 ignores ancillary data. The word count data (D11-0 in MM, LL) in the ancillary data packet indicate the number of words in ancillary data. Ancillary phase data is used to program the MSBs of the PHASE register. ANCPHEN and PHV determine how ancillary phase data is used. When ancillary data is not present, the TMC2192 assumes PHV = LOW. 26 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 Table 15. Ancillary Data Control – Phase ANCPHEN 0 1 1 PHV x 0 1 Description Ignore ancillary phase data, set PHASE = 0 Ignore ancillary phase data, no change to PHASE Load ancillary phase data into PHASE registers ancillary frequency data is used. When ancillary data is not present, the TMC2192 assumes FRV = LOW. Table 16. Ancillary Data Control Frequency ANCFREN 0 1 1 FRV x 0 1 Description Ignore ancillary frequency data Ignore ancillary frequency data Load ancillary frequency data into FREQ3-0 registers Ancillary frequency data is used to program the 32 bits of the FREQ3-0 registers. ANCFREN and FRV determine how Table 17. Field Identification and Subcarrier Reset Modes ANCTREN Basic Mode 0 0 Genlocking Mode 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 x x 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Odd field, subcarrier free run Even field Field 1, reset subcarrier at field 1 Field 2 Field 3 Field 4 Field 5 Field 6 Field 7 Field 8 x x x x x x x x 0 1 Odd field, reset subcarrier every 8 fields Even field SVF F2 F1 F0 F (EAV) Field ID / Subcarrier Reset Mode Field Sequence Mode Note: 1. The F bit is part of the EAV timing reference code and tracks the F0 bit. Operating Modes The field number bits (F2-0) from the ancillary data packet FIELD word, are used to program the encoder’s field counter depending upon the state of the synchronous video flag (SVF) and the ANCTREN bit in the control register. In the basic operating mode (ANCTREN = LOW), all timing is found in the F bit of EAV. F2-0 and SVF are ignored and the encoder subcarrier synthesizer is reset to the PHASE value every eight fields (when the field counter transitions from 111 (field 8) to 000 (field 1). In the basic mode, ANCFREN and ANCPHEN are typically set LOW, ignoring ancillary frequency and phase data. If ANCFREN and ANCPHEN are HIGH, the TMC2192 uses the incoming ancillary frequency and phase data on a lineby-line basis. REV. 1.0.0 8/13/03 In genlocking mode (ANCTREN and SVF = HIGH), the subcarrier synthesizer is allowed to free run, with phase and frequency being set from the ancillary data packet PH12-0 and FR31-0 data. The field counter increments just like it does in basic mode. Field sequence mode (ANCTREN = HIGH and SVF = LOW), is the same as basic mode except that the field counter is set by the F2-0 bits in the FIELD word of ancillary data. If ancillary data is not present on a line, the field counter will continue to count as it does in basic mode. When ancillary data is present, the contents of the field counter are loaded with field data (F2-0). In this way, the TMC2192 may be synchronized with an external source by sending field data only once. 27 TMC2192 PRODUCT SPECIFICATION Layering Engine Control Registers for this section Address 0x04 0x05 0x07 0x09 0x09 0x09 0x09 0x09 0x09 0x09 Bit(s) 2 3-2 6 7 6 5 4 3 2 1-0 Name SKEN OMIX SKFLIP HKEN BUKEN SKEXT DKDIS EKDIS FKDIS LAYMODE Address 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Bit(s) 7-0 7-0 7-0 7-0 7-0 7-0 Name DKEYMAX DKEYMIN EKEYMAX EKEYMIN FKEYMAX FKEYMIN The TMC2192 features a robust layering engine with three possible input layers controlled by two keying controls. The layer assignments are shown in Table 22, along with the keying control. The keying controls, KEY pin or OL4-0 are aligned with the incoming pixel data stream and are then delayed throughout the chip to be continuously aligned with the input video streams. A generic overview of the keying and layering features is shown in Figure 21. Table 18. Layering and Keying Modes LAYMODE 0 1 2 3 OL4-0 BACKGROUND Image Source PD PD CVBS CVBS MIDGROUND Image Source OVERLAY CVBS OVERLAY PD Keying Control OL4-0 KEY or Data Key OL4-0 KEY or Data Key FOREGROUND Image Source CVBS OVERLAY PD OVERLAY Keying Control KEY or Data Key OL4-0 KEY or Data Key OL4-0 dT PD OVERLAY MIXER YC PD LOGIC DATA KEY LOGIC KEY dT dT OLUT 1/2AMP CVBS dT dT dT dT KEYING MIXER COMP 65-6294-23 Figure 20. Layering Engine Overlay Mixer The OL[4:0] bus provides the ability to overlay 30 different 24 bit values onto the pixel data path. The 24 bit overlay colors must be the same format as the incoming Pixel data. For Y,Cb,Cr input formats the range of Y values spans the entire range of the format, 1 to 254, this enables super whites and super blacks in the overlay palette. When OL[4:0] is equal to 00h the pixel data port to be the output of the overlay mixer. If OL[4:0] is in the range of 1 to 31 then the output source is one of 30 possible overlay col- ors, see Table 22. Overlay Address Map. When OL4-0 equal to 16, the overlay mixer produces a pixel data output with half the luminance magnitude and chrominance magnitude. Any OL4-0 value greater than 16 will result in a overlay mix with a full amplitude overlay and the pixel data with half amplitude pixel data (PD) or half amplitude CVBS data as its values. This allows for transparent overlays or produce shadow boxes around overlaid text. The midpoint of the rising and falling edges on the mixed output is determined by the transition of the OL[4:0] pins in 28 REV. 1.0.0 8/13/03 PRODUCT SPECIFICATION TMC2192 relation to the PD port. Control register OMIX chooses among the following set of coefficients; either 0 1/8 1/2 7/8 1, 0 1/2 1 , or 0 1 to switch between the PD port and the over- lay color. The timing diagram in Figure 22 identifies the three possible output formats that the mixer can produce. PDx OL[4:0] MixOUT (OMIX = 3) MixOUT (OMIX = 2) MixOUT (OMIX = 1) A A B C D E >0 F G H I 0 A A A 7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL OL OL OL 1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL I I I 65-6294-24 B B 1/2C, 1/2OL OL OL OL OL 1/2G, 1/2OL H H OL OL Figure 21. Overlay Outputs Table 19. Overlay Address Map OL4-0 0 1-15 16 17-31 Result Pixel data is passed through overlay mixer. Overlay is mixed with PD or CVBS at the transitions. Half amplitude PD or half amplitude CVBS is the output of COMP2. Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions. key value and a minimum key value. If the pixel data is greater than xKEYMIN and less than or equal to xKEYMAX, then a key match is signaled for that channel. Hardware Keying The KEY input switches the input to the Comp data path between the composite video generated from the PD port and the CVBS data bus on a pixel-by-pixel basis. This is a “soft” switch is executed over 3 PCK periods to minimize out-ofband transients. Keying is accomplished in the digital composite video domain. The coefficients for the mix are 0, 1/8, 1/2, 7/8, and 1 . The COMP output is the final output for all overlay functions. Hardware keying is enabled by the key Control Register HKEN. Normally, keying is only effective during the active video portion of the encoded video line (as determined by Control Register VA). That is, the horizontal blanking interval is generated by the encoder even if the KEY signal is held HIGH through horizontal blanking. However, it is possible to allow digital horizontal blanking to be passed through from the CVBS bus to the COMP output by setting key Control Register BUKEN HIGH. In this mode, KEY is always active, and may be exercised at will. The KEY input is registered into the encoder just as Pixel data is clocked into the PD port. It is internally pipelined, so the midpoint of the KEY transition occurs at the output of the pixel that was input at the same time at the KEY signal. xKEYMAX A B A