TMC3003R2C50

www.cadeka.com TMC3003 Triple Video D/A Converter 10 bit, 80 Msps Features • • • • • • 10-bit resolution 80, 50, and 30 megapixels per second Sync and blank controls Sync on green D/A output 1.0V p-p video into 37.5Ω or 75Ω load Enhancement of ADV7122 – Internal bandgap voltage reference – Double-buffered data for low distortion • TTL-compatible inputs • Low glitch energy • Single +5 Volt power supply Applications • Video signal conversion – RGB – YCBCR – Composite, Y, C • Multimedia systems • Image processing • True-color graphics systems (1 billion colors) • Broadcast television equipment • High-Definition Television (HDTV) equipment • Direct digital synthesis Description The TMC3003 is a high-speed triple 10-bit D/A converter especially suited for video and graphics applications. It offers 10-bit resolution, TTL-compatible inputs, low power consumption, and requires only a single +5 Volt power supply. It has single-ended current outputs, SYNC and BLANK control inputs, and a separate current source for adding sync pulses to the Green D/A converter output. It is ideal for generating analog RGB from digital RGB and driving computer display and video monitors. Three speed grades are available: 30, 50, and 80 Msps. The TMC3003 triple D/A converter is available in a 44-lead plastic J-leaded PLCC and 48-Lead quad flatpack (LQFP). It is fabricated on a sub-micron CMOS process with performance guaranteed from 0°C to 70°C. Block Diagram SYNC BLANK 10 10 bit D/A Converter G9-0 IOG B9-0 10 10 bit D/A Converter IOB R9-0 CLK 10 10 bit D/A Converter IOR COMP RREF VREF 65-3003-01 +1.235V Ref REV. 1.0.3 3/5/01 TMC3003 PRODUCT SPECIFICATION Functional Description The TMC3003 is a low-cost triple 10-bit CMOS D/A converter designed to directly drive computer CRT displays and video transmission lines at pixel rates of up to 80 Msps. It comprises three identical 10-bit D/A converters with registered data inputs, common clock, and internal voltage reference. An independent current source allows sync to be added to the green D/A converter output. D/A Outputs Each D/A output is a current source. To obtain a voltage output a resistor must be connected to ground. Output voltage of the D/A converters depends upon this resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. Normally, a source termination resistor of 75 Ohms is connected between the D/A current output pin and GND near the D/A converter. A 75 Ohm coaxial cable may then be connected with another 75 Ohm termination resistor at the far end of the cable. This “double termination” presents the D/A converter with a net resistive load of 37.5 Ohms. The TMC3003 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the value of the resistor on RREF should be increased. Digital Inputs All digital inputs are TTL-compatible. Data are registered on the rising edge of the CLK signal. The analog output changes tDO after the rising edge of CLK. There is one stage of pipeline delay on the chip. The guaranteed clock rates of the TMC3003 are 80, 50, and 30 MHz. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC turns off a separate current source which is connected to the green D/A converter. This connection adds a 40 IRE sync pulse to the D/A output and brings that D/A output to 0.0 Volts during the sync tip. SYNC and BLANK are registered on the rising edge of CLK. BLANK gates the D/A inputs and sets the pedestal voltage. If BLANK = HIGH, the D/A inputs are added to a pedestal which offsets the current output. If BLANK = LOW, data inputs and the pedestal are disabled. Voltage Reference The TMC3003 has an internal bandgap voltage reference of +1.235 Volts. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. All three D/A converters are driven from the same reference. A 0.1µF capacitor must be connected between the COMP pin and VDD to stabilize internal bias circuitry and ensure low-noise operation. Power and Ground The TMC3003 D/A converter requires a single +5.0 Volt power supply. The analog (VDD) power supply voltage should be decoupled to GND to reduce power supply induced noise. 0.1µF decoupling capacitors should be placed as close as possible to the power pins. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. data: 660 mV max. pedestal: 54 mV sync: 286 mV 65-3003-02 Figure 1. Nominal Output Levels 2 REV. 1.0.3 3/5/01 PRODUCT SPECIFICATION TMC3003 Table 1. Output Voltage versus Input Code, SYNC, and BLANK VREF = 1.235 V, RREF = 590 Ω, RL = 37.5 Ω RGB9-0 (MSB...LSB) 11 1111 1111 11 1111 1110 11 1111 1101 • • 10 0000 0000 01 1111 1111 • • 00 0000 0010 00 0000 0001 00 0000 0000 xx xxxx xxxx xx xxxx xxxx Red and Blue D/As SYNC X X X • • X X • • X X X X X BLANK 1 1 1 • • 1 1 • • 1 1 1 0 0 VOUT 0.7140 0.7134 0.7127 • • 0.3843 0.3837 • • 0.0553 0.0546 0.0540 0.0000 0.0000 SYNC 1 1 1 • • 1 1 • • 1 1 1 1 0 Green D/A BLANK 1 1 1 • • 1 1 • • 1 1 1 0 0 VOUT 1.0000 0.9994 0.9987 • • 0.6703 0.6697 • • 0.3413 0.3406 0.3400 0.2860 0.0000 Pin Assignments G0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 NC RREF VREF COMP IOR IOG VDD VDD IOB GND GND CLK 48 47 46 45 44 43 42 41 40 39 38 37 44 43 42 41 18 19 20 21 22 23 24 25 26 27 28 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2 G3 G4 G5 G6 G7 G8 G9 BLANK SYNC 40 39 38 37 6 5 4 3 2 7 8 9 10 11 12 13 14 15 16 17 1 PLCC TMC3003 36 35 34 33 32 31 30 29 G1 G2 G3 G4 G5 G6 G7 G8 G9 BLANK SYNC VDD 1 2 3 4 5 6 7 8 9 10 11 12 LQFP TMC3003 36 35 34 33 32 31 30 29 28 27 26 25 RREF VREF COMP IOR IOG OVDD VDD IOB GND GND CLOCK NC 65-3003-05 VDD B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 65-3003-03 NC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 NC REV. 1.0.3 3/5/01 3 TMC3003 PRODUCT SPECIFICATION Pin Descriptions Pin Number Pin Name CLK PLCC 29 LQFP 26 Value TTL Description Clock. The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. Red pixel data inputs. The Red digital input is TTLcompatible and registered on the rising edge of CLK. Clock and Pixel I/O R9-0 5, 4, 3, 2, 1, 44, 43, 42, 41, 40 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37 TTL G9-0 15, 14, 13, 48, 9, 8, 7, 6, 12, 11, 10, 9, 5, 4, 3, 2, 1 8, 7, 6 28, 27, 26, 25, 24, 23, 22, 21, 20, 19 17 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 11 TTL Green pixel data inputs. The Green digital input is TTLcompatible and registered on the rising edge of CLK. Blue pixel data inputs. The Blue digital input is TTLcompatible and registered on the rising edge of CLK. B9-0 TTL Controls SYNC TTL Sync pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA) current source which forms a sync pulse on the Green D/A converter output. SYNC is registered on the rising edge of CLK along with pixel data and has the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. Since this is a single-supply D/A and all signals are positive-going, sync is added to the bottom of the Green D/A range. So turning SYNC OFF means turning the current source ON. When a sync pulse is desired, the current source is turned OFF. If the system does not require sync pulses from the Green D/A converter, SYNC should be connected to GND. BLANK 16 10 TTL Blanking Input. When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK and has the same pipeline latency as SYNC. Red D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Green D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses may be added to the Green D/A output. Blue D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Video Outputs IOR 36 33 0.714 Vp-p IOG 35 32 1 V p-p IOB 32 29 0.714 Vp-p 4 REV. 1.0.3 3/5/01 PRODUCT SPECIFICATION TMC3003 Pin Descriptions (continued) Pin Number Pin Name VREF PLCC 38 LQFP 35 Value +1.235 V Description Voltage Reference output/input. An internal voltage source of +1.235 Volts is output on this pin. An external +1.235 Volt reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. Current-setting resistor. The full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. The nominal value for RREF is found from: RREF = 9.1( VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.4 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/ RL Where VFS is the white voltage level and RL is the total resistive load (in ohms) on each D/A converter. VFS is the blank to full-scale voltage. COMP 37 34 0.1 µF Compensation capacitor. A 0.1 µF ceramic capacitor must be connected between COMP and VDD to stabilize internal bias circuitry. Power supply Ground Voltage Reference RREF 39 36 560 Ω Power and Ground VDD GND 18, 33, 34 30, 31 12, 30, 31 27, 28 +5 V 0.0 V Equivalent Circuits VDD VDD p Digital Input n OUT GND GND 27014C 27013B n VDD p Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit REV. 1.0.3 3/5/01 5 TMC3003 PRODUCT SPECIFICATION Equivalent Circuits (continued) VDD p RREF VREF p GND 27012B Figure 4. Equivalent Analog Input Circuit Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Power Supply Voltage VDD (Measured to GND) Inputs Applied Voltage (measured to GND)2 Forced Current Outputs Applied Voltage (measured to GND)2 Forced Current3,4 Short Circuit Duration (single output in HIGH state to ground) Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -20 110 150 300 220 150 °C °C °C °C °C -0.5 -60.0 VDD + 0.5 60.0 infinite V mA second 3,4 Min -0.5 -0.5 -10.0 Typ Max 7.0 VDD + 0.5 10.0 Unit V V mA Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 6 REV. 1.0.3 3/5/01 PRODUCT SPECIFICATION TMC3003 Operating Conditions Parameter VDD fS Power Supply Voltage Conversion Rate TMC3003-30 TMC3003-50 TMC3003-80 tPWH tPWL ts th VREF CC RL VIH VIL TA CLK Pulsewidth, HIGH CLK Pulsewidth, LOW Input Data Setup Time Input Date Hold Time Reference Voltage, External Compensation Capacitor Output Load Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temperature, Still Air 2.0 GND 0 4 4 3 2 1.0 1.235 0.1 37.5 VDD 0.8 70 1.5 Min 4.75 Nom 5.0 Max 5.25 30 50 80 Units V Msps Msps Msps ns ns ns ns V µF Ω V V °C Electrical Characteristics Parameter IDD Power Supply Current2 Conditions3 VDD = Max TMC3003-30 TMC3003-50 TMC3003-80 PD Total Power Dissipation2 VDD = Max TMC3003-30 TMC3003-50 TMC3003-80 RO CO IIH IIL IREF VREF VOC CDI Output Resistance Output Capacitance Input Current, HIGH Input Current, LOW VREF Input Bias Current Reference Voltage Output Output Compliance Digital Input Capacitance Referred to VDD -0.4 IOUT = 0mA VDD = Max, VIN = 2.4V VDD = Max, VIN = 0.4V 0 1.235 0 4 +1.5 10 100 30 -1 1 ±100 525 525 655 kΩ pF µA µA µA V V pF mW 100 100 125 mA Min Typ1 Max Units Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C. 2. Minimum/Maximum values with VDD = Max and TA = Min. 3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 540Ω REV. 1.0.3 3/5/01 7 TMC3003 PRODUCT SPECIFICATION Switching Characteristics Parameter tD tSKEW tR tF tSET Clock to Output Delay Output Skew Output Risetime Output Falltime Output Settling Time 10% to 90% of Full Scale 90% to 10% of Full Scale to 3%/FS Conditions2 VDD = Min Min Typ1 10 1 2 2 15 Max 15 2 3 3 Units ns ns ns ns ns Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω. System Performance Characteristics Parameter ELI ELD EDM EG TCE VOF PSR Integral Linearity Error Differential Linearity Error DAC to DAC Matching Absolute Gain Error Gain Error Tempco Output Offset Current Power Supply Rejection Conditions2 VDD, VREF = Nom VDD, VREF = Nom VDD, VREF = Nom VDD, VREF = Nom VDD, VREF = Nom VDD = Max, R, G, B = 000h — 20 0.05 Min Typ1 ±0.1 ±0.1 3 Max ±0.25 ±0.25 10 — Units %/FS %/FS % %/FS PPM/°C mA %/% Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω. Timing Diagram t PWL CLK t PWH 1/f S tS PIXEL DATA & CONTROLS DataN tH DataN+1 DataN+2 3%/FS 90% tD OUTPUT 50% t SET tF 10% tR 65-3003-03 8 REV. 1.0.3 3/5/01 PRODUCT SPECIFICATION TMC3003 Applications Discussion Figure 4 illustrates a typical TMC3003 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage reference source. the power supply for the TMC3003 is the same as that of the system's digital circuitry, power to the TMC3003 should be decoupled with 0.1µF and 0.01µF capacitors and isolated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC3003, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC3003 and its related analog circuitry can have an adverse effect on performance. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Grounding It is important that the TMC3003 power supply is wellregulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The TMC3003 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. 4. 5. Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOR, IOG, IOB) as short as possible and as far as possible from all digital signals. The TMC3003 should be located near the board edge, close to the analog output connectors. The power plane for the TMC3003 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If +5V Related Products • • • • • • • • • • • TMC3503 Triple 8-bit 80 Msps D/A Converters TMC1175A 40 Msps CMOS 8-bit A/D Converter TMC1275 40 Msps CMOS 8-bit A/D Converter TMC22091, TMC22191 Digital Video Encoders TMC2242A/TMC2243/TMC2246A Video Filters TMC2249A Digital Mixer TMC2250A Matrix Multiplier TMC2272A Colorspace Converter TMC2302 Image Manipulation Sequencer TMC2340A Digital Synthesizer TMC2081 Digital Video Mixer 2. 10µF 0.1µF Red IO R IO G 75Ω 75Ω 75Ω COMP 0.1µF +5V 3.3kΩ ZO=75Ω VDD RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT R9-0 G9-0 B9-0 GND 75Ω 75Ω 75Ω Green ZO=75Ω Blue ZO=75Ω TMC3003 Triple 10-bit D/A Converter IO B CLOCK SYNC BLANK CLK SYNC BLANK VREF RREF LM185-1.2 (Optional) 0.1µF 560Ω 65-3003-04 Figure 4. Typical Interface Circuit REV. 1.0.3 3/5/01 9 TMC3003 PRODUCT SPECIFICATION Mechanical Dimensions – 44-Lead PLCC Package Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45° 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) .165 .180 .090 .120 .020 — .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 — .004 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 — 0.10 3 2 E E1 J D D1 D3/E3 B1 e J A A1 A2 B –C– LEAD COPLANARITY ccc C 10 REV. 1.0.3 3/5/01 PRODUCT SPECIFICATION TMC3003 Mechanical Dimensions – 48-Lead LQFP Package Symbol A A1 A2 B D/E D1/E1 e L N ND α ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Pin 1 identifier is optional. 7 8 2 6 4 5 4. Dimension ND: Number of terminals. 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. 8. To be determined at seating place —C— .055 .063 .001 .005 .053 .057 .006 .010 .346 .362 .268 .284 .019 BSC .017 .029 48 12 0° 7° .004 1.40 1.60 .05 .15 1.35 1.45 .17 .27 8.8 9.2 6.8 7.2 .50 BSC .45 .75 48 12 0° 7° 0.08 D D1 e E E1 PIN 1 IDENTIFIER C α L 0.063" Ref (1.60mm) See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C REV. 1.0.3 3/5/01 11 TMC3003 PRODUCT SPECIFICATION Ordering Information Product Number TMC3003R2C30 TMC3003R2C50 TMC3003R2C80 TMC3003KRC30 TMC3003KRC50 TMC3003KRC80 Conversion Rate (Msps) 30 Msps 50 Msps 80 Msps 30 Msps 50 Msps 80 Msps Temperature Range TA = 0°C to 70°C TA = 0°C to 70°C TA = 0°C to 70°C TA = 0°C to 70°C TA = 0°C to 70°C TA = 0°C to 70°C Screening Commercial Commercial Commercial Commercial Commercial Commercial Package 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP Package Marking 3003R2C30 3003R2C50 3003R2C80 3003KRC30 3003KRC50 3003KRC80 3/5/01 0.0m 002 Stock#DS30003003