CC5003MBLP

CALIFORNIA MICRO DEVICES NDC ISOLATED RESISTOR NETWORK California Micro Devices’ resistor arrays are the hybrid equivalent to the isolated resistor networks available in surface mount packages. The resistors are spaced on ten mil centers resulting in reduced real estate. These chips are manufactured using advanced thin film processing techniques and are 100% electrically tested and visually inspected. TCR Operating Voltage Power Rating (per resistor) Thermal Shock High Temperature Exposure Moisture Resistance Life Noise Short Time Overload Insulation Resistance 90 Parameter -55°C to +125° -55°C to +125° @ 70°C (D erate linearly to zero @ 150°C) Method 107 MIL-STD -202F 100 Hrs @ 150°C Ambient Method 106 MIL-STD -202F Method 108 MIL-STD -202F (125°C/1000hr) Method 308 MIL-STD -202F ≥250kΩ MIL-R-83401 @25°C ELECTRICAL SPECIFICATIONS Test Condition ±100ppm/°C 50Vdc 50mw ±0.25%@∆R ±0.25%∆R ±0.5%∆R ±0.5%∆R -35 dB -30 dB 0.25% 1 X 1 0 12 Ω Max Max Max Max Max Max Max Max Max Max Min 8 resistors from 100Ω to 346Ω R1 R2 R3 R4 R5 R6 R7 R8 60 VALUES Substrate Isolation Layer Backing Metalization MECHANICAL SPECIFICATIONS Silicon 10±2 mils thick SiO2 10,000Å thick, min Lapped (gold optional) Aluminum 10,000Å thick, min (15,000Å gold optional) Silicon nitride Formats Die Size: 90±3 x 60±3 mils Bonding Pads: 5x7 mils typical Passivation PACKAGING Two inch square trays of 196 chips maximum. NOTE S 1. Resistor pattern may vary from one value to another. CC Series 5003 Value First 3 digits are significant value. Last digit represents number of zeroes. R indicates decimal point. F Tolerance TCR D = ±0.5% No Letter =±100ppm F = ±1% A = ±50% G = ±2% B = ±25% J = ±5% K = ±10% M = ±20% PART NUMBER DESIGNATION N A G W Bond Pads G = Go l d No Letter=Aluminum Backing W = Go l d L = Lapped No Letter=Either P Ratio Tolerance No Letter=±1% P = ±0.5% © 2000 California Micro Devices Corp. All rights reserved. 4/00 C0820400 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1