CM1209

CM1209 4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp Features • • • • • • • Four, six or eight channels of ESD protection for high data rate signals Zener diode protects supply rail and eliminates the need for external by-pass capacitors +15 kV contact, +15 kV air ESD protection per channel (IEC 61000-4-2 standard) Low loading capacitance of 6pF typical Low supply current Available in miniature MSOP and SOIC packages Lead-free versions available Product Description The CM1209 family of diode arrays are designed to provide either 4, 6 or 8 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steer the ESD current pulse either to the positive (VP) or negative (VN) supply. In addition, there is an integral Zener diode between VP and VN to suppress any voltage disturbance due to these ESD current pulses. The CM1209 devices will protect against ESD pulses up to 15kV contact discharge per the International Standard IEC61000-4-2. These devices are particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. They are also suitable for protecting video output lines and I/O ports in computers, set top boxes, digital TVs and peripheral equipment. The CM1209 family of devices is optionally available with lead-free finishing. Applications • • • • • • • ESD protection for a variety of electronic equipment Set Top Boxes Digital TVs I/O & VGA Port protection Desktop and Notebook computers PDAs Cellular Phones Electrical Schematics 8 VP 7 6 5 8 VP 7 6 5 10 9 VP 8 7 6 VN VN VN 1234 CM1209-04 4-Channel 1 234 CM1209-06 6-Channel 1 234 CM1209-08 8-Channel 5 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 1 CM1209 PACKAGE / PINOUT DIAGRAMS TOP VIEW CH 1 CH 2 VN VN 1 2 3 4 8 7 6 5 CH 4 CH 3 VP VN CH 1 CH 2 VN CH 3 TOP VIEW 1 2 3 4 8 7 6 5 CH 6 VP CH 5 CH 4 CH 1 CH 2 CH 3 CH 4 VN TOP VIEW 1 2 3 4 5 10 9 8 7 6 CH 8 CH 7 VP CH 6 CH 5 8-pin MSOP CM1209-04MS/MR Note: These drawings are not to scale. 8-pin SOIC/MSOP CM1209-06SN/SM CM1209-06MS/MR 10-pin MSOP CM1209-08MS/MR PIN DESCRIPTIONS CM1209-04 NAME CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8 VN VP 3,4,5 6 3 7 PIN NO. 1 2 7 8 CM1209-06 PIN NO 1 2 4 5 6 8 CM1209-08 PIN NO 1 2 3 4 6 7 9 10 5 8 TYPE I/O I/O I/O I/O I/O I/O I/O I/O GND Supply DESCRIPTION ESD Channel 1 ESD Channel 2 ESD Channel 3 ESD Channel 4 ESD Channel 5 ESD Channel 6 ESD Channel 7 ESD Channel 8 Negative voltage supply rail or ground reference rail. Positive voltage supply rail. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/09/04 CM1209 Ordering Information PART NUMBERING INFORMATION Standard Finish Ordering Part # of Channels 4 6 6 8 Pins 8 8 8 10 Package MSOP-8 SOIC-8 MSOP-8 MSOP-10 Number1 CM1209-04MS CM1209-06SN CM1209-06MS CM1209-08MS Part Marking 0904 CM1209-06S 0906 0908 Lead-free Finish Ordering Part Number1 CM1209-04MR CM1209-06SM CM1209-06MR CM1209-08MR Part Marking 0914 CM1209-06SM 0916 0918 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (VP - VN) Diode Forward DC Current (Note 1) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating SOIC Package MSOP Package Note 1: Only one diode conducting at a time. RATING 6.0 20 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) 350 200 UNITS V mA °C °C V mW mW STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) RATING -40 to +85 0 to 5.5 UNITS °C V © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 3 CM1209 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL IP VF VZBD ILEAK CIN PARAMETER Supply Current ESD Diode Forward Voltage Zener Clamp Reverse Breakdown Voltage Channel Leakage Current Channel Input Capacitance CONDITIONS (VP-VN)=5.5V; TA=25°C IF = 20mA; TA=25°C At 1mA; TA=25°C TA=25°C At 1 MHz, VP=5V, via 10K; VN=0V, VIN=2.5V; Notes 2 and 6 0.65 7 +0.1 6 +1.0 8 MIN TYP MAX 10 0.95 UNITS µA V V µA pF VESD ESD Protection Peak Discharge Voltage at any channel input and VP rail Contact discharge per IEC 61000-4-2 standard Air discharge per IEC 61000-4-2 standard Channel Clamp Voltage Positive Transients Negative Transients Notes 2, 3, 5, and 6 Notes 2, 3, 5, and 6 At 8kV ESD HBM; TA=25°C; Notes 2, 4 and 6 + 15 15 + kV kV VCL +12.5 - 5.1 I = 1A; TA=25°C; See Figure 2; Note 6 applies I = 1A; TA=25°C; See Figure 2; Note 6 applies 0.70 0.45 V V Ω Ω ZPOS ZNEG Dynamic Resistance of Channel Input for Positive Transients Dynamic Resistance of Channel Input for Negative Transients Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: All parameters specified at TA=-40 to +85°C unless otherwise noted. These parameters guaranteed by design and characterization. From I/O pins to VP or VN only. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω VP = 5.0V, VN grounded. , These measurements performed with no external capacitor on VP.. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/09/04 CM1209 Performance Information 10 Slope = I/ZPOS 8 Cin (pF) 6 Current [I] 4 Slope = I/ZNEG VZBD 2 0 0 1 2 Vin 3 4 5 Voltage [V] Figure 2. IV Curve for CM1209 Figure 1. Typical Variation of Channel Input Capacitance (CIN) vs. Channel Input Voltage (VIN) (VP = 5V via 10K resistor, VN = 0V) Application Information 3 CM1209-06 1 24568 7 0.22µF* I/O Port Buffers Expansion Connector Typical ESD Protection * Optional capacitor should be placed as close as possible to the VP pin on all CM1209 devices. Refer to ’Design Considerations’ text. Figure 3. Application Example Using the CM1209-06 for I/O Port Protection © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 5 CM1209 Application Information Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 4, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L 1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt The CM1209 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22µF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by ∆IESD/∆t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Additional Information See California Micro Devices Application Note AP209, “Design Considerations for ESD Protection", under Applications at www.calmicro.com. L2 VP POSITIVE SUPPLY RAIL PATH OF ESD CURRENT PULSE IESD 0.22µF D1 ONE CHANNEL D2 OF CM1209 L1 CHANNEL INPUT 20A LINE BEING PROTECTED SYSTEM OR CIRCUITRY BEING PROTECTED VCL GROUND RAIL 0A VN CHASSIS GROUND Figure 4. Application of Positive ESD Pulse between Input Channel and Ground © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/09/04 CM1209 Mechanical Details CM1209 devices are packaged in 8-pin and 10-pin MSOP and 8-pin SOIC packages. Dimensions for these packages are presented on the following pages. For complete information on the MSOP-8/-10 or SOICMSOP-8 Mechanical Specifications Mechanical Package Diagrams TOP VIEW 8 packages, see the specific California Micro Devices Package Information document. PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel 2.90 2.90 4.78 0.52 Millimeters Min 0.87 0.05 0.18 3.10 3.10 4.98 0.54 0.114 0.114 0.188 0.017 Max 1.17 0.25 Min 0.034 0.002 MSOP 8 Inches Max 0.046 0.010 D 8 7 6 5 0.30 (typ) 0.012 (typ) 0.007 0.122 0.122 H Pin 1 Marking E 0.65 BSC 0.025 BSC 0.196 0.025 1 2 3 4 SIDE VIEW 80 pieces* 4000 pieces Controlling dimension: inches SEATING PLANE A A1 B e END VIEW * This is an approximate number which may vary. C L Package Dimensions for MSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 7 CM1209 Mechanical Details (cont’d) MSOP-10 Mechanical Specifications Mechanical Package Diagrams TOP VIEW PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel 2.90 2.90 4.76 0.40 Millimeters Min 0.75 0.05 0.18 0.18 3.10 3.10 5.00 0.70 0.114 0.114 0.187 0.0137 4000 Controlling dimension: inches * This is an approximate number which may vary. MSOP 10 Inches Min 0.028 0.002 0.006 Max 0.038 0.006 0.016 0.007 0.122 0.122 1 10 D 9 8 7 6 Max 0.95 0.15 0.40 H Pin 1 Marking E 0.50 BSC 0.0196 BSC 0.197 0.029 2 3 4 5 SIDE VIEW 80 pieces* A SEATING PLANE A1 B e END VIEW C L Package Dimensions for MSOP-10 © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/09/04 CM1209 Mechanical Details (cont’d) SOIC-8 Mechanical Specifications Mechanical Package Diagrams TOP VIEW PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165 D 8 7 6 5 H Pin 1 Marking E 1.27 BSC 0.050 BSC 0.244 0.050 1 2 3 4 SIDE VIEW 100 pcs* 2500 pcs Controlling dimension: inches SEATING PLANE A A1 B e END VIEW * This is an approximate number which may vary. C L Package Dimensions for SOIC-8 © 2004 California Micro Devices Corp. All rights reserved. 01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 9