CM1216-06SM

PRELIMINARY CM1216 6- and 8-Channel Low Capacitance ESD Arrays Features • • • • • • • • • 6 and 8 channels of ESD protection Provides +15 kV ESD protection on each channel per the IEC 61000-4-2 ESD requirements Channel loading capacitance of 1.6 pF typical Channel I/O to GND capacitance difference of 0.04pF typical Mutual capacitance of 0.13pF typical Minimal capacitance change with temperature and voltage Each I/O pin can withstand over 1000 ESD strikes SOIC and MSOP packages Lead-free versions available Product Description The CM1216 family of diode arrays has been designed to provide ESD protection for electronic components or sub-systems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. The CM1216 will protect against ESD pulses up to +15kV per the IEC 61000-4-2 standard. This device is particularly well-suited for protecting systems using high-speed ports such as USB2.0, IEEE1394 (Firewire®, iLink™), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD-RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. The CM1216 family of devices is available with optional lead-free finishing. Applications • • • • • IEEE1394 Firewire® ports at 400Mbps / 800Mbps DVI ports, HDMI ports in notebooks, set top boxes, digital TVs, LCD displays Serial ATA ports in desktop PCs and hard disk drives PCI Express ports General purpose high-speed data line ESD protection Simplified Electrical Schematic CH6 VP CH5 CH4 CH8 CH7 VP CH6 CH5 CH1 CH2 VN CM1216-06MS/MR CM1216-06SN/SM CH3 CH1 CH2 CH3 CM1216-08MS/MR CH4 VN © 2005 California Micro Devices Corp. All rights reserved. 06/30/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1 PRELIMINARY CM1216 PACKAGE / PINOUT DIAGRAM Top View Top View CH1 CH2 VN Top View CH6 VP CH1 CH6 VP 1 2 3 4 5 10 9 8 7 6 CH8 CH7 VP 1 8 CH1 CH2 VN 1 8 CH2 CH3 CH4 VN D168 / E168 D166 / E166 D166 / E166 2 3 4 7 6 5 2 3 4 7 6 5 CH5 CH4 CH5 CH4 CH6 CH5 CH3 CH3 8-pin SOIC-8 8-pin MSOP-8 10-pin MSOP-10 Note: This drawing is not to scale. Pin Configuration PIN DESCRIPTIONS PIN NAME CH1 CH2 CH3 CH4 VN CH5 CH6 VP CH7 CH8 MSOP-8 PIN NO. SOIC-8 PIN NO. MSOP-10 PIN NO. TYPE DESCRIPTION ESD Channel ESD Channel ESD Channel ESD Channel Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail ESD Channel ESD Channel 1 2 4 5 3 6 8 7 − − 1 2 4 5 3 6 8 7 − − 1 2 3 4 5 6 7 8 9 10 I/O I/O I/O I/O GND I/O I/O PWR I/O I/O Ordering Information PART NUMBERING INFORMATION Standard Finish Pins 8 8 10 Package SOIC MSOP MSOP Ordering Part Number1 CM1216-06SN CM1216-06MS CM1216-08MS Part Marking D166 D166 D168 Lead-free Finish Ordering Part Number1 CM1216-06SM CM1216-06MR CM1216-08MR Part Marking E166 E166 E168 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2005 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 06/30/05 PRELIMINARY CM1216 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER Operating Supply Voltage (VP-VN) Diode Forward DC Current (Note 1) DC Voltage at any Channel Input Operating Temperature Range Ambient Junction Storage Temperature Range RATING 6 20 (VN-0.5) to (VP+0.5) -40 to +85 -40 to +125 -40 to +150 UNITS V mA V °C °C °C Standard Operating Condition STANDARD OPERATING CONDITIONS PARAMETER Temperature Range (Ambient) Package Power Rating MSOP8 Package (CM1216-06MS/MR) SOIC8 Package (CM1216-06SN/SM) MSOP10 Package (CM1216-08MS/MR) RATING -40 to +85 400 600 400 UNITS °C mW mW mW © 2005 California Micro Devices Corp. All rights reserved. 06/30/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 3 PRELIMINARY CM1216 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS NOTE 1 SYMBOL VP IP VF PARAMETER Operating Supply Voltage (VP-VN) Operating Supply Current Diode Forward Voltage Top Diode Bottom Diode Channel Leakage Current Channel Input Capacitance Channel Input Capacitance Matching Mutual Capacitance ESD Protection Peak Discharge Voltage at any channel input, in system, contact discharge per IEC 61000-4-2 standard Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive transients Negative transients (VP-VN) = 3.3V IF = 20mA; TA=25°C 0.6 0.6 0.8 0.8 ±0.1 1.6 0.04 0.13 ±15 CONDITIONS MIN TYP 3.3 MAX 5.5 8 0.95 0.95 ±1.0 2.0 UNIT V μA V V μA pF pF pF kV ILEAK CIN ΔCIN CMUTUAL VESD TA = 25°C; VP= 5V, VN = 0V At 1 MHz, VP=3.3V, VN =0V, VIN=1.65V;Note2 Note 2 (VP-VN) = 3.3V; Note 2 Notes 2, 3, and 4; TA = 25°C VCL IPP = 1A, tP = 8/20μS; TA=25°C; Notes 2 IPP = 1A, tP = 8/20μS; TA=25°C; Notes 2 +9.0 -1.5 0.6 0.4 V V Ω Ω RDYN Note 1: Note 2: Note 3: Note 4: All parameters specified at TA = -40°C to +85°C unless otherwise noted. These parameters guaranteed by design and characterization. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 3.3V, VN grounded. From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2μF ceramic capacitor. © 2005 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 06/30/05 PRELIMINARY CM1216 Performance Characteristics Figure 1. Typical Variation of CIN vs. VIN (f = 1MHz, VP= 3.3V, VN = 0V, 0.1μF chip capacitor between VP and VN, TA = 25°C) Figure 2. Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment © 2005 California Micro Devices Corp. All rights reserved. 06/30/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 5 PRELIMINARY CM1216 APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by d(ESD)/dt, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also California Micro Devices Application Note AP-209, “Design Considerations for ESD Protection”, in the Applications section at www.calmicro.com. Figure 3. Application of Positive ESD Pulse between Input Channel and Ground © 2005 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 06/30/05 PRELIMINARY CM1216 Mechanical Details The CM1216 is supplied in SOIC-8, MSOP-8 and MSOP-10 packages with a lead-free finishing option. These package drawings are presented on the follow pages. SOIC-8 Mechanical Specifications CM1216-06SN/SM devices are supplied in 8-pin SOIC packages. Dimensions are presented below. For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document. 8 Mechanical Package Diagrams TOP VIEW D 7 6 5 PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165 0.244 0.050 END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 H Pin 1 Marking E A B e A1 1.27 BSC 0.050 BSC 2500 pieces Controlling dimension: inches C L Package Dimensions for SOIC-8 © 2005 California Micro Devices Corp. All rights reserved. 06/30/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 7 PRELIMINARY CM1216 Mechanical Details MSOP-8 Mechanical Specifications: CM1216-06MS/MR devices are supplied in 8-pin MSOP packages. Dimensions are presented below. For complete information on the MSOP-8 package, see the California Micro Devices MSOP Package Information document. 8 Mechanical Package Diagrams TOP VIEW D 7 6 5 PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tape and reel 2.90 2.90 4.78 0.43 Millimeters Min 0.87 0.05 0.18 3.10 3.10 4.98 0.64 0.114 0.114 0.188 0.017 Max 1.17 0.25 Min 0.034 0.002 MSOP 8 Inches Max 0.046 0.010 1 2 3 4 H E Pin 1 Marking 0.30 (typ) 0.012 (typ) 0.007 0.122 0.122 SIDE VIEW 0.65 BSC 0.025 BSC 0.196 0.025 A SEATING PLANE A1 B e END VIEW 4000 pieces Controlling dimension: inches C L Package Dimensions for MSOP-8 © 2005 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 06/30/05 PRELIMINARY CM1216 Mechanical Details (cont’d) MSOP-10 Mechanical Specifications CM1216-08MS/MR devices are supplied in 10-pin MSOP packages. Dimensions are presented below. For complete information on the MSOP-10 package, see the California Micro Devices MSOP Package Information document. 10 Mechanical Package Diagrams TOP VIEW D 9 8 7 6 PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tape and reel 2.90 2.90 4.76 0.40 Millimeters Min 0.75 0.05 0.18 0.18 3.10 3.10 5.00 0.70 4000 END VIEW MSOP 10 Inches Min 0.028 0.002 0.006 0.114 0.114 0.187 0.0137 Max 0.038 0.006 0.016 0.007 0.122 0.122 0.197 0.029 SIDE VIEW 1 2 3 4 5 H E Pin 1 Marking Max 0.95 0.15 0.40 0.50 BSC 0.0196 BSC A SEATING PLANE A1 B e Controlling dimension: inches C L Package Dimensions for MSOP-10 © 2005 California Micro Devices Corp. All rights reserved. 06/30/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 9