PRELIMINARY CM1230 2, 4 and 8-Channel Low Capacitance ESD Protection Array
Features
• • • • • • • • • • • 2, 4 and 8 channels of ESD protection Provides ESD protection to IEC61000-4-2 Level 4 • ±8kV contact discharge • ±15kV air discharge Low loading capacitance of 0.8pF typical Minimal capacitance change with temperature and voltage Channel I/O to GND capacitance difference of 0.02pF typical is ideal for differential signals Channel I/O to I/O capacitance 0.15pF typical Zener diode protects supply rail and eliminates the need for external by-pass capacitors Each I/O pin can withstand over 1000 ESD strikes Available in 4, 6 and 10 bump Chip Scale Packages (CSP) OptiGuard™ coated for improved reliability at assembly Lead-free version available
Product Description
The CM1230 is a family of 2, 4 and 8 channel, very low capacitance ESD protection diode arrays in CSP form factor. This device is ideal for protecting systems with high data and clock rates or for circuits that require low capacitive loading. Each channel consists of a pair of ESD diodes that act as clamp diodes that steer positive or negative ESD current pulses to either the positive or negative supply rail. A zener diode is integrated into the array between the positive and negative supply rails. The VCC rail is thus protected from ESD strikes and eliminates the need for a bypass capacitor to absorb positive ESD strikes to ground. Each channel of the CM1230 can safely dissipate ESD strikes of ±8kV, meeting the Level 4 requirement of the IEC61000-4-2 international standard for contact discharges as well as ±15kV air discharges per the IEC61000-4-2 specification. Using the MIL-STD-883 (Method 3015) specification for Human Body Model (HBM) ESD, the pins are protected for contact discharges at greater than ±15kV. This device is particularly well-suited for next generation wireless handsets that implement high-speed serial interface solutions for the LCD display and camera interfaces. In these wireless handset designs, a tolerance above 1.5pF cannot be tolerated due to the high data rates that are transferred between the baseband chipset and the LCD driver/controller ICs because a higher capacitive loading will cause the rise and fall times to slow which in turn hampers the functionality of circuit and operation of the wireless handset. The CM1230 incorporates OptiGuard™ which results in improved reliability at assembly. The CM1230 is available in a space-saving, low profile Chip Scale Package with optional lead-free finishing.
Applications
• • • • • LCD and Camera data lines in wireless handsets that use high-speed serial interfaces. I/O port protection for mobile handsets, notebook computers, DSCs, MP3 players, PDAs, etc. including USB, 1394 and Serial ATA Wireless handsets Handheld PCs/PDAs LCD and camera modules
Electrical Schematic
VP CH4 VP CH3 CH8 CH7 VP CH6 CH5
CH1
CH2
VN
CH1
VN
CH2
CH1
CH2
VN
CH3
CH4
CM1230-02CS/CP
CM1230-04CS/CP
CM1230-08CS/CP
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM1230
PACKAGE / PINOUT DIAGRAMS
TOP VIEW (Bumps Down View)
Orientation Marking
(see note 2)
BOTTOM VIEW (Bumps Up View)
1 A B
2
A2 A1 B1
L
CM1230-02 4-Bump CSP Package
B2
Orientation Marking
(see note 2)
1 A B
2
3
A3 A2 B2 A1 B1
A1
L30
CM1230-04 6-Bump CSP Package
B3
Orientation Marking
(see note 2)
1 A B
2
3
4
5
A5 A4 B4 A3 B3 A2 B2 A1 B1
A1
L308
B5
Notes: 1) These drawings are not to scale. 2) Lead-free devices are specified by using a "+" character for the top side orientation mark.
CM1230-08 10-Bump CSP Package
Ordering Information
PART NUMBERING INFORMATION
Standard Finish # of Channels 2 4 8 Bumps 4 6 10 Package CSP-4 CSP-6 CSP-10 Ordering Part Number1 CM1230-02CS CM1230-04CS CM1230-08CS Part Marking L L30 L308 Lead-free Finish2 Ordering Part Number1 CM1230-02CP CM1230-04CP CM1230-08CP Part Marking L L30 L308
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Note 2: Lead-free devices are specified by using a "+" character for the top side orientation mark.
© 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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A1
Orientation Marking
Orientation Marking
Orientation Marking
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03/15/06
PRELIMINARY CM1230
Pin Descriptions
PIN DESCRIPTIONS PIN DESCRIPTIONS (CONT’D)
2-CHANNEL, 4-BUMP CSP
PIN A1 B1 A2 B2 NAME VN CH2 CH1 VP NAME CH1 CH2 VP VN CH3 CH4 TYPE GND I/O I/O PWR DESCRIPTION Negative voltage supply rail ESD Channel ESD Channel Positive voltage supply rail PIN A1 B1 A2 B2 A3 B3 A4 B4 A5 B5
8-CHANNEL, 10-BUMP CSP
NAME CH1 CH2 CH3 CH4 VP VN CH5 CH6 CH7 CH8 TYPE I/O I/O I/O I/O PWR GND I/O I/O I/O I/O DESCRIPTION ESD Channel ESD Channel ESD Channel ESD Channel Positive voltage supply rail Negative voltage supply rail ESD Channel ESD Channel ESD Channel ESD Channel
4-CHANNEL, 6-BUMP CSP
PIN A1 B1 A2 B2 A3 B3 TYPE I/O I/O PWR GND I/O I/O DESCRIPTION ESD Channel ESD Channel Positive voltage supply rail Negative voltage supply rail ESD Channel ESD Channel
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM1230
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating Supply Voltage (VP - VN) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input RATING 6.0 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) UNITS V °C °C V
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range RATING -40 to +85 UNITS °C
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)
SYMBOL PARAMETER VP Operating Supply Voltage (VP-VN) IP VF Operating Supply Current Diode Forward Voltage Top Diode Bottom Diode Channel Leakage Current Channel Input Capacitance Channel Input Capacitance Matching Mutual Capacitance between signal pin and adjacent signal pin In-system ESD Protection Peak Discharge Voltage at any channel input, in system a) Contact discharge per IEC 61000-4-2 standard b) Human Body Model, MILSTD-883, Method 3015 Channel Clamp Voltage Positive Transients Negative Transients Dynamic Resistance Positive Transients Negative Transients CONDITIONS (VP-VN)=3.3V IF = 8mA; TA=25°C 0.60 0.60 0.80 0.80 ±0.1 0.8 0.02 0.15 MIN TYP 3.3 MAX 5.5 8.0 0.95 0.95 ±1.0 1.20 UNITS V μA V V μA pF pF pF
ILEAK CIN
TA=25°C; VP=5V, VN=0V, VIN = 0V to 5V At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V; Note 2 applies At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V; Note 2 applies At 1 MHz, VP=3.3V, VN=0V, VIN=1.65V; Note 2 applies
ΔCIN
CMUTUAL VESD
Notes 2, 4 & 5; TA=25°C Notes 2, 3 & 5; TA=25°C TA=25°C, IPP = 1A, tP = 8/20μS; Notes 2, & 5 IPP = 1A, tP = 8/20μS Any I/O pin to Ground; Note 2 and 5
±8 ±15
kV kV
VCL
+9.8 -1.8 0.76 0.56
V V Ω Ω
RDYN
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
All parameters specified at TA = -40°C to +85°C unless otherwise noted. These parameters guaranteed by design and characterization. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 3.3V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 3.3V, VN grounded. These measurements performed with no external capacitor on VP. Measured under pulsed conditions, pulse width = 0.7ms, maximum current = 1.5A.
© 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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PRELIMINARY CM1230
Performance Information
Input Channel Capacitance Performance Curves
2.000 1.800 1.600
Capacitance (pF)
1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.000 0 0.5 1 1.5 Bias Voltage (V) 2 2.5 3
Typical Variation of CIN vs. VIN
(f=1MHz, VP = 3.3V, VN = 0V, 0.1 μF chip capacitor between VP and VN,
TA = 25°C)
0.90
Capacitance [pF]
0.85 0.80 0.75 0.70 0.65 0.60 -50 -25 0
0V DC Input Bias 1.65 DC Input Bias
25
50
75
100
Temperature ['C]
Typical Variation of CIN vs. Temp
(f=1MHz, VIN=30mV, VP = 3.3V, VN = 0V, 0.1 μF chip capacitor between VP and VN)
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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PRELIMINARY CM1230
Performance Information (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)
Insertion Loss VS. Frequency (0V DC Bias, VP=3.3V)
Insertion Loss VS. Frequency (2.5V DC Bias, VP=3.3V)
© 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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PRELIMINARY CM1230
Application Information
Refer to Application Note AP-217, "The Chip Scale Package", for a detailed description of Chip Scale Packages offered by California Micro Devices.
PRINTED CIRCUIT BOARD RECOMMENDATIONS
PARAMETER Pad Size on PCB Pad Shape Pad Definition Solder Mask Opening Solder Stencil Thickness Solder Stencil Aperture Opening (laser cut, 5% tapered walls) Solder Flux Ratio Solder Paste Type Pad Protective Finish Tolerance — Edge To Corner Ball Solder Ball Side Coplanarity Maximum Dwell Time Above Liquidous (183°C) Maximum Soldering Temperature for a Eutectic Device using Eutectic Solder Paste Maximum Soldering Temperature for a Lead-free Device using Lead-free Solder Paste VALUE 0.275mm Round Non-Solder Mask defined pads 0.325mm Round 0.125mm - 0.150mm 0.330mm Round 50/50 by volume No Clean OSP (Entek Cu Plus 106A) +50μm +20μm 60 seconds 240°C 260°C
Non-Solder Mask Defined Pad 0.275mm DIA. Solder Stencil Opening 0.330mm DIA. Solder Mask Opening 0.325mm DIA.
Figure 1. Recommended Non-Solder Mask Defined Pad Illustration
250
Temperature (°C)
200 150 100 50 0 1:00.0 2:00.0 3:00.0 Time (minutes) 4:00.0
Figure 2. Eutectic (SnPb) Solder Ball Reflow Profile
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
Figure 3. Lead-free (SnAgCu) Solder Ball Reflow Profile
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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PRELIMINARY CM1230
Mechanical Details
CSP-4 Mechanical Specifications The CM1230-02CS/CP is supplied in a 4 bump Chip Scale Package (CSP). Dimensions are shown below. For complete information on the CSP, see the California Micro Devices CSP Package Information document. Mechanical Package Diagrams
BOTTOM VIEW
A1 C1
OptiGuardTM Coating
PACKAGE DIMENSIONS
Package Bumps Dim A1 A2 B1 B2 C1 C2 D1 D2 Millimeters Min Nom Max Min Custom CSP 4 Inches Nom Max
B1 B
B2 A2
A 1 2 C2 D1 D2
0.915 0.960 1.005 0.0360 0.0378 0.0396 0.915 0.960 1.005 0.0360 0.0378 0.0396 0.495 0.500 0.505 0.0195 0.0197 0.0199 0.495 0.500 0.505 0.0195 0.0197 0.0199 0.180 0.230 0.280 0.0071 0.0091 0.0110 0.180 0.230 0.280 0.0071 0.0091 0.0110 0.575 0.644 0.714 0.0226 0.0254 0.0281 0.368 0.419 0.470 0.0145 0.0165 0.0185 3500 pieces
0.30 DIA. 63/37 Sn/Pb (Eutectic) or 96.8/2.6/0.6 Sn/Ag/Cu (Lead-free) SOLDER BUMPS DIMENSIONS IN MILLIMETERS
SIDE VIEW
Package Dimensions for CM1230-02 Chip Scale Package
# per tape and reel
Controlling dimension: millimeters
© 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
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Fax: 408.263.7846
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www.cmd.com
03/15/06
PRELIMINARY CM1230
Mechanical Details (cont’d)
CSP-6 Mechanical Specifications The CM1230-04CS/CP is supplied in a 6 bump Chip Scale Package (CSP). Dimensions are shown below. For complete information on the CSP, see the California Micro Devices CSP Package Information document. Mechanical Package Diagrams
BOTTOM VIEW
A1 C1 B1 B3 B2
OptiGuardTM Coating
PACKAGE DIMENSIONS
Package Bumps Dim A1 A2 B1 B2 C1 C2 D1 D2 Millimeters Min Nom Max Min Custom CSP 6 Inches Nom Max
3 2 1 B A C2 D1 A2
0.915 0.960 1.005 0.0360 0.0378 0.0396 1.415 1.460 1.505 0.0557 0.0575 0.0593 0.495 0.500 0.505 0.0195 0.0197 0.0199 0.495 0.500 0.505 0.0195 0.0197 0.0199 0.180 0.230 0.280 0.0071 0.0091 0.0110 0.180 0.230 0.280 0.0071 0.0091 0.0110 0.575 0.644 0.714 0.0226 0.0254 0.0281 0.368 0.419 0.470 0.0145 0.0165 0.0185 3500 pieces
D2 0.30 DIA. 63/37 Sn/Pb (Eutectic) or 95.5/3.8/0.7 Sn/Ag/Cu (Lead-free) SOLDER BUMPS
SIDE VIEW
NOTE: DIMENSIONS IN MILLIMETERS
Package Dimensions for CM1230-04 Chip Scale Package
# per tape and reel
Controlling dimension: millimeters
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
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Fax: 408.263.7846
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www.cmd.com
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PRELIMINARY CM1230
Mechanical Details (cont’d)
CSP-10 Mechanical Specifications The CM1230-08CS/CP is supplied in a 10 bump Chip Scale Package (CSP). Dimensions are shown below. For complete information on the CSP, see the California Micro Devices CSP Package Information document. Mechanical Package Diagrams
BOTTOM VIEW
A1 C1 B1 B2
OptiGuardTM Coating
PACKAGE DIMENSIONS
Package Bumps Dim A1 A2 B1 B2 C1 C2 D1 D2 Millimeters Min 0.915 2.415 0.495 0.495 0.180 0.180 0.575 0.368 Nom 0.960 2.460 0.500 0.500 0.230 0.230 0.644 0.419 Max 1.005 2.505 0.505 0.505 0.280 0.280 0.714 0.470 Min Custom CSP 10 Inches Nom Max 0.0360 0.0378 0.0396 0.0951 0.0969 0.0986 0.0195 0.0197 0.0199 0.0195 0.0197 0.0199 0.0071 0.0091 0.0110 0.0071 0.0091 0.0110 0.0226 0.0254 0.0281 0.0145 0.0165 0.0185
B A 5 4 3 2 1 B A
A2
0.30 DIA. D2 63/37 Sn/Pb (Eutectic) or 95.5/3.8/0.7 Sn/Ag/Cu (Lead-free) SOLDER BUMPS NOTE: DIMENSIONS IN MILLIMETERS
C2 D1
SIDE VIEW
# per tape and reel
3500 pieces
Controlling dimension: millimeters
Package Dimensions for CM1230-08 Chip Scale Package
© 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM1230
CSP Tape and Reel Specifications
PART NUMBER CM1230-02 CM1230-04 CM1230-08 CHIP SIZE (mm) 0.96 x 0.96 x 0.644 1.46 x 0.96 x 0.644 2.46 x 0.96 x 0.644 POCKET SIZE (mm) B0 X A0 X K0 1.14 x 1.00 x 0.70 1.72 x 1.17 x 0.73 2.62 x 1.12 x 0.76
Po Top Cover Tape
TAPE WIDTH W 8mm 8mm 8mm
REEL DIAMETER 178mm (7") 178mm (7") 178mm (7")
QTY PER REEL 3500 3500 3500
P0 4mm 4mm 4mm
P1 4mm 4mm 4mm
10 Pitches Cumulative Tolerance On Tape ±0.2 mm
Ao W Bo
Ko
For Tape Feeder Reference Only including Draft. Concentric Around B.
Embossment
P1 User Direction of Feed
Center Lines of Cavity
Figure 4. Tape and Reel Mechanical Data
© 2006 California Micro Devices Corp. All rights reserved. 03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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