CM3102

CM3102 Micropower 1.2V/150mA CMOS LDO Regulator with Power Good Features • • • • • • • • • • • 1-5ms Power Good (PG) control signal Regulated 1.2V output 150mA output current Low quiescent operating current (90µA typical) "Zero" disable mode current Foldback current limiting protection Thermal shutdown protection Stable with low-ESR capacitors SOT23-5 package "MIC5258" pinout Lead-free version available Product Description The CM3102 is a low quiescent current (90uA) regulator that delivers up to 150mA of load current at a fixed 1.2V output. In addition, the CM3102 features a Power Good output signal (PG) that goes open drain 1 to 5 ms after the output voltage has exceeded typically 93% of its nominal level. A dedicated control input (EN, Active High) has been included for power-up sequencing flexibility. When this input is taken low, the regulator is disabled. In this state, the supply current will drop to near zero. An internal discharge MOSFET resistance (500Ω) will force the output to ground whenever the device has been shutdown. The CM3102 is fully protected, offering both overload current limiting and high temperature thermal shutdown. Available in a tiny SOT23 package, the device is ideal for space critical applications. The CM3102 is available with optional lead-free finishing. Applications • • • • • Pentium 4 Motherboards Processor Power-up Sequencing Desktop, Notebook and Palmtop Computers PC Cards Peripheral Adapter Cards Pentium 4 Motherboard Application Circuit CM3102-12Sx 10Ω Simplified Electrical Schematic 1.2V VCC3 IN EN GND .1µF* OUT PG VCCVID PG IN 1.2V/150mA OUT EN .1µF + VREF 1.2V * Input capacitor optional. - Typical Application Circuit 47kΩ + CM3102-12Sx VREF X 0.93 2.5ms PG VIN EN 1µF* GND IN EN GND OUT PG 1µF VOUT 1X PG GND * Input capacitor optional. © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 1 CM3102 PACKAGE / PINOUT DIAGRAM Top View IN 1 5 OUT BA12/BB12 GND 2 EN 3 4 PG 5-pin SOT23 Note: This drawing is not to scale. PIN DESCRIPTIONS PIN 1 NAME IN DESCRIPTION Positive input voltage for the regulator. The internal loading on this input is typically 300µA whenever the regulator is enabled, and less than 1µA when the regulator is disabled. Although an input filter capacitor is not required, it is recommended that a 1µF ceramic capacitor be used for additional filtering and stability if this pin is greater than 2 inches from the main input filter. The negative reference for all voltages. Enable/shutdown input. When EN is asserted high (VEN ≥ 1.6V), the regulator is enabled. When EN is asserted low (VEN ≤0.4V), the regulator’s series pass transistor is forced into a high impedance mode and an internal discharge resistance (500Ω) is applied to the output to quickly reduce the output voltage to 0 volts. 4 PG Power Good output. This is an open drain output and functions as a supply voltage supervisor for the output voltage. It is asserted low when the output falls below 89% of its nominal value. This output becomes inactive when VOUT remains above 97% of its nominal value for 1 to 5ms. The regulated voltage output. An output capacitor of 1µF is recommended to minimize any transient load disturbances under normal operating conditions. Additional output capacitance can be used to further improve transient load response. 2 3 GND EN 5 OUT Ordering Information PART NUMBERING INFORMATION Standard Finish Ordering Part Regulator CM3102-12 Pins 5 Package SOT23-5 Number1 CM3102-12ST Part Marking BA12 Lead-free Finish Ordering Part Number1 CM3102-12SO Part Marking BB12 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/20/04 CM3102 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER ESD Protection (HBM) Pin Voltages VIN VOUT VEN Storage Temperature Range Operating Temperature Range Ambient Junction Power Dissipation (See note 1) RATING +2000 [GND - 0.6] to +6.0 [GND - 0.6] to [VIN+0.6] [GND - 0.6] to [VIN+0.6] -40 to +150 0 to +70 0 to +150 Internally Limited UNITS V V V V °C °C °C W Note 1: The power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards using power plane construction will provide this heat spreading ability without the need for additional dedicated copper area. Please consult with factory for thermal evaluation assistance. STANDARD OPERATING CONDITIONS PARAMETER VIN Ambient Operating Temperature Range Load Current COUT VALUE 2.7 to 5.5 0 to +70 0 to 150 1 +20% UNITS V °C mA µF © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 3 CM3102 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VOUT VR LOAD VR LINE ILIM ISC RDISCH IGND PARAMETER Regulator Output Voltage Load Regulation Line Regulation xx Overload Current Limit Short Circuit Current Limit Discharge Resistance Ground Current VOUT < 0.5V EN tied to GND Regulator Enabled (EN=VIN); ILOAD= 0mA Regulator Enabled (EN=VIN); ILOAD= 150mA Regulator Disabled (EN=GND); (Disable Mode) 1.6 0.4 0.01 % of VOUT (PG ON) % of VOUT (PG OFF) IL=100µA; Fault Condition Power Good Off; V PG=5.5V 1 0.02 0.01 5 89 97 0.1 CONDITIONS 0.1mA < ILOAD < 150mA 10mA < ILOAD < 150mA ILOAD = 5mA; 2.7V < V IN < to 3.6V 160 MIN 1.1 TYP 1.2 30 20 350 140 500 90 100 0.01 200 250 10 MAX 1.3 UNITS V mV mV mA mA Ω µA µA µA V V µA % % V µA mS VEN VDIS IEN VPGL VPGH VOL IPG EN Input Logic High Threshold Regulator Enabled EN Input Logic Low Threshold Enable Input Current Power Good Low Threshold Power Good High Threshold Power Good Logic "0" Voltage Power Good Leakage Current Regulator Disabled PG DELAY Delay Time to Power Good Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Timing Diagram © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/20/04 CM3102 Performance Information CM3102 Typical DC Characteristics (nominal conditions unless specified otherwise) Load Regulation 1.25 OUTPUT VOLTAGE [V] OUTPUT VOLTAGE [V] Line Regulation (1% and 100% rated load) 1.30 1.23 1.21 1.19 1.17 1.15 0 50 100 150 200 LOAD CURRENT [mA] 250 1.25 1.20 1mA 150mA 1.15 1.10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE [V] Foldback Current Protection 1.4 POWER GOOD VOLTAGE [V] OUTPUT VOLTAGE [V] Power Good Pull-up Resistor vs. VPG 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.001 0.01 0.1 1 10 100 1000 10000 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 LOAD CURRENT [mA] 400 Power Good Power Fail PULL-UP RESISTOR [kΩ ] Ground Current vs. Load Current (VIN=3.3V) 150 GROUND CURRENT [uA] Ground Current vs. Input Voltage (1mA Load) 150 GROUND CURRENT [uA] 125 100 75 50 25 0 0 50 100 150 200 LOAD CURRENT [mA] 250 125 100 75 50 25 0 0 2 4 6 INPUT VOLTAGE [V] © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 5 CM3102 Performance Information (cont’d) CM3102 Typical DC Characteristics (cont’d, nominal conditions unless specified otherwise) Short Circuit Current vs. Input Voltage SHORT CIRCUIT CURRENT [mA] Current Limit vs. Input Voltage (VOUT=1.15V) 600 500 400 300 200 100 0 180 160 140 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE [V] CURRENT LIMIT [mA] 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE [V] 5.0 Enable Voltage vs. Input Voltage ENABLE THRESHOLD VOLTAGE [V] PGDELAY vs. Input Voltage 2.0 1.10 1.08 1.5 1.06 1.04 PGDELAY [ms] 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.0 1.02 0.5 1.00 INPUT VOLTAGE [V] 0.0 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE [V] 5.0 © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/20/04 CM3102 Performance Information (cont’d) CM3102 Transient Characteristics (nominal conditions unless specified otherwise) (PG connected to VIN with a 47kΩ resistor) Load transient (10% to 90%) Step Response (VIN = 3.3V, CIN = COUT = 1uF Ceramic) Line Transient (0.6Vpp) Step Response (1mA Load, COUT = 1uF Ceramic, no CIN) Enable Response (150mA Load, CIN = COUT = 1uF Ceramic) Cold Start & Power Down (150mA Load, CIN = COUT = 1uF Ceramic) © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 7 CM3102 Performance Information (cont’d) CM3102-12ST/SO Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θ JC) which is defined by the package style, OUTPUT VOLTAGE [V] VOUT 1.230 1.220 1.210 1.200 1.190 1.180 1.170 Variation with TAMB (150mA Load) and the second path is case to ambient (θ CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD (θ JC) + PD (θCA) = TAMB + PD (θJA) The CM3102-12ST/SO uses a SOT23-5 package. When this package is mounted on a double sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting θJA is 175°C/W. OUTPUT VOLTAGE [V] -25 0 25 50 AMBIENT TEMPERATURE [oC] 75 VOUT Variation with TJUNCT (1mA Load) 1.230 1.220 1.210 1.200 1.190 1.180 1.170 -25 0 25 50 75 100 JUNCTION TEMPERATURE [oC] 125 Based on a maximum power dissipation of 315mW (2.1Vx150mA), with an ambient of 70°C the resulting junction temperature will be: TJUNC = TAMB + PD (θ JA) = 70°C + 315mW X (175°C/W) = 70°C + 55°C = 125°C Thermal characteristics were measured using a double sided board with two square inches of copper area connected to the GND pin for "heat spreading". Measurements showing performance up to junction temperature of 125°C were performed under light load conditions (1mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. In the event of no copper area being dedicated for heat spreading, a multi-layer board construction, using only the minimum size pad layout, will provide the CM3102-12ST/SO with an overall θJA of 175°C/W which allows up to 450mW to be safely dissipated for the maximum junction temperature. Short Circuit Current vs. TJUNCT 200 SHORT CIRCUIT CURRENT [mA] 150 100 50 0 -50 -25 0 25 50 75 100 125 JUNCTION TEMPERATURE [oC] © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 01/20/04 CM3102 Mechanical Details SOT23-5 Mechanical Specifications Dimensions for CM3102-12ST/SO device packaged in 5-pin SOT23 package are presented below. For complete information on the SOT23-5 package, see the California Micro Devices SOT23 Package Information document. 5 Mechanical Package Diagrams TOP VIEW e1 e 4 E1 E 1 2 3 PACKAGE DIMENSIONS Package Pins Dimensions A A1 b c D E E1 e e1 L L1 # per tape and reel Millimeters Min -0.00 0.30 0.08 2.75 2.60 1.45 Max 1.45 0.15 0.50 0.22 3.05 3.00 1.75 Min -0.0000 0.0118 0.0031 0.1083 0.1024 0.0571 SOT23-5 (JEDEC name is MO-178) 5 Inches Max 0.0571 0.0059 0.0197 0.0087 0.1201 0.1181 0.0689 END VIEW SIDE VIEW b D A A1 0.95 BSC 1.90 BSC 0.30 0.60 0.60 REF 0.0374 BSC 0.0748 BSC 0.0118 0.0236 L1 L 0.0236 REF 3000 pieces c Package Dimensions for SOT23-5. © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 9