CM3106-12SN

CM3106 2 Amp Source/ Sink Bus Termination Regulator Features • • • • • • • • • Ideal for DDR-I and DDR-II VTT applications Sinks and sources 2.0A for DDR-I Over current protection Over temperature protection Integrated power MOSFETs Excellent accuracy (0.5% load regulation) Pin and functionally compatible with LP2995 8-lead SOIC and PSOP packages Lead-free versions available Product Description The CM3106 is a sinking and sourcing regulator specifically designed for providing power to DDR memory terminating resistors and companion chip set VTT power. The output voltage accurately tracks VDDQ/2. The CM3106 can source and sink current up to 2A, ideal for DDR-I memory systems, and 1.2A for DDR-II systems, while maintaining a load regulation of 0.5% in either application. The CM3106 provides over current and over temperature protection which protects the device from excessive heating due to high current and high temperature. A shutdown capability using an external transistor reduces power consumption and provides a high impedance output. The CM3106 is housed in both 8-lead SOIC and PSOP packages and is available with optional lead-free finishing. Applications • • • Single and Dual Channel DDR Memory Bus Termination Active Termination Buses Graphics Card Memory Termination Simplified Electrical Schematic AVIN VDDQ PVIN Over Temp Over Current Reference 50K Driver VREF OUT IN VTT 50K Buffer VSENSE GND © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 1 CM3106 PACKAGE / PINOUT DIAGRAM TOP VIEW NC GND VSENSE V REF 1 2 3 4 8 7 6 5 TOP VIEW VTT PVIN AVIN VDDQ NC GND VSENSE V REF 1 2 3 4 8 7 GND 6 5 VTT PVIN AVIN VDDQ 8-lead SOIC Note: This drawing is not to scale. 8-lead PSOP PIN DESCRIPTIONS LEAD(S) 1 2 3 4 5 6 7 8 NAME NC GND VSENSE VREF VDDQ AVIN PVIN VTT DESCRIPTION No Connect Ground Feedback Reference Output, VDDQ/2 VDDQ Input Analog Input Power Input Output Ordering Information PART NUMBERING INFORMATION Standard Finish Ordering Part Pins 8 8 Package SOIC-8 PSOP-8 Number1 CM3106-12SN CM3106-12SB Part Marking CM310601S CM3106-12SB Lead-free Finish Ordering Part Number1 CM3106-12SM CM3106-12SH Part Marking CM3106-12SM CM3106-12SH Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3106 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER AVIN O perating Supply Voltage VDDQ Input Voltage Pin Voltages VTT O utput Any other pins ESD (HBM) Storage Temperature Range Operating Temperature Range Ambient Junction Power Dissipation (see note 1) RATING 7 7 7 7 ±2000 -40 to +150 -40 to +85 (see note1) -40 to +150 Internally Limited UNITS V V V V V °C °C °C W Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in a 8-lead SOIC leadframe must be derated at θJA = 151°C/W . θ JA of the 8-lead PSOP is 40°C/W. STANDARD OPERATING CONDITIONS PARAMETER VDDQ AVIN PVIN Ambient Operating Temperature CTT VALUE 2.5 2.5 2.5 0 to +70 220 +20% UNITS V V V °C µF ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL VIN PARAMETER Input Voltage Range VDDQ AVIN AVIN Quiescent Current Load Regulation Output Reference Voltage Output Offset from VREF VREF Output Impedance VDDQ Input Impedance VTT Current Limit Shutdown Temperature Thermal Hysteresis -5µA < IREF < 5µA IVTT = 0A 0A < IVTT < 2.0A or -2.0A < IVTT < 0A VDDQ=2.5V, IREF=0A 1.225 -20 5 100 2.5 150 50 CONDITIONS MIN 2.2 2.2 TYP 2.5 2.5 450 6.25 1.25 1.275 20 MAX AVIN 5.5 UNITS V V µA mV V mV kΩ kΩ A °C °C ICC VRLOAD VREF VOSVTT ZREF ZVDDQ ILIM TDISABLE THYST Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 3 CM3106 Performance Information Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 1. Output Voltage with AVIN Supply (VDDQ=2.5V) Figure 3. Reference Voltage with AVIN Supply (VDDQ=2.5V) Figure 2. Load Regulation (Sink) Figure 4. Load Regulation (Source) © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3106 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 5. Over Current Limit (Sink) Figure 7. Over Current Limit (Source) Figure 6. AVIN Supply Current with Supply Voltage © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 5 CM3106 Performance Information (cont’d) Typical Transient Characteristics (nominal conditions unless otherwise specified) Figure 8. Load Transient (0A to 2.0A Sink) Figure 9. Line Transient (0A to 2.0A Source) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3106 Performance Information (cont’d) Typical Thermal Characteristics (nominal conditions unless otherwise specified) The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θ JC) which is defined by the package style, and the second path is case to ambient (θ CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD (θJC) + PD (θCA) = TAMB + PD (θJA) When a CM3106-12SN is mounted on a double sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting θJA is 151°C/W. Based on the over temperature limit of 150°C with an ambient of 70°C, the available power of this package will be: PD = (150°C - 85°C) / 151°C/W = 0.43W Since the θJA of the CM3106-12SB (PSOP) is 40°C/W, the available power for this package will be: PD = (150°C - 85°C) / 40°C/W = 1.625W DDR Memory Application Since the output voltage is 1.25V, and the device can either source current from VDD or sink current to Ground, the power dissipated in the device at any time is 1.25V times the current load. This means the the maximum average RMS current (in either direction) is 0.344A for the CM3106-12SN and 1.3A for the CM3106-12SB. The maximum instantaneous current is specified at 2A, so this condition should not be exceeded for more than 17% of the time for the CM3106-12SN and 65% of the time for the CM310612SB. It is highly unlikely in most usage of DDR memory that this might occur, because it means the DDR memory outputs are either all high or all low for 17% (SOIC) and 65% (PSOP) of the time. If the ambient temperature is 40°C instead of 85°C, which is typically the maximum in most DDR memory applications, the power dissipated (PD) can be 0.73W, for the CM3106-12SN and 2.75W for the CM310612SB. So the maximum average RMS current © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 increases from 0.42A to 0.58A for the CM3106-12SN and a maximum instantaneous current of 2A should not be exceeded for more than 29% of the time. For CM3106-12SB, the maximum RMS current increases from 1.3A to 2.2A. Thus, the maximum continuous current can be 2A all the time. Figure 10. Duty Cycle vs. Ambient Temperature (ILOAD=2.0A) Figure 11. Duty Cycle vs. Output Current (Temp=70°C) 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 7 CM3106 Performance Information (cont’d) Typical Thermal Characteristics (cont’d) (nominal conditions unless otherwise specified) The theoretical calculations of these relationships show the safe operating area of the CM3106 in the SOIC package. Thermal characteristics were measured using a double sided board with two square inches of copper area connected to the GND pins for "heat spreading". Measurements showing performance up to a junction temperature of 150°C were performed under light load conditions (5mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. Figure 12. Reference Voltage vs. Temperature Figure 13. VTT Output Voltage vs.Temperature (5mA load) Figure 14. AVIN Quiescent Current vs.Temperature © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3106 Application Information CM3106 VDDQ VDDQ VREF CREF VREF AVIN AVIN VSENSE 0.1µF PVIN PVIN GND VTT VTT CTT 220µF CAVIN 47µF CPVIN 47µF Figure 15. Typical Application Circuit PCB Layout Considerations The CM3106-12SB has a heat spreader attached to the underneath of the PSOP-8 package in order for heat to be transferred much easier from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation to spread if the chip is positioned away from the edge of the PCB, and not near other heat dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will ensure a thermal link from the CM3106 package to ambient, θ JA, of around 40°C/W. Figure 16. Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 9 CM3106 Mechanical Details The CM3106 is available in an 8-lead SOIC and PSOP package. SOIC-8 Mechanical Specifications Dimensions for CM3106 devices packaged in 8-pin SOIC packages are presented below. For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document. H Pin 1 Marking 8 Mechanical Package Diagrams TOP VIEW D 7 6 5 E PACKAGE DIMENSIONS Package Leads Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165 END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 A A1 B e 1.27 BSC 0.050 BSC 0.244 0.050 L C 100 pieces* 2500 pieces Controlling dimension: inches Package Dimensions for SOIC-8 * This is an approximate number which may vary. © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3106 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3106 devices packaged in 8-pin PSOP packages with an intagrated heatslug are presented below. Mechanical Package Diagrams TOP VIEW D 8 7 6 5 PACKAGE DIMENSIONS Package Leads Dimensions A A1 B C D E e H L x** y** # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 1.02 5.79 0.41 3.30 2.29 Max 1.62 0.10 0.51 0.25 5.00 3.99 1.52 6.20 1.27 3.81 2.79 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.040 0.228 0.016 0.130 0.090 PSOP-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157 0.060 0.244 0.050 0.150 0.110 1 2 1 2 3 4 H Pin 1 Marking E BOTTOM VIEW D 3 4 Heat Slug x Hy E x/2 y/2 100 pieces* 2500 pieces 8 7 6 5 Controlling dimension: inches SIDE VIEW * This is an approximate number which may vary. ** Centered on package centerline. SEATING PLANE A A1 B e END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 11