CM3107-00SH

CM3107 2 Amp Source/ Sink Bus Termination Regulator for DDR Memory and Front Side Bus Applications Features • • • • • • • • • Ideal for Intel 865 Front Side Bus VTT and DDR VTT applications Sinks and sources 2 Amps Over current protection Over temperature protection Integrated power MOSFETs Excellent accuracy (0.5% load regulation) Selectable output (1.225V/1.45V or VDDQ/2) 8-lead SOIC and PSOP packages Lead-free versions available Product Description The CM3107 is a sinking and sourcing regulator specifically designed for series-parallel bus termination for high-speed chip set busses as well as DDR memory systems. It can source and sink current up to 2.0A with a load regulation of 0.5%. The VTT output voltage is selectable by VDDQSEL and FSBSEL pins. The VDDQSEL pin controls whether the CM3107 is in DDR memory mode with VTT=VDDQ/2, or in FSB mode. In FSB mode, FSBSEL controls whether VTT is 1.225V or 1.45V. This allows the same chip to be used in two different circuits on an Intel 865-based motherboard. The CM3107 provides over current and over temperature protection, which protect the chip from excessive heating due to high current and high temperature. A shutdown capability using an external transistor reduces power consumption and provides a high impedance output. The CM3107 is housed in 8-lead SOIC and PSOP packages and is available with optional lead-free finishing. Applications • • • • Intel 865/845 Front Side Bus termination Single and dual DDR memory termination Active termination buses Graphics card DDR memory termination Simplified Electrical Schematic VCC VDDQSEL FSBSEL VDDQ 50K Over Temp Over Current Reference Output Select Driver VREF OUT IN VTT 50K Buffer VSENSE GND © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 1 CM3107 PACKAGE / PINOUT DIAGRAM TOP VIEW VDDQ VTT GND VSENSE 1 2 3 4 8 7 6 5 TOP VIEW VCC VDDQSEL VREF FSBSEL VDDQ V TT GND VSENSE 1 2 3 4 8 7 GND 6 5 VCC VDDQSEL VREF FSBSEL 8-lead SOIC Note: This drawing is not to scale. 8-lead PSOP PIN DESCRIPTIONS SOIC-8 LEAD(S) 1 2 3 4 5 6 7 8 NAME VDDQ VTT GND VSENSE FSBSEL VREF VDDQSEL VCC DESCRIPTION VDDQ Outputs either 1.225V/1.45V FSB or VDDQ/2 DDR (See note 1) Ground Feedback voltage input Selects FSB output for either VTT=1.225V or 1.45V 1.25V reference voltage input for DDR bus Select output to support FSB or DDR applications Power for internal control circuits Note 1: Assumes VDDQ and VDDQSEL are tied together in DDR application. Ordering Information PART NUMBERING INFORMATION Standard Finish Ordering Part Pins 8 8 Package PSOP-8 SOIC-8 Number1 CM3107-00SB CM3107-00SN Part Marking CM3107-00SB CM310701S Lead-free Finish Ordering Part Number1 CM3107-12SH CM3107-00SM Part Marking CM3107-00SH CM3107-00SM Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC O perating Supply Voltage VDDQ Input Voltage Pin Voltages VTT O utput Any other pins ESD (HBM) Storage Temperature Range Operating Temperature Range Ambient Junction Power Dissipation (see note 1) RATING 7 7 7 7 ±2000 -40 to +150 -40 to +85 -40 to +150 Internally Limited UNITS V V V V V °C °C °C W Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in a 8-lead SOIC leadframe must be derated at θJA = 151°C/W . θ JA of the 8-lead PSOP is 40°C/W. STANDARD OPERATING CONDITIONS PARAMETER VDDQ VCC Ambient Operating Temperature CVOUT VALUE 2.5 to 3.3 2.5 to 3.3 0 to +70 220 ±20% UNITS V V °C µF © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 3 CM3107 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VIN PARAMETER Input Voltage Range VDDQ VCC VCC Quiescent Current Output Voltage IVTT = 0A IVTT = 0A, VDDQ = 2.5V, VDDQSEL= logic "1" = 2.5V VDDQSEL= logic "0", FSBSEL= logic "0" VDDQSEL = logic "0", FSBSEL = logic "1" IVTT = 0A, VDDQ = 3.3V, VDDQSEL= logic "0", FSBSEL= logic "0" VDDQSEL = logic "0", FSBSEL = logic "1" VRLOAD VREF VOSVTT ZREF ZVDDQSEL CLVTT VFSBSEL Load Regulation Output Reference Voltage Output Offset from V REF VREF Output Impedance VVDDQSEL Input Impedance VTT Current Limit Output Selection Logic (FSBSEL) Logic "1" Level Logic "0" Level Shutdown Temperature Thermal Hysteresis 1.5 0.4 150 50 -5µA < IVREF < 5µA 0A < IVTT < 2.0A or 0A < IVTT < -2.0A VDDQSEL = 2.5V, IVREF=0A 1.225 -20 5 100 2.5 1.225 1.200 1.425 CONDITIONS MIN 2.2 2.2 TYP 2.5 2.5 450 1.250 1.225 1.450 1.275 1.250 1.475 MAX VCC 5.5 UNITS V V µA V V V V ICC VTT 1.200 1.425 1.225 1.450 6.25 1.250 1.250 1.475 V V mV 1.275 20 V mV kΩ kΩ A V V °C °C TDISABLE THYST Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Performance Information Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 1. Output Voltage with VCC Supply (VDDQSEL= 2.5V) Figure 3. Reference Voltage with VCC Supply (VDDQSEL= 2.5V) Figure 2. Load Regulation (Sink) Figure 4. Load Regulation (Source) © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 5 CM3107 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 5. Over Current Limit (Sink) Figure 7. Over Current Limit (Source) Figure 6. Output Voltage with VCC Supply Voltage (VDDQSEL = 0V, FSBSEL = 0V) Figure 8. Output Voltage with VCC Supply Voltage (VDDQSEL = 0V, FSBSEL = 2.5V) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 9. VCC Supply Current with Supply Voltage Typical Transient Characteristics (nominal conditions unless otherwise specified) Figure 10. Load Transient (0A to 2.0A Sink) Figure 11. Line Transient (0A to 2.0A Source) © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 7 CM3107 Performance Information (cont’d) Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θ JC) which is defined by the package style, and the second path is case to ambient (θ CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD (θJC) + PD (θCA) = TAMB + PD (θJA) When a CM3107-00SN (SOIC) is mounted on a double sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting θJA is 151°C/W. Based on the over temperature limit of 150°C with an ambient of 85°C, the available power of this package will be: PD = (150°C -85°C) / 151°C/W = 0.43W For the CM3107-00SB (PSOP), the θJA is 40°C/W and the available power for this package will be: PD = (150°C -85°C) / 40°C/W = 0.1.625W DDR Memory Application Since the output voltage is 1.25V, and the device can either source current from VDDQ or sink current to Ground, the power dissipated in the device at any time is 1.25V times the current load. This means the maximum average RMS current (in either direction) is 0.344A for CM3107-00SN and 1.3A for CM3107-00SB. The maximum instantaneous current is specified at 2A, so this condition should not be exceeded 17% and 65% of the time for CM3107-00SN and CM3107-00SB, respectively. It is highly unlikely in most usage of DDR memory that this might occur, because it means the DDR memory outputs are either all high or all low for 17% (SOIC) and 65% (PSOP) of the time.. If the ambient temperature is 40°C instead of 85°C, which is typically the maximum in most DDR memory applications, the power dissipated PD can be 0.73W for CM3107-00SN and 2.75W for CM3107-00SB. So the maximum average RMS current increases from 0.42A to 0.58A for CM3107-00SN and maximum © 2004 California Micro Devices Corp. All rights reserved. instantaneous current of 2A should not be exceeded 29% of the time. For CM3107-00SB, the maximum RMS current increases from 1.3A to 2.2A. Thus, the maximum continuous current can be 2A all the time. Figure 12. Duty Cycle vs. Ambient Temperature (ILOAD = 2A) Figure 13. Duty Cycle vs. Output Current (Temp=70°C) 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Performance Information (cont’d) Typical Thermal Characteristics (cont’d) Front Side Bus Application If the CM3107-00SN is instead used for the Front Side Bus application, where VDDQ could be connected to the 3.3V VCC rail for ease of connectivity, the power dissipated will increase to [3.3V-1.4V] = 1.9V times the sourcing current, or [1.4V - 0V] = 1.4V times the sinking current. So the worst case is with all FSB outputs low for a period of time, such that the maximum average source current at an ambient of 40°C is [0.73W / 1.9V] = 0.38A. If this average current is exceeded, the device will go over-temperature and the output will drop to 0V. If it is likely that this average current will be exceeded for the FSB application, then the version with the heat spreader, CM3107-00SB, should be used, or for commonality of device type for both applications, the VDDQ pin should instead be connected to 2.5V. The maximum average source current at an ambient of 40°C is [2.75W/1.9V] = 1.45A. The theoretical calculations of these relationships show the safe operating area of the CM3107 in the SOIC and PSOP packages. Thermal characteristics were measured using a double sided board with two square inches of copper area connected to the GND pins for "heat spreading". Figure 15. Output Voltage vs. Ambient Temperature (ILOAD=5mA) Measurements showing performance up to a junction temperature of 150°C were performed under light load conditions (5mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. Figure 14. Reference Voltage vs. Temperature Figure 16. Quiescent Current vs. Temperature Figure 17. © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 9 CM3107 Application Information VCC VDDQ CVDDQ 47µF VDDQ VDDQSEL FSBSEL GND VCC VREF VREF CVREF 0.1µF CVCC 47µF VDDQSEL FSBSEL VTT VSENSE VTT CVTT 220µF Figure 18. Typical Application Circuit Figure 19. Typical Front Side Bus with Suspend to RAM Application Circuit © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Application Information (cont’d) VCC (CPU Core) GMCH_EN VDDQSEL "1" Open or "0" Open or "0" FSBSEL Don’t Care "0" "1" VTT VDDQSEL/2 (Note1) 1.225V 1.45V NOTE For DDR For FSB For FSB GMCHVCCP Note 1:Assumes VDDQ and VDDQSEL are tied together in DDR application. Figure 20. Front Side Bus Timing diagram PCB Layout Considerations The CM3107-00SB has a heat spreader attached to the underneath of the PSOP-8 package in order for heat to be transferred much easier from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of Table 1: VTT Output Selection Truth Table. the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation to spread if the chip is positioned away from the edge of the PCB, and not near other heat dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will ensure a thermal link from the CM3107 package to ambient, θ JA, of around 40°C/W. Table 2: Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 11 CM3107 Mechanical Details The CM3107 is available in an 8-lead SOIC and PSOP package. SOIC-8 Mechanical Specifications Dimensions for CM3107 devices packaged in 8-pin SOIC packages are presented below. For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document. H Pin 1 Marking 8 Mechanical Package Diagrams TOP VIEW D 7 6 5 E PACKAGE DIMENSIONS Package Leads Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165 END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 A A1 B e 1.27 BSC 0.050 BSC 0.244 0.050 L C 100 pieces* 2500 pieces Controlling dimension: inches Package Dimensions for SOIC-8 * This is an approximate number which may vary. © 2004 California Micro Devices Corp. All rights reserved. 12 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 02/02/04 CM3107 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3107 devices packaged in 8-pin PSOP packages with an intagrated heatslug are presented below. For complete information on the PSOP-8 package, see the California Micro Devices PSOP-8 Package Information document. Mechanical Package Diagrams TOP VIEW D 8 7 6 5 PACKAGE DIMENSIONS Package Leads Dimensions A A1 B C D E e H L x** y** # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 1.02 5.79 0.41 3.56 2.29 Max 1.62 0.10 0.51 0.25 5.00 3.99 1.52 6.20 1.27 4.06 2.79 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.040 0.228 0.016 0.130 0.090 PSOP-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157 0.050 0.244 0.050 0.150 0.110 H Pin 1 Marking E 1 2 3 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x Hy E x/2 y/2 8 7 6 5 100 pieces* 2500 pieces Controlling dimension: inches SIDE VIEW A SEATING PLANE A1 B e END VIEW * This is an approximate number which may vary. ** Centered on package centerline. C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214 L Fax: 408.263.7846 L www.calmicro.com 13