CM3132

PRELIMINARY CM3132 Triple Linear Voltage Regulator for DDR-I Memory and CPU Features • • • • • • • • • Fully integrated power solution for a CPU/SOC core and DDR-I memory ICs Lowest system cost and smallest footprint with just three external output capacitors Three linear regulators for VCORE (1.5A), VDDQ (1.5A), and VTT (0.5A, source-sink) Product Description The CM3132 provides an integrated power solution for a CPU core and DDR-I memory for consumer and other embedded applications. It features three independent linear regulators for VCORE, VDDQ and VTT supply regulation. The default voltage for VCORE is 1.5V. The SENSE_CORE pin can be tied to GND for the default voltage, or through a resistor divider for setting the CPU core in the range 1.2V to 1.8V. VDDQ is internally set to 2.50V and the VTT voltage is always half the VDDQ voltage. A capacitor should be connected to each of the three outputs. There are two enable pins, EN_CORE and EN_DDR. When EN_CORE is set high, the CORE regulator is disabled. When EN_DDR is set high, the two DDR regulators are disabled to minimize overall system power dissipation when memory is in standby mode. These two enable pins allow power sequencing of the DDR and CORE regulator blocks independently. The CM3132 is available in a PSOP-8 package that has excellent thermal dissipation. It is available with optional lead-free finishing. VDDQ = 2.5V, VTT = VDDQ/2 ±25mV VCORE is adjustable, with a default output of 1.5V Over-temperature and reverse current protection Overcurrent protection for all regulators PSOP-8 package with integrated heat spreader Lead-free version available Applications • Core CPU and DDR-I memory power for: − Set Top Boxes, DVD Players, Games − Digital TVs, Flat Panel Displays − Printers, Digital Projectors − Embedded systems − Communications systems Typical Application Circuit 2.8V to 3.3V Circuit Schematic VCC VREF VDDQ REGULATOR VDDQ VDDQ = 2.5V VCC VDDQ REGULATOR CVCC VREF EN_DDR Enable DDR Memory # EN_DDR CDDQ DDR MEMORY R R CTT VTT REGULATOR VREF=1.25V VTT=1.25V R R VTT REGULATOR VTT VREF VCORE REGULATOR VCORE R3 VREF CPU CORE + I/O CCORE VCORE REGULATOR VCORE Enable CORE# EN_CORE SENSE_CORE R4 EN_CORE SENSE_CORE GND GND © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1 PRELIMINARY CM3132 PACKAGE / PINOUT DIAGRAM TOP VIEW VCORE VCC VDDQ VTT 1 2 3 4 8 7 6 5 SENSE_CORE GND EN_CORE EN_DDR 8-Lead PSOP Note: This drawing is not to scale. PIN DESCRIPTIONS PSOP-8 LEAD 1 2 3 4 5 6 7 8 PAD NAME VCORE VCC VDDQ VTT EN_DDR EN_CORE GND SENSE_CORE GND DESCRIPTION VCORE output. Input supply. VDDQ output. VTT output for termination resistors or VREF Enable DDR power. Active low input. Enable VCORE. Active low input. Ground reference. Sense input. Adjusts VCORE output voltage using external resistor divider. When tied to GND, VCORE = 1.5V. Tied to ground reference. Ordering Information PART NUMBERING INFORMATION Standard Finish Leads 8 Package PSOP-8 Ordering Part Number1 CM3132-02SB Part Marking CM3132 02SB Lead-free Finish Ordering Part Number1 CM3132-02SH Part Marking CM3132 02SH Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER ESD (Human Body Model) Pin Voltages VCC EN_CORE, EN_DDR, SENSE_CORE VDDQ, VTT Storage Temperature Range Operating Temperature Range Ambient Junction RATING UNITS V V V V °C °C °C ±2000 [GND - 0.6] to [+6.5] [GND - 0.6] to [VCC + 0.6] [GND - 0.6] to [VCC + 0.6] -40 to +150 0 to +85 0 to +125 STANDARD OPERATING CONDITIONS PARAMETER Ambient Operating Temperature Range 1. VDDQ Regulator DDR-I Supply Voltage VCC Load Current CCC, CDDQ 2. VTT Regulator DDR-I Supply Voltage VDDQ DDR-I Load Current CTT 3. VCORE Regulator Core Supply Voltage VCC DDR-I Load Current CCORE [VDDQ or VCORE + 0.3] to 3.6 0 to 1500 10 V mA µF 2.3 to 2.8 0 to ±500 47 V mA µF [VDDQ + 0.3] to 3.6 0 to 1500 10, 10 V mA µF RATING 0 to +85 UNITS °C © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 3 PRELIMINARY CM3132 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS SYMBOL TOVER THYST ICCN ICCQ ISENSE IN VIH VIL UVLO tRISE VCC MIN VDDQ DEF VDDQ LD VDDQ LINE eN DDQ IDDQ LIM IDDQ SC PARAMETER Shutdown Junction Temperature Junction Temp Hysterisis Normal Mode VCC Supply Current Shutdown Mode VCC Supply Current SENSE_CORE Input Current EN_DDR, EN_CORE Input High Threshold EN_DDR, EN_CORE Input Low Threshold Under Voltage Lock-Out VDDQ, VCORE Rise TIme Input Voltage Default Output Voltage Load Regulation Line Regulation Output Noise Voltage Current Limit Short Circuit Current IC in shutdown EN_DDR = logic "0", EN_CORE =logic "0" EN_DDR = logic "1", EN_CORE =logic "1" VSENSE_CORE=0.6V VCORE=3.3V VCORE=3.3V IDDQ = 10mA VCC = 3.3V, CLOAD = 10µF VDDQ = 2.5V, IDDQ = 1.5A, Note 2 IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 TA = 25°C, VCC = 3.3V, 0.01A ≤ IDDQ ≤ 1.5A, Note 2 -1.0 49 1.7 2.0 0.5 1.0 % µVrms A A 2.8V ≤ VCC ≤ 3.6V, Note 2 BW = 10Hz - 100kHz, CDDQ = 10µF Note 2 VDDQ < 0.3V 2.80 2.45 2.50 2.55 2.5 0.5 2.0 0.4 1.8 CONDITIONS General Parameters 150 25 400 2 0.1 800 10 1.0 °C °C µA µA µA V V V ms (SEE NOTE1) MIN TYP MAX UNITS VDDQ Regulator Parameters V V % TA = 25°C, IDDQ = 0.01A, © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE1) VTT Regulator Parameters VTT VTT REF VTT LD eN TT ITT LIM ITT SC VCC MIN VCORE DEF VCORE ADJ VCORE LD Output Voltage Range Output Voltage Range Load Regulation Output Noise Voltage Current Limit Short Circuit Current VTT < 0.7V VCORE = 1.5V, ICORE = 1.5A, SENSE_CORE = 0V, Note 3 VCC = 3.3V, ICORE = 0.01A, SENSE_CORE = 0V VCC = 3.3V, SENSE_CORE from resistors R3 & R4, Note 4 TA = 25°C, VCC = 3.3V, 0.01A ≤ ICORE ≤ ±1.5 TA = 25°C, 2.8V ≤ VCC ≤ 3.6V, ICORE = 0.01A BW = 10Hz - 100kHz, CCORE = 47µF 1.7 VCORE < 0.3V 2.2 1.45 1.2 -1.0 59 2.0 0.5 1.50 1.55 1.8 2.5 1.0 VDDQ = 2.5V, ITT = 0.01A, IDDQ = 0A VCC = 0V, VDDQ = 2.500V, ITT = 0.01A TA = 25°C, VDDQ = 2.5V, 0.01A ≤ ITT ≤ ±0.5A BW = 10Hz - 100kHz, CTT = 10µF 0.6 1.20 1.225 -1.0 1.25 1.250 51 0.8 0.3 1.30 1.275 1.0 V V % µVrms A A VCORE Regulator Parameters Input Voltage Default Output Voltage Range Adjustable Output Voltage Range Load Regulation V V V % % µVrms A A VCORE LINE Line Regulation eN CORE ICORE LIM ICORE SC Output Noise Voltage Current Limit Short Circuit Current Note 1: All parameters specified at TA = 0°C to +85°C unless otherwise noted. Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A.The maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. Note 3: VCORE regulator only. Refer to VDDQ regulator parameters for VDDQ regulator. Note 4: VCORE = 1.15V X (1 + ------- ) R3 R4 VCC(1) 2.8V to 3.6V X EN_DDR Low High VDDQ OUT VDDQ 0V VTT OUT VDDQ / 2 0V Table 1: Truth Table for CM3132 © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 5 PRELIMINARY CM3132 Performance Information Power Supply Ripple Rejection CCC = 10µF, VCC = 3.3V, ILOAD = 50mA, PSRR measured with 50mV pk-pk sin wave on VCC. 50 45 40 35 PSRR (dB) 30 25 20 15 10 5 0 10 100 1000 Frequency (Hz) 10000 100000 Figure 1. VCORE PSRR (VCORE = 1.5V) 50 45 40 35 PSRR (dB) 30 25 20 15 10 5 0 10 100 1000 Frequency (Hz) 10000 100000 Figure 2. VDDQ PSRR (VDDQ = 2.5V) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 60 50 40 PSRR (dB) 30 20 10 0 10 100 1000 Frequency (Hz) 10000 100000 Figure 3. VTT PSRR (VTT = 1.25V) © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 7 PRELIMINARY CM3132 Performance Information (cont’d) Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θJC) which is defined by the package style, and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD ( θJC ) + PD ( θCA ) = TAMB + PD ( θJA) When a CM3132-02SB (PSOP-8) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting θJA is 40°C/W. Based on the over temperature limit of 150° C with an ambient of 70°C, the available power of this package will be: 150 ° C – 70 ° C PD = -------------------------------------- = 2W 40 ° C/ W PCB Layout Considerations The CM3132-02SB/SH has a heat spreader attached to the bottom of the PSOP-8 package in order for heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3132 package to ambient, θJA, of around 40°C/W. Figure 4. Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Application Information Other Applications The CM3132 can be used without any external resistors if a core voltage of 1.5V is required, the SENSE_CORE pin is connected to GND. In applications where a reference voltage (VREF) is required, the VTT pin can be used. The VTT output pin has an error relative to VDDQ/2 of up to ±25mV, which is well within most DDR system specs of ±50mV. This is because the VTT output internally tracks the VDDQ output very closely due to the matched on-chip resistors R that tap down from the VDDQ rail, and the low offset voltage of the VTT regulator. It is recommended that the VREF trace be connected directly to the VTT pin, as shown in Figure 5, to eliminate noise and ripple on the VTT trace caused by current switching. 2.8V to 3.3V CVCC VCC VDDQ REGULATOR VREF VDDQ = 2.5V Enable DDR Memory EN_DDR CDDQ DDR-I MEMORY R R CTT VTT REGULATOR VREF=1.25V VTT=1.25V VREF VCORE REGULATOR VCORE=1.5V CPU CORE + I/O Enable CORE EN_CORE SENSE_CORE CCORE GND Figure 5. Minimal cost solution for CM3132 supplying DDR memory and core CPU. © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 9 PRELIMINARY CM3132 Application Information (cont’d) 1 PSOP-8 IC drives 1-DIMM single channel DDR-I and CPU Core VCORE rail VCC VCC VDDQ REGULATOR VDDQ=2.5V, 1A MAX, 1A CONTINUOUS VREF Enable DDR Memory EN_DDR CDDQ DDR-I MEMORY R R VTT REGULATOR VREF=1.25V, 0.5A MAX, 0.1A CONTINUOUS CM3132-02 PSOP-8 VREF VCORE REGULATOR CTT VCORE=1.5V, 1A MAX, 1A CONTINUOUS CPU CORE + I/O Enable CORE EN_CORE SENSE_CORE CCORE GND With 3.3VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (3.3-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.3-1.5) * 1 = 0.84 + 0.125 + 1.8 = 2.765W With 3.0VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (3.0-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.0-1.5) * 1 = 0.525 + 0.125 + 1.5 = 2.15W With 2.8VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (2.8-2.5) * 1.05 + (2.5-1.25) * 0.1 + (2.8-1.5) * 1 = 0.315 + 0.125 + 1.3 = 1.74W Figure 6. Power Dissipation Calculations PD = (Vcc-2.5)*Iddq + (2.5-1.25)*0.1 + (Vcc-Vcore)*Icore PD - (Vcc-2.5)*Iddq - 0.125 = (Vcc-Vcore)*Icore Icore = [PD - (Vcc-2.5)*Iddq - 0.125] / (Vcc-Vcore) TJUNC = TAMB + PD * (θJA) PD = (TAMB - TJUNC ) / (θJA) Derating (degC/W) 40 Ambient (degC) 85 40 85 1.6 3.0 1.5 0.8 0.7 60 85 1.1 3.0 1.5 0.5 0.5 80 85 0.8 3.0 1.5 0.3 0.4 40 85 1.6 2.8 1.5 0.5 1.0 60 85 1.1 2.8 1.5 0.6 0.6 80 85 0.8 2.8 1.5 0.3 0.5 40 60 2.3 3.3 1.5 1.0 0.7 60 60 1.5 3.3 1.5 1.0 0.3 80 60 1.1 3.3 1.5 0.5 0.3 40 60 2.3 3.0 1.4 1.0 1.0 60 60 1.5 3.0 1.5 0.7 0.7 80 60 1.1 3.0 1.5 0.5 0.5 40 60 2.3 2.8 1.0 1.0 1.0 60 60 1.5 2.8 1.5 0.5 0.9 80 60 1.1 2.8 1.5 0.5 0.7 40 40 2.8 3.3 1.5 1.0 1.0 60 40 1.8 3.3 1.5 0.5 0.7 80 40 1.4 3.3 1.5 0.5 0.5 40 40 2.8 3.0 1.2 1.0 1.0 60 40 1.8 3.0 1.5 0.7 1.0 80 40 1.4 3.0 1.5 0.7 0.6 40 40 2.8 2.8 1.1 1.0 1.4 60 40 1.8 2.8 1.4 1.0 1.0 80 40 1.4 2.8 1.5 0.5 0.8 θJA = 40 oC/W Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 1.6 3.3 1.5 1.0 0.4 Derating (degC/W) 60 Ambient (degC) 85 θJA = 60 oC/W Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 1.1 3.3 1.5 0.3 0.4 Derating (degC/W) 80 Ambient (degC) 85 θJA = 80 oC/W Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 0.8 3.3 1.5 0.3 0.2 Figure 7. Power Derating Table © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3132 devices packaged in an 8lead PSOP package with a heatspreader are shown below. Mechanical Package Diagrams TOP VIEW PACKAGE DIMENSIONS Package Leads Dimensions A A1 B C D E e H L x** y** # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 1.02 5.79 0.41 3.30 2.29 Max 1.62 0.10 0.51 0.25 5.00 3.99 1.52 6.20 1.27 3.81 2.79 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.040 0.228 0.016 0.130 0.090 PSOP-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157 0.060 0.244 0.050 0.150 0.110 D 8 7 6 5 H Pin 1 Marking E 1 2 3 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x Hy x/2 E y/2 100 pieces* 2500 pieces Controlling dimension: inches 8 7 6 5 * This is an approximate number which may vary. SIDE VIEW ** Centered on package centerline. A SEATING PLANE A1 B e END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11