CM8888-2

CALIFORNIA MICRO DEVICES CM8888/8888-2 CMOS INTEGRATED DTMF TRANCEIVER Fea tur es • Advanced CMOS technology for low power consumption and increased noise immunity • Complete DTMF • Transmitter/Receiver • Standard 8051, 8086/8 microprocessor port • Central office quality and performance • Adjustable guard time • Automatic tone burst mode • Call progress mode • Single +5 volt power supply • 20-pin DIP, 20-pin DIP EIAJ, 20-pin SOIC, 28-pin PLCC packages • 2 MHz microprocessor port operation Applications • Paging systems • Repeater systems/mobile radio • Interconnect dialers • PABX systems • Computer systems • Fax machines • Pay telephones • Credit card verification Product Description The CAMD CM8888/8888-2 is a fully integrated DTMF Transceiver, featuring adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The CM8888/8888-2 is manufactured using state-of-the-art advanced CMOS technology for low power consumption and precise data handling. The CM8888/8888-2 is based on the industry standard CM8870 DTMF Receiver, while the transmitter utilizes a switchedcapacitor D/A converter for low distortion, highly accurate DTMF signaling. Internal counters provide an automatic tone burst mode which allows tone bursts to be transmitted with precise timing. A call progress filter can be selected by an external microprocessor for analyzing call progress tones. The CM8888-2 is electrically equivalent to the CM8888 but does not include the call progress function. Block Diagram All trademarks are the property of their respective holders. © 2000 California Micro Devices Corp. All rights reserved. 5/00 C0400798D 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES Absolute Maximum Ratings: (See Note) CM8888/8888-2 This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Note: Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied. ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage (VD D -VS S ) Voltage on any Pin Current on any Pin Operating Temperature Storage Temperature Symbol VD D Vdc ID D TA TS Value 6.0V Max -0.3V to VD D +0.3V 10mA Max -40°C to +85°C -65°C to +150°C DC Characteristics: All voltages referenced to VSS, VDD = 5.0V + 5%, fc = 3.579545 MHz, TA = -40°C to +85°C unless otherwise noted. Parameter Operating Supply Voltage Operating Supply Current Power Consumption Inputs High Level Input Voltage OSCI Low Level Input Voltage OSCI Input Impedance, (@ 1KHz) IN+INSteering Threshold Voltage (V DD=5.0V) Outputs High Level Output Voltage (No Load) OSC2 Low Level Output Voltage (No Load) OSC2 Output Leakage Current (VOH=2..4V) IRQ VREF Output Voltage (No Load) VREF Output Resistance D ata Bus (D O-D 3, RD , WR, RSO, CS) Low Level Input Voltage High Level Input Voltage Low Level Output Voltage (I High Level Input Voltage (I OL=1.6mA) OH=400µA) DC CHARACTE RISTICS Symbol Min VDD 4.75 ID D PO V I HO VI LO RI N VTst VOHO VOLO IOZ V R EF ROR VI L VI H VOL VOH II Z 2.4 2.0 3.5 Typ* 5.0 10 Max 5.25 52.5 Units V mA mΩ V V MΩ V V 1.5 2.2 4.9 1.0 2.4 0.1 10.0 2.7 1 0.8 0.4 10.0 10.0 2.3 2.5 V µA V KΩ V V V V µA Input Leakage Current (VI N=0.4 to 2.4V) I Operating Characteristics - Gain Setting Amplifier: All voltages referenced to VSS, VDD = 5.0V + 5%, fc = 3.579545 MHz, TA = -40°C to +85°C unless otherwise noted. OPE RATING CHARACTE RISTICS Parameter Symbol Min Typ II N 10 0 Input Leakage Current( VS S < VI N < VD D ) Input Resistance Input Offset Voltage Power Supply Rejection (1 KHz) Common Mode Rejection(-3.0V < VI N 100KΩ to VS S ) Maximum Capacitive Load (GS) Maximum Resistive Load (GS) Common Mode Range (No Load) ©2000 California Micro Devices Corp. All rights reserved. Max Units nA MΩ mV dB dB dB MHz Vpp pF KΩ Vpp RI N VO S P SR R CMRR AV O L BW VO CL RL Vc m 10 25 60 60 65 1.5 4.5 10 0 50 3.0 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES AC Characteristics: All voltages referenced to VSS, VDD = 5.0V + 5%, fc = 3.579545 MHz, TA = -40°C to +85°C unless otherwise noted. Parameter Receive Signal Conditions Valid Input Signal Levels (Each Tone of Composite Signal; Notes 1,2,3,4,5,6,9) Positive Twist Accept (Notes 2,3,6,9) Negative Twist Accept (Notes 2,3,6,9) Freq. D eviation Accept Limit (Notes 2,3,5,9) Freq. D eviation Reject Limit (Notes 2,3,5) Third Tone Tolerance ( 2,3,4,5,9,10) Noise Tolerance ( 2,3,4,5,7,9,10) D ial Tone Tolerance ( 2,3,4,5,8,9,11) Lower Frequency (@ -25 dBm) ACCEPT Upper Frequency (@ -25 dBm) ACCEPT Lower Frequency (@ -25 dBm) ACCEPT Upper Frequency (@ -25 dBm) ACCEPT Receive Timing Tone Present D etection Time Tone Absent D etection Time Min Tone D uration Accept (Ref. Fig 9) Max Tone D uration Reject (Ref. Fig 9) Min. Interdigit Pause Accept (Ref. Fig 9) Max. Interdigit Pause Reject (Ref. Fig 9) Propagation D elay (St to b3) Propagation D elay (St to RXO - RX3) Transmit Timing Tone Burst D uration (D TMF Mode) Tone Pause D uration (D TMF Mode) Tone Burst D uration (Extended, Call Process Mode) Tone Pause D uration (Extended, Call Process Mode) Tone Output High Group Output Level (RL = 10KΩ) Low Group Output Level (RL= 10KΩ) Pre-emphasis (RL = 10KΩ) Output D istortion (RL = 10K Ω 3.4 KHz Bandwidth) Frequency D eviation (f = 3.5795 MHz) Output Load Resistance AC CHARACTE RISTICS Symbol Min -29 27.5 Typ CM8888/8888-2 Max +1 869 10 10 Units dBm mVRMS dB dB Nom. Nom. dB dB dB Hz Hz Hz Hz ±1.5% ±2Hz ±3.5% -16 -16 22 320 510 290 540 5 0.5 20 40 20 13 8 50 50 10 0 10 0 52 52 10 4 10 4 11 4 14 8.5 40 FLA FHA FLR FHR tDP tDA tREC tREC tID tDO tPStb3 tPStRX tBST tPS tBSTE tPSE mS mS mS mS mS µS µS µS mS mS mS mS VHOUT VLOUT dBP TH D fD RLT -6.1 -8.1 0 2 -25 ±0.7 10 -2.1 -4.1 3 dBm dBm dB dB % KΩ ±1.5 50 © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CALIFORNIA MICRO DEVICES A Characteristics: VDD = 5.0V + 5%, VSS = OV, TA = -40°C to +85°C C AC CHARACTE RISTICS CM8888/8888-2 Parameter Microprocessor Interface RD , WR, Low Pulse Width RD , WR, High Pulse Width RD , WR, Rise and Fall Address Hold Address Setup Read D ata Hold RD to Valid D ata D elay (200 pF Load) Write D ata Setup Write D ata Hold Input Capacitance D O-D 3 Output Capacitance IRQ CP D TMF Clock Crystal Clock Frequency Clock Input Rise Time (External Clk.) Clock Input Fall Time (External Clk.) Clock Input D uty Cycle (External Clk.) Capacitive Load OSC2 Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40mS. Tone pause = 40 mS. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. Symbol tCL tCH tR , tF tAH tAS tD H R tD D R tD SW tD H W tCIN t OU T fc tL H CL tL H CL D CCL C LO Min 200 18 0 Typ* Max Unit ns ns ns ns ns ns ns ns ns pF pF MHz ns ns % pF 25 10 23 22 150 45 10 5 5 3.5759 3.5795 3.5831 110 110 60 30 40 50 * Typical values are for use as design aids only, and are not guaranteed or subject to production testing. 6. 7. 8. 9. 10. 11. The tone pair is deviate by + 1.5% + 2Hz. Bandwidth limited (3 KHz) Gaussian Noise. The precise dial tone frequencies are 350 and 440 Hz (+2%) For an error date of less than 1 in 10,000. Referenced to the lowest amplitude tone in the DTMF signal. Referenced to the minimum valid accept level. ©2000 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES CM8888/8888-2 © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5 CALIFORNIA MICRO DEVICES Explanation Of Events A. Tone bursts detected, tone duration invalid RX data register not updated. B. Tone #n detected, tone duration valid, tone decoded and latched in RX data register. C. End of tone #n detected, tone absent duration valid, information in RX data register retained until next valid tone pair. D. Tone #n + 1 detected, tone duration valid, tone decoded and latched in RX data register. E. Acceptance dropout of tone #n + 1, tone absent duration invalid, data remains unchanged. F. End of tone #n + 1 detected, tone absent duration valid, inforamtion in RX data register retained until next valid tone repair. Explanation Symbols DTMF composite input signal. VIN ESt Early steering output, Indicates detection of valid tone frequencies. St/GT Steering input/guard time output. Drives external RC timing circuit. CM8888/8888-2 RX0-RX3 4-bit decoded data in receive data register. b3 Delayed steering. Indicates that valid freqeuncies have been present/absent for the required guard time thus consituting a valid siganal. b2 Indicates that valid data is in the receive data register. The bit is cleared after the status register is read. IRQ/CP Interupt is active indicating that new data is in the RX data register. The interupt is cleared after the status register is read. tREC Maximum DTMF signal duration not detected as valid. tREC Minimum DTMF signal duration required for valid recognition. Minimum time between valid sequencial tID DTMF signals. Maximum allowable dropout during valid tDO DTMF signal. Time to detect valid frequencies present. tDP Time to detect valid frequencies absent. tDA Guard time, tone present. tGTP Guard time, tone absent. tGTA Functional Description The CM8888 Integrated DTMF Transceiver provides the design engineer with not only low power consumption, but central office quality performance. The CM8888’s internal architecture consists of high performance DTMF receiver with an internal Gain Setting Amplifier and DTMF gernerator. The DTMF Generator contains a Tone Burst Counter for generating precise tone bursts and pauses. The Call Progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers and two data registers within the CM8888. Input Configuration The CM8888 input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op amp output (GS) for gain adjustment. In the single-ended configuration, the input pins should be connected as shown in Figure 1, while Figure 2 shows the necessary connections for a differential input configuration. ©2000 California Micro Devices Corp. All rights reserved. 6 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES Receiver Section Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs to two sixth order switched capacitor bandpass filters, the bandwidths of which correspond to the low and highgroup frequencies as shown in Figure 5. The lowgroup filter incorporates notches at 350 Hz and 440 Hz for excellent dial-tone rejection. Each filter output is followed by a single-order switched capacitor filter section which smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide fullrail logic swings at the incoming DTMF signals frequencies. Following the filter section is a decoder which employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that the incoming tones correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals (e.g. voice), while still providing tolerance to small deviations in frequency. The averaging algorithm was developed to ensure and optimum combination of immunity to talk-off , as well as a tolerance to the presence of two valid tones (sometimes referred to as “signal condition” in industry publications), the “Early Steering” (EST) output will go to and active state. Any subsequent loss of signal condition will cause ESt to assume and inactive state. SteeringCircuit Before registration of a decoded tone pair, the receiver CM8888/8888-2 checks for a valid signal duration (referred to as Character Recognition Condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (See Figure 3) to rise as the capacitor discharge. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (See Figure 5) into the Receive Data Register. At this point the GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the Delayed Steering output flag goes high, signalling that a received tone pair has been registered. It is possible to monitor the status of the Delayed Steering flag by checking the appropriate bit in the Status Register. If Interrupt Mode has been selected, the IRQ/CP pin will pull low when the Delayed Steering flag is active. The contents of the output latch are updated on an active Delayed Steering transition. This data is presented to the 4-bit bi directional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. VOLTAGE GAIN Figure 1. Single Ended Input Configuration Figure 2. Differential Input Configuration © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 7 CALIFORNIA MICRO DEVICES Guard Time Adjustment The simple steering circuit shown in Figure 3 is adequate for most applications. Component values are chosen according to the formula: tREC = tDP + tGTP tID = tDA + tGTA The value of tDP is a device parameter and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGPT) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard Time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance CM8888/8888-2 since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short tREC with a ling tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for Guard Time adjustments is shown in Figure 4. Figure 3. Basic Steering Circuit Figure 4. Guard Time Adjustment Call Progress Filter (CM8888) A Call Progress (CP) Mode can be selected allowing the detection of various tones which identify the progress of a telephone call on the network. The Call Progress tone input and DTMF input are common, however, call progress tones can only be detected when the CP Mode has been selected. DTMF signals cannot be detected if the CP Mode has been selected (see Table 5). Figure 6. indicates the useful detect bandwidth of the Call Progress filter. Frequencies presented to the input (IN + and IN-) which are within the ‘accept’ bandwidth limits of the filter are hard-limited by a highgain comparator with the IRQ/CP pin serving as the output. The square wave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the Call Progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected, and consequently there will be no activity on IRQ/CP as a result of these frequencies. FLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 DIGIT 1 2 3 4 5 6 7 8 9 0 # A B C D D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0=LOGIC LOW, 1=LOGIC HIGH Figure 5. Function Encode/Decode ©2000 California Micro Devices Corp. All rights reserved. 8 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES DTMF Generator The DTMF transmitter employed in the CM888 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.58 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal, data conforming to the encoding format shown in Figure 5 must be written to the Transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as low-group and high-group tones. As seen from Table 1, the Low-Group frequencies are 697, 770, 852, and 941 Hz; the High-Group frequencies are 1209, 1336, 1477, and 1633 Hz. Typically the HighGroup to Low-Group amplitude ratio (twist) is 2dB to compensate for High-Group attenuation on long loops. CM8888/8888-2 circuits are employed to produce row and column tones which are then mixed using a low noise summing amplifier. The oscillator described needs no “”start-up” time as in other DTMF generators since the crystal oscillator is running continuously, thus providing a high degree of tone burst accuracy. Under conditions when there is no tone output signal, the TONE pin assumes a DC level of 2.5 volts (typ.) A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 4 KHz. It can be seen from Figure 7 that the distortion products are very low in amplitude. Figure 7 Spectrum Plot ACTIVE CELL L1 L2 L3 L4 H1 H2 H3 H4 OU T P U T F R E QU E N CY ( H z) SPECIFIED 697 770 852 941 1209 1336 1447 1633 Figure 6 Call Progress Response ACTUAL 699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 1645.0 % ERROR +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73 DTMF Generator Operation The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the transmit data register, 4-bit data on the bus is latched and converted to of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length which will ultimately determine the frequency for the tone. When the divider reaches the appropriate count as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32; however, by varying the segment length as described above, the frequency can also be varied. The divider output clocks another counter which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical Table 1 Actual Frequencies Versus Standard Requirements Burst Mode In certain telephony applications it is required that DTMF signals being generated be of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 mS + 1 mS which is a standard interval for autodialer and central office applications. After the burst pause has been issued, the appropriate bit is set in the Status Register, indicating that the transmitter is ready for more data. The timing described above is available when the DTMF Mode has been selected. However, when CP © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 9 CALIFORNIA MICRO DEVICES Mode (Call Progress Mode is selected, a secondary burst/ pause time is available such that this interval is extended to 102 mS + 2 mS. The extended interval is useful when precise tone bursts of longer than 51 mS duration and 51 mS pause are desired. Note that when CP mode and burst mode have been selected, DTMF tones may be transmitted only and not received. In certain applications where a nonstandard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. The CM8888 is initialized on power-up sequences such that DTMF mode and burst mode are selected. CP mode and burst mode have been selected, DTMF tones may be transmitted only and not received. In certain applications where a nonstandard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. The CM8888 is initialized on power-up sequence such that DTMF mode and burst mode are selected. Single Tone Generation A Single Tone Mode is available whereby individual tones from the low-group or high-group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B (Table 6) description for details. Distortion Calculations The CM8888 is capable of producing precise tone bursts with minimal error in frequency (See Table1). The internal summing amplifier is followed by a first-order low-pass switched-capacitor filter to minimize harmonic components and intermodulation products. CM8888/8888-2 calculated using equation 2. VL and VH correspond to the low-group amplitude, respectively, and V2IMD is the sum of all the intermodulation components. The interval switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 7. DTMF Clock Circuit The internal clock circuit is complete with the addition of a standard television color burst crystal having a resonant frequency of 3.579545 MHz. A number of CM8888 devices can be connected as shown in Figure 8 such that only one crystal is required. Figure 8 Common Crystal Connection Table 2. Internal Register Functions Table 3. CRA Bit Positions Equation 1. THD (%) For a Single Tone Table 4. CRA Bit Positions Equation 2. THD (%) For a Dual Tone The total harmonic distortion for a single tone can be calculated using Equation 1 which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier components of the tone output correspond to V2f...Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be Microprocessor Interface The CM8888 employs a microprocessor interface which allows precise control of transmitter and receiver functions. There are five internal registers associated with the microprocessor interface which can be subdivided into three categories, ie; data transfer, transceiver control and transceiver status. There are two registers associated with ©2000 California Micro Devices Corp. All rights reserved. 10 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES data transfer operations. The Receive Data Register contains the output code of the last valid DTMF tone pair to be decoded and is a read-only register. The data entered in the Transmit Data Register will determine which tone pair is to be generated (See Figure 5 fro coding details). Data can only be written to the Transmit Data Register. Transceiver control is accomplished with two Control Registers (CRA and CRB) which occupy the same address space. A write operation to CRB can be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be directed to CRB and subsequent write cycles will then be directed Table 5. Control Regsiter A Description CM8888/8888-2 back to CRA. Internal reset circuitry will clear the control registers on power-up; however, as a precautionary measure the initialization software should include a routine to clear the registers. Refer to Table 5 and 6 for details concerning the Control Registers. The IRQ/CP pin can be programmed such that it will provide and interrupt request signal upon validation of DTMF signals, or when the transmitter is ready for more data (Burst mode only). The IRQ/CP pin is configured as an opendrain output device and as such requires a pull-up resistor (See Figure 9). Bit bo b1 N am e TOUT CP/D TMF b2 IR Q b3 RSEL CONTROL RE GISTE R A DE SCRIPTION Function D escription Tone Output A logic '1' enables the Tone Output. This function can be implemented in either the Burst Mode or Non-Burst Mode. Mode Control In D TMF (logic '0'), the device is capable of generating and receiving D ual Tone Multi-Frequency signals. When the CP (Call Progress) mode is selected (logic '1'), a 6th order bandpass filter is enabled to allow Call Progress tones to be detected. Call Progress tones which are within the specified bandwidth will be presented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (B2=1). Also when the CP mode and Bust Mode have both been selected, the transmitter will issue D TMF signal with a burst and pause of 102 mS (typ) duration. This signal duration is twice that obtained from the D TMF transmitter, if D TMF mode had been selected. Note that signals connot be decoded when the CP mode of operation has been selected. Interrupt Enable A logic '1' enables the Interrupt Mode. When this mode is active and the D TMF Mode has been selected (b1=0), the IRQ/CP pin will pull to a logic '0' condition when either 1) a valid D TMF signal has been received and has been present for the guard time duration or 2) the transmitter is ready for more data (Burst Mode onl y ) . Register A logic '1' selects Control Register B on the next write cycle to the Control Register address. Subsequent write cycles to the Control Register are directed back to Control Register A. © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11 CALIFORNIA MICRO DEVICES CM8888/8888-2 ©2000 California Micro Devices Corp. All rights reserved. 12 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5/00 CALIFORNIA MICRO DEVICES Table 7. Status Register Description Bit Name Status Flag Set CM8888/8888-2 Status Flag Cleared bo b1 IRQ Transmit Data Register Interrupt has occured. Bit one (b1) and/or bit two (b2) is set. Pause duration has terminated and transmitter is ready for new data. Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in Non-Burst Mode. Cleared after Status Register is read. Cleared upon the detection of a valid DTMF signal. b2 b3 Receive Data Register Full Delayed Steering Pin Function Table Name Description Name Description N+ INGS Non-inverting op-amp input. Inverting op-amp input Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. References voltage output. Nominally VDD /2 is used to bais inputs at inputs at mid-rail (see application circuit). Negative power supply input. DTMF clock/oscillator input. Clock output. A 3.5795 MHz crystal connected between OSC1 AND OSC2 completes the internal oscillator circuit. Dual tone Multi-Frequency (DTMF) output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip Select. TTl input. (CS =0 to select the chip). Register select input. See register decode table. TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible. VREF IRQ/CP Interupt request to microprocessor (open-drain output). Also, when Call Progress (CP) Mode has been selected and Interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative of the input siganl applied at the input opamp. The input signal must be within the bandwidth limits of the Call Progress filter. See Filter 6. DO-D3 Microprocessor data bus. TTL compatible. ESt Early Spring output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause EST to return to a logic low. Steering input/Guard Time output (bidierectional). A voltage greater than VTS, detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTS, frees the device to accept a new tone pair. The GT output acts to reset the external steering timeconstant; its state is a function of ESt and the voltage on St. Positive power supply input. VSS OSC1 OSC2 TONE WR StGT CS RSO RD V DD © 2000 California Micro Devices Corp. All rights reserved. 5/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 13