CMPWR025

CALIFORNIA MICRO DEVICES CMPWR025 Dual Input SmartOR™ Power Switch FEATURES • Automatically selects V CC1 OR V CC2 input source • Integrated low impedance switches (0.2Ω TYP) • Operating supply range from 2.8V to 5.5V • Glitch-free output during supply switching transitions • Low operating supply current of 20µA (TYP) • User-selectable hysteresis for supply selection • 8-pin SOIC Narrow or 8-pin MSOP packages APPLICATIONS • PCI cards for Wake-On-LAN/Wake-On-Ring • Dual power systems • Systems with standby capabilities • Battery backup systems • See Application Note AP211 PRODUCT DESCRIPTION California Micro Devices’ SmartOR™ CMPWR025 is a dual input power switch that selects between two different power inputs and delivers it to one output. The device integrates two very low impedance power switches and automatically implements an OR function that selects the higher of the two inputs. A hysteresis is built in (and is user selectable) to prevent switch chatter. The CMPWR025 is a much-improved solution to simply ORing two diodes, due to the greatly reduced losses of the CMPWR025 when compared to low forward drop Schottky diodes. The CMPWR025 is designed to operate above the 1W (375mA at 3.3V) sleep mode rating stated in the PCI Rev 2.2 spec. In fact the CMPWR025 current rating is dependent upon the power dissipation resulting from the voltage drop across the internal switch elements. See the Typical DC Characteristics section in this data sheet for details. For IAPC (Instantly Available Personal Computer) applications see the CAMD Applications Note AP211 “Instantly Available PCI Card Power Management”. PIN DIAGRAM, TYPICAL APPLICATION CIRCUIT, AND SIMPLIFIED BLOCK DIAGRAM Top View VCC1 VCC1 VCC2 VCC2 1 2 3 4 8 7 6 5 HYS VOUT VOUT GND + – CMPWR025 VCC1 VCC2 VCC1 5V + VOUT VOUT + HYS GND VCC2 – 5V COUT 10µF CMPWR025 8-Pin SOIC Narrow and MSOP Package Pin Diagram GND VCC1 + – SW1 0.2Ω Typical Application Circuit GND SW2 0.2Ω VOUT VCC2 HYS GND GND GND Simplified Block Diagram © 2000 California Micro Devices Corp. All rights reserved. 10/18/2000 C0970500 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES ABSOLUTE MAXIMUM RATINGS Parameter ESD Protection (HBM) VCC1 VCC2 Input Voltage Storage Temperature Range Operating Ambient Operating Junction Maximum DC IOUT Power Dissipation Rating 2000 +6.0, GND –0.5 –40 to +150 0 to +70 0 to +125 750 0.3 CMPWR025 Unit V V oC mA W O P E R AT I N G C O N D I T I O N S Parameter VCC1, VCC2 Input Voltage Ambient Temperature Rating 2.8 to 5.5 0 to 70 Unit V °C Symbol V CCDES1 V CCDES2 V CC1SEL VHYS1 VHYS2 tDL tDH RSW ELECTRICAL OPERATING CHARACTERISTICS (over operating conditions unless specified otherwise) Parameter Conditions Min V CC1 D e s e l e c t Not e 1 Typ 125 200 50 75 150 200 200 0.28 0.21 28 56 140 21 42 105 Max 200 300 100 100 200 Unit mV mV mV mV mV ns Ω Ω V CC1 D e s e l e c t 2 Not e 1 V CC1 S e l e c t P r e fe r e n c e N o t e 1 H y s t e r e s i s Not e 1 Switching delay Note 3 Switch Resistance Voltage Drop Across Switch (VCC1,2 – VOUT) V C C 1 D e s e l e c t l ev e l b e l o w V C C 2 Pi n 8 ( HYS) f l oat i ng V C C 1 D e s e l e c t l ev e l b e l o w V C C 2 Pi n 8 ( HYS) gr o u n d e d 50 90 10 VCC1SEL – VCC1DES, Pin 8 floating VCC1SEL – VCC1DES, Pin 8 grounded VCC1, 2 falltime < 100ns VCC1, 2 risetime < 100ns ILOAD = 0 to 500mA VCC1,2 = 2.8V ILOAD = 0 to 500mA VCC1,2 = 5.0V 40 80 0.4 0.3 40 80 200 30 60 150 100 100 VSW IOUT = 100mA (VCC1, VCC2 = 2.8V) IOUT = 200mA (VCC1, VCC2 = 2.8V) IOUT = 500mA (VCC1, VCC2 = 2.8V) IOUT = 100mA (VCC1, VCC2 = 5V) IOUT = 200mA (VCC1, VCC2 = 5V) IOUT = 500mA (VCC1, VCC2 = 5V) mV mV IRCC1 IRCC2 ICC1, ICC2 IGND Reverse Leakage Supply Current Ground Pin Current VCC1 = 0V, VCC2 = 5V VCC1 = 5V, VCC2 = 0V When Selected (IOUT = 0) When not Selected VCC1 = VCC2, = 5V, ILOAD = 0mA to 500mA 20 1.0 20 µΑ µΑ 50 µΑ Note 1: This parameter applies at 25°C only. Note 2: Hysteresis level defines the maximum level of acceptable noise on VCC during switching. Excessive parasitic inductance on VCC board traces to the CMPWR025 may require an input capacitor to adequately filter the supply noise to below the hysteresis level. This will ensure that precise switching occurs between VCC1 and VCC2 supply inputs. Note 3: This is the time, after the select/deselect threshold is reached, for the switches to react. Not tested, guaranteed by device design and characterization. ©2000 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 10/18/2000 CALIFORNIA MICRO DEVICES CMPWR025 INTERFACE SIGNALS VCC1 is the primary power source, which is given priority when present. If pin 8 (HYS) is unconnected, then the hysteresis level is 75mV (typ.). Whenever the primary power source drops below the secondary supply VCC2 by more than 125mV, it will immediately become deselected. When the primary power source is restored to within 50mV of the secondary supply, the primary power source will once again be selected and provide all the output current. When VCC1 is selected, it will supply all the internal current requirements which are typically 20µA. When VCC1 is not selected, there will be no current loading on this input. VCC2 is the secondary power source and is selected when the primary source has fallen below it by more than 125mV (or 200mV if pin 8 is grounded). The secondary source will be deselected immediately once the primary source is restored to within 50mV of VCC2 . When VCC2 is selected, it will supply all the internal current requirements which are typically 20µA. When VCC2 is not selected, there will be no current loading on this input. GND is the negative reference for all voltages. VOUT provides the power for the load. During normal operation the impedance from VOUT to the selected supply is typically less than 0.28Ω, which results in minimal voltage loss from input to output. During the cold-start interval when both inputs are initially applied, the internal circuitry provides a soft turn-on for the switches, which limits peak in-rush current. HYS is the user-selectable hysteresis input. The hysteresis level is set to 150mV when grounding pin 8. The default hysteresis level is set to 75mV by leaving pin 8 unconnected. Using 150mV hysteresis is recommended, especially in environments with noisy power supplies, high power supply resistances or high load currents. If the hysteresis level is set to 150mV, the primary supply VCC1 must now fall 200mV below the secondary supply VCC2 before it becomes deselected. Important note: There is an internal connection between pins 1 and 2. These pins must be connected externally. There is an internal connection between pins 3 and 4. These pins must be connected externally. There is an internal connection between pins 6 and 7. These pins must be connected externally. PIN FUNCTIONS Pin No. 1, 2 3, 4 5 6, 7 8 Symbol VCC1 VCC2 GND VOUT HYS Description Primary Positive Supply input. This input must fall below the secondary input by more than 125mV (or 200mV if pin 8 is grounded) before it is deselected. Secondary Positive Supply input. This input will be deselected whenever the primary input has been restored to within 50mV ofVCC2. Negative reference for all voltages. Positive voltage output internally switched to either VCC1 or VCC2 input source. Pins 6 and 7 must be connected together externally. Hysteresis adjust. Not Connected for 75mV hysteresis. Connect pin 8 to pin 5 (GND) for 150mV hysteresis. © 2000 California Micro Devices Corp. All rights reserved. 10/18/2000 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CALIFORNIA MICRO DEVICES CMPWR025 SELECTION THRESHOLD DIAGRAMS VCC1SEL (50mV) VCC2 VCC1DES1 (75mV) VHYS1 (75mV) VCC1 SW1 SW2 OFF ON ON OFF OFF ON Supply Selection Threshold Diagram (Hysteresis Pin Floating) VCC1SEL (50mV) VCC2 VCC1DES1 (200mV) VHYS2 (150mV) VCC1 SW1 SW2 OFF ON ON OFF ON OFF OFF ON Supply Selection Threshold Diagram (Hysteresis Pin Grounded) ©2000 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 10/18/2000 CALIFORNIA MICRO DEVICES TYPICAL DC CHARACTERISTICS Hysterresis Voltage (mA) CMPWR025 200 175 150 125 100 75 50 25 0 2.5 3.0 4.5 5.5 6.5 7.5 VHYS1 VHYS2 VCC1SEL Switch Resistance vs. VCC with Temperature in Figure 1 shows the switch resistance measured at 500mA load, over a wide VCC voltage range. The resistance is shown at ambient temperatures of 0°C, 25°C, and 70°C. When the temperature rises from 25°C to 70°C, the switch resistance increases by about 20%. 0.40 Switch Resistance (Ω) 0.35 0.30 0.25 0.20 0.15 0.10 2.5 70˚C 25˚C 0˚C Temperature (˚C) Figure 3. Hysteresis Voltage vs.Temperature 3.0 3.5 4.0 4.5 5.0 5.5 6.0 POWER DISSIPATION AND OUTPUT CURRENT CONSIDERATION The CMPWR025 is supplied in standard SOIC or MSOP packages, which have a maximum power dissipation rating of 0.3W. It is important that the heat generated within the part does not exceed this rating. The heat generated by the load current is given by: PDISS = VSW X ILOAD or PDISS = RSW X (ILOAD)2 At a typical load of 375mA the PDISS is just 0.4 x (0.375)2 = 56mW. A primary consideration is Maximum Junction Temperature, TJ(max), which can be calculated using the following formula: TJ(max) = TA + θJA X PDISS Where: TA = The Ambient Temperature θJA = Thermal Resistance = 100 °C/W PDISS = Power Dissipation In the above example operating at an ambient of 70°C, Tj(max) would be: TJ(max) = 70°C + (0.056W)(100°C/W) = 75.6°C Maximum power dissipation, including the power from the other circuitry within the device, suggests a current rating of approximately: VCC (V) Figure 1. Switch Resistance vs. VCC with Temperature Supply Current vs. VCC with Temperature in Figure 2 shows how the small internal supply current varies with VCC voltage and temperature. This current will be drawn from the selected VCC input, and will be dissipated through ground pin 5. This current is independent of load current. 40 35 30 70˚C 25˚C 0˚C ICC (µA) 25 20 15 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) PDISS – PINT RSW = ILOAD 0.3W – 100µW Figure 2. Supply Current vs. VCC with Temperature (No Load) 0.4 = 865mA Note that this is beyond the maximum current rating of the device, which is to 750mA maximum. © 2000 California Micro Devices Corp. All rights reserved. 10/18/2000 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5 CALIFORNIA MICRO DEVICES TYPICAL TRANSIENT CHARACTERISTICS The circuit schematic below shows the transient characterization test setup. It includes the power supply source impedances RS1 and RS2, which represent the power supplies’ output impedances and interconnection parasitics to the VCC1 and VCC2 input pins. In this test setup, the series resistances on VCC1 and VCC2 are respectively RS1 = 0.16Ω, and RS2 = 0.06Ω, unless specified otherwise. A load resistance RL of 11Ω is used, setting a load current of about 450mA at 5V. The hysteresis level is increased by connecting pin 8 to ground, which will improve the transient performance in noisy environments. In the transient analysis, the rise time and fall time of VCC1 is very long, in the 20msec range, providing a worst case situation. Important note: Power supply source impedance must be as low as possible to avoid chatter during power transition. When operating in a high load and long rise time power-up condition, we recommend not exceeding a value of 0.15Ω on both source resistances. VHYS > I(RS + RT) Where: VHYS = The Minimum Hysterisis Voltage = 80mV Rs = The Power Supply Output Impedance RT = The PCB Trace Impedance For a rated load of 500mA, Rs + RT < 0.15Ω. CMPWR025 voltage at the input terminals will rise. If this voltage rise exceeds the hysteresis (75mV typical), the switch may chatter. There are four ways to eliminate this chatter: • Connect pin 8 to GND to select 150mV hysteresis, • Position the device as close as possible to the power supply connectors, • Use low-impedance PCB traces, or • Include low-ESR input bypass capacitors at the VCC1 and VCC2 input pins. Capacitors of 10mF or greater are recommended. VOUT provides the power for the load. To ensure the output is glitch-free during dynamic switching of the inputs, it is recommended that an external capacitor of 10µF or greater is included. This will restrict any transient output disturbances to less than 300mV at 500mA loading during dynamic switching of the inputs. The test set-up used in Figures 4 and 5 is described on page 5. The set-up for Figure 6 has larger series resistances on VCC1 and VCC2. VCC1 Rising from 0V to 5V/(VCC2 = 5V). Figure 4 shows the primary supply VCC1 becoming selected during a 0V to 5V transition. The secondary supply VCC2 is set to 5V DC. The channel 1 switch is turned on when VCC1 rises to within about 70mV of VCC2. VCC1 drops when it is selected due to power supply source resistance RS1. A positive glitch appears on VCC2 when channel 2 switch is turned off, due to power supply inductance. This has no effect on the output voltage. Input and Output Capacitors Filtering is typically unnecessary on the inputs, however power supply source impedance and parasitic resistance or inductance on the interconnections may result in chattering during the supply changeover. When an input is deselected and the input current drops to zero, the RS1 VCC1 5V TR = 20ms TF= 20ms C1 0.1µF + C2 10µF GND CMPWR025 RS2 VCC1 VCC2 + – VOUT C5 0.1µF + C6 10µF VOUT VCC2 5V C3 0.1µF + C4 10µF HYS GND Load 11Ω GND Transient Characterization Test Set-up ©2000 California Micro Devices Corp. All rights reserved. 6 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 10/18/2000 CALIFORNIA MICRO DEVICES CMPWR025 VCC1 Rising (VCC2 = 5V). Figure 6 is a bad test set-up that shows what may happen if either power supply source resistance RS1 or RS2 is too large. In this example, RS2 is increased to 0.3Ω. The oscillation during the power transition is caused by the cumulated voltage change across RS1 and RS2 being greater than the hysteresis. The behavior is exacerbated by: • a high load current, • too many parasitics on power lines, and • noisy power sources. To avoid such behavior, the solution is to reduce the load or parasitic on power supply and layout, or use a more stable power supply. See Application Note AP-211 for more information. Tek 1.00MS/s 4 Acqs ∆: 72mV @: 4.900V VCC2 3 VCC1 VOUT Ch1 100mV Ch3 100mV 100mV M 50µs Ch1 4.88V Figure 4. VCC1 rising from 0V to 5V, VCC2 = 5V. Ch1 and Ch2: VCC1 and VCC2, offset = 5V. Ch3: VOUT , offset = 5V. VCC1 Falling from 5V to 0V (VCC2 = 5V). Figure 5 shows the primary supply Vcc1 becoming deselected during a 5V to 0V transition. The test conditions are the same as in Figure 4. Channel 2 switch is turned on as soon as Vcc2 and Vcc1 are about 200mV. A negative glitch appears on Vcc2, when channel 2 is turned on. This has no effect on the output voltage. Tek 1.00MS/s 1 Acqs ∆: 200mV @: 4.802V VCC2 VCC1 Tek 50.0kS/s 0 Acqs ∆: 72mV @: 4.790V VCC2 VCC1 3 VOUT 100mV Ch3 500mV Ch2 100mV M 1.00ms Ch3 4.62V 3 Figure 6. VCC1 Rising (VCC2@ = 5V). Ch1 and Ch2: VCC1 and VCC2@, offset = 5V. Ch3: VOUT, offset = 3.3V. VOUT 100mV Ch3 100mV Ch2 100mV M 50µs Ch1 4.88V Figure 5. VCC1 falling from 0V to 5V (VCC2 = 5V). Ch1 and Ch2: VCC1 and VCC2, offset = 5V. Ch3: VOUT , offset = 5V. © 2000 California Micro Devices Corp. All rights reserved. 10/18/2000 215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 7