CSPDDR100

CALIFORNIA MICRO DEVICES CSPDDR100 Chip Scale DDR Termination Array Features • 16 Integrated High frequency Series/Parallel Terminations • Ultra small footprint Chip Scale Package • Ceramic substrate • 0.35mm Eutectic Solder Bumps, 0.65mm Pitch Applications • DDR Memory bus termination • SSTL Termination Product Description The CSPDDR100 is a high performance Integrated Passive Device (IPD) which provides Series/Parallel terminations suitable for use in SSTL and DDR termination applications. Sixteen (16) Series/Parallel termination channels are provided for a total of 32 integrated resistors. These resistors provide excellent high frequency performance in excess of 3GHz and are manufactured to an absolute tolerance of ±1%. The Chip Scale Package provides an ultra small footprint for this Integrated Passive Device and provides minimal parasitics compared to conventional packaging. Typical bump inductance is less than 25pH. The large solder bumps and ceramic substrate allow for standard attachment to laminate printed circuit boards without the use of underfill. The 4X9 Bump pattern is arranged for easy flow through routing on the pcb. SCHEMATIC DIAGRAM D R1 R1 R1 R1 R1 R1 R1 R1 C R2 R2 R2 R2 R2 R2 R2 R2 R2 B R1 A 1 2 R2 R2 R2 R2 R2 R2 R2 R1 R1 R1 R1 R1 R1 R1 3 4 5 6 7 8 9 S TA N D A R D PA R T O R D E R I N G I N F O R M AT I O N Package Style Chip Scale Bumps 36 Tape & Reel CSPDDR100 Ordering Part Number Part Marking Ink dot to mark bump A1 © 2000 California Micro Devices Corp. All rights reserved. 7/21/2000 C1260700 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES CSPDDR100 Package Diagram (Bumps Up View) 5.79mm 0.297mm 0.65 mm D C B A 0.35mm Dia. Bumps 1 2 3 4 5 6 7 8 9 0.245 mm 0.381mm 0.875mm 0.65 mm 2.44mm P R I N T E D C I R C U I T B OA R D R E C O M M E N D AT I O N S Pad Size on PCB Pad Shape Pad Definition Solder Mask Opening Solder Stencil Thickness Solder Stencil Aperture Opening Solder Flux Ratio Solder Paste Bond Trace Finish 0.300mm Round Non Solder Mask Defined Pads (NSMD) 0.350mm 0.152mm 0.360mm (sq.) 50/50 No Clean OSP (Entek Cu Plus 106A) Typical PCB Routing Diagram (Bumps Down View) 1 9 A B C D ©2000 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 7/21/2000 CALIFORNIA MICRO DEVICES CSPDDR100 R e s i s t o r Va l u e s ( Ω ) R1 (Ω) Ω) 25 R2 (Ω) Ω) 50 Code 100 S TA N D A R D VA L U E S Re s i s t o r Va l u e Ab s o l u t e To l e r a n c e R TCR of Resi st or s Powe r Ra t i n g / Re s i s t o r Op e r a t i n g Te mp e r a t u r e Ra n g e R1 = 25Ω, R2 = 50Ω, ±1% ±100ppm 1 0 0 mW –40°C to 85°C 250 EXH 225 200 PH Z2 Z3 Z4 Z5 RF CD EXH Temperature ( C) 175 150 125 100 75 50 25 0 48 97 145 194 Time (s) 242 290 339 387 435 o Typical Solder Reflow Thermal Profile (No Clean Flux) PART NUMBER KEY CSP DDR 100 PACKAGE TYPE CSP = Chip Scale Package APPLICATION DDR = Double Data Rate Memory Termination Resistor Value Code 100 = R1 25Ω; R2 50Ω © 2000 California Micro Devices Corp. All rights reserved. 7/21/2000 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CALIFORNIA MICRO DEVICES CSPDDR100 Applications The CSPDDR100, Chip Scale DDR Termination Array, provides sixteen (16) channels of series/parallel termination for SSTL termination applications such as DDR memory systems. SSTL is the bus standard for DDR SDRAM systems. Applying terminating resistors to DDR SDRAM’s interconnections is a necessity to avoid signal integrity problems in the memory system’s operation. Improper or no termination on an interconnection that is a transmission line will cause reflections which in turn will affect the performance of the system due to ringing, delays, exceeding IC voltage specifications, or crosstalk. [1] SSTL has four possible configurations. One of them calls for both a series termination resistor and a parallel termination at one end of the bus, as shown in Figure 1. This is the application that the CSPDDR100 satisfies. When a full level signal is sent down the transmission line and no reflection is desired, the parallel load resistance should equal the characteristic impedance (Z0) of the transmission line. When a less than full level signal is sent down a transmission line, it is desirable to have an intentional mismatch of the parallel termination load resistor so that the higher level reflection voltage (resulting from having RT > Z0) raises the signal to the full signal level so that load switching occurs in only one propagation delay time. The use of a series termination resistor at the source enables the sending of a reduced level signal on the first incident wave. A reduced level signal is beneficial in reducing rise times and EMI. The values of the resistors for DDR/SSTL terminations are user determined. If values different from the ones in the CSPDDR100 specification are desired, please contact California Micro Devices for quotations on other values. [1] James Sutherland, “Understanding Transmission Lines, and High Speed Terminations”, EDN, October 9, 1999 VTT = 0.5 x VDDQ RT = 50Ω VTT = 0.5 x VDDQ RT = 50Ω VOUT RSERIES + VIN – VREF = 0.5 x VDDQ Figure 1. SSTL_2 Class II, Symmetrically Double Parallel Terminated Output Load with Series Resistor ©2000 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 7/21/2000