CAT1024ZI-42-GT3

CAT1024, CAT1025 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset FEATURES Precision Power Supply Voltage Monitor — 5V, 3.3V and 3V systems — Five threshold voltage options Active High or Low Reset — Valid reset guaranteed at VCC = 1V 400kHz I2C Bus 2.7V to 5.5V Operation Low power CMOS technology 16-Byte Page Write Buffer Built-in inadvertent write protection — WP pin (CAT1025) 1,000,000 Program/Erase cycles Manual Reset Input 100 year data retention Industrial and extended temperature ranges Green packages available with NiPdAu Lead finished DESCRIPTION The CAT1024 and CAT1025 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS techno– logy. Memory interface is via a 400kHz I2C bus. The CAT1025 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high ¯¯¯¯¯¯ and the other (RESET) drives low whenever VCC falls below the reset threshold voltage. The CAT1025 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high. The CAT1024 also provides a precision VCC sense ¯¯¯¯¯¯ circuit, but has only a RESET output and does not have a Write Protect input. The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, ¯¯¯¯¯¯ the RESET pin or a separate input, ¯¯¯, can be used MR as an input for push-button manual reset capability. The CAT1024/25 memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include an 8-pin PDIP and a surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP packages. The TDFN package thickness is 0.8mm maximum. TDFN footprint is 3x3mm. For Ordering Information details, see page 19. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 BLOCK DIAGRAM EXTERNA LOAD L DOUT ACK VCC VSS WORDADDRESS BUFFERS START/STOP LOGIC 2kbit EEPROM COLUMN DECODERS SENSEAMPS SHIFT REGISTERS THRESHOLD VOLTAGE OPTION Part Dash Number -45 -42 -30 -28 -25 Minimum Threshold 4.50 4.25 3.00 2.85 2.55 Maximum Threshold 4.75 4.50 3.15 3.00 2.70 SDA XDEC WP* CONTR OL LOGIC DATA IN STORAGE HIGHVOLTAGE/ TIMING CONTR OL RESET Controller MR Precision Vcc Monitor STATE COUNTERS SLAVE ADDRESS COMPARATORS SCL RESET* * CAT1025 Only RESET PIN CONFIGURATION DIP Package (L) SOIC Package (W) TSSOP Package (Y) MSOP Package (Z) ¯¯¯ MR ¯¯¯¯¯¯ RESET NC VSS ¯¯¯ MR ¯¯¯¯¯¯ RESET RESET VSS 1 2 3 4 CAT1024 8 7 6 5 VCC NC SCL SDA (Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (ZD4) VCC 8 NC 7 CAT1024 SCL 6 SDA 5 VCC 8 WDI 7 CAT1025 SCL 6 SDA 5 1 ¯¯¯ MR ¯¯¯¯¯¯ 2 RESET 3 NC 4 VSS 1 ¯¯¯ MR ¯¯¯¯¯¯ 2 RESET 3 RESET 4 VSS 1 2 3 4 CAT1025 8 7 6 5 VCC WP SCL SDA Doc. No. MD-3008 Rev. O 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 PIN DESCRIPTION ¯¯¯¯¯¯ RESET/RESET: RESET OUTPUTs (RESET CAT1025 Only) ¯¯¯¯¯¯ These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the ¯¯¯¯¯¯ RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. ¯¯¯: MANUAL RESET INPUT MR Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while ¯¯¯ input is MR low and for the reset timeout period after ¯¯¯ returns MR to high. The input has an internal pull up resistor. WP (CAT1025 Only): WRITE PROTECT INPUT When WP input is tied to VSS or left unconnected write operations to the entire array are allowed. When tied to VCC, the entire array is protected. This input has an internal pull down resistor. PIN FUNCTION Pin Name NC ¯¯¯¯¯¯ RESET VSS SDA SCL RESET VCC WP ¯¯¯ MR Function No Connect Active Low Reset Input/Output Ground Serial Data/Address Clock Input Active High Reset Output (CAT1025 only) Power Supply Write Protect (CAT1025 only) Manual Reset Input OPERATING TEMPERATURE RANGE Industrial Extended -40ºC to 85ºC -40ºC to 125ºC CAT10XX FAMILY OVERVIEW Device CAT1021 CAT1022 CAT1023 CAT1024 CAT1025 CAT1026 CAT1027 WDI Manual Reset Input Pin Watchdog Watchdog Monitor Pin SDA SDA WDI Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM 2k 2k 2k 2k 2k 2k 2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 ABSOLUTE MAXIMUM RATINGS(1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground VCC with Respect to Ground Package Power Dissipation Capability (TA = 25°C) Lead Soldering Temperature (10 secs) Output Short Circuit Current (3) (2) Ratings –55 to +125 –65 to +150 –2.0 to VCC + 2.0 –2.0 to 7.0 1.0 300 100 Units ºC ºC V V W ºC mA D.C. OPERATING CHARACTERISTICS VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified. Symbol ILI ILO ICC1 ICC2 ISB VIL(4) VIH (4) Parameter Input Leakage Current Output Leakage Current Power Supply Current (Write) Power Supply Current (Read) Standby Current Input Low Voltage Input High Voltage Output Low Voltage ¯¯¯¯¯¯ (SDA, RESET) Output High Voltage (RESET) Test Conditions VIN = GND to VCC VIN = GND to VCC fSCL = 400kHz VCC = 5.5V fSCL = 400kHz VCC = 5.5V Vcc = 5.5V, VIN = GND or VCC Min -2 -10 Typ Max 10 10 3 1 40 Units µA µA mA mA µA V V V V -0.5 0.7 x Vcc IOL = 3mA VCC = 2.7V IOH = -0.4mA VCC = 2.7V CAT102x-45 (VCC = 5.0V) CAT102x-42 (VCC = 5.0V) VCC - 0.75 4.50 4.25 3.00 2.85 2.55 1.00 15 0.3 x VCC VCC + 0.5 0.4 VOL VOH 4.75 4.50 3.15 3.00 2.70 V VTH Reset Threshold CAT102x-30 (VCC = 3.3V) CAT102x-28 (VCC = 3.3V) CAT102x-25 (VCC = 3.0V) VRVALID VRT (5) Reset Output Valid VCC Voltage Reset Threshold Hysteresis V mV Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) VIL min and VIH max are reference values only and are not tested. (5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. MD-3008 Rev. O 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 CAPACITANCE TA = 25ºC, f = 1.0MHz, VCC = 5V Symbol COUT CIN (1) (1) Test Output Capacitance Input Capacitance Test Conditions VOUT = 0V VIN = 0V Max 8 6 Units pF pF AC CHARACTERISTICS VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle(2) Symbol fSCL tSP tLOW tHIGH tR tF (1) (1) Parameter Clock Frequency Input Filter Spike Suppression (SDA, SCL) Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time (for a Repeated Start) Data Input Hold Time Data Input Setup Time Stop Condition Setup Time SCL Low to Data Out Valid Data Out Hold Time Time the Bus must be Free Before a New Transmission Can Start Write Cycle Time (Byte or Page) Min Max 400 100 Units kHz ns µs µs 1.3 0.6 300 300 0.6 0.6 0 100 0.6 900 50 1.3 5 ns ns µs µs ns ns µs ns ns µs ms tHD; STA tSU; STA tHD; DAT tSU; DAT tSU; STO tAA tDH tBUF (1) tWC(3) Notes: (1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (2) Test Conditions according to “AC Test Conditions” table. (3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 RESET CIRCUIT AC CHARACTERISTICS Symbol tPURST tRDP tGLITCH MR Glitch tMRW tMRD Parameter Power-Up Reset Timeout VTH to RESET Output Delay VCC Glitch Reject Pulse Width Manual Reset Glitch Immunity MR Pulse Width MR Input to RESET Output Delay Test Conditions Note 2 Note 3 Note 4, 5 Note 1 Note 1 Note 1 5 1 Min 130 Typ 200 Max 270 5 30 100 Units ms µs ns ns µs µs POWER-UP TIMING (5), (6) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Test Conditions Min Typ Max 270 270 Units ms ms AC TEST CONDITIONS Parameter Input Pulse Voltages Input Rise and Fall Times Input Reference Voltages Output Reference Voltages Output Load RELIABILITY CHARACTERISTICS Symbol NEND (5) Test Conditions 0.2VCC to 0.8VCC 10ns 0.3VCC, 0.7VCC 0.5VCC Current Source: IOL = 3mA; CL = 100pF Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Max Units Cycles/Byte Years Volts mA TDR(5) VZAP(5) ILTH(5)(7) Notes: (1) Test Conditions according to “AC Test Conditions” table. (2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data (5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. (7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V. Doc. No. MD-3008 Rev. O 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 DEVICE OPERATION Reset Controller Description The CAT1024/25 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET outputs will be active ¯¯¯¯¯¯ when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Operation ¯¯¯¯¯¯ The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that ¯¯¯¯¯¯ is, the RESET input will initiate a reset timeout after detecting a high to low transition. ¯¯¯¯¯¯ When RESET I/O is driven to the active state, the 200ms timer will begin to time the reset interval. If external reset is shorter than 200ms, Reset outputs will remain active at least 200ms. The CAT1024/25 also have a separate manual reset input. Driving the ¯¯¯ input low by connecting a MR pushbutton (normally open) from ¯¯¯ pin to GND will MR generate a reset condition. The input has an internal pull up resistor. Reset remains asserted while ¯¯¯ is low and for the MR Reset Timeout period after ¯¯¯ input has gone high. MR Glitches shorter than 100ns on ¯¯¯ input will not geMR nerate a reset pulse. No external debouncing circuits are required. Manual reset operation using ¯¯¯ input MR is shown in Figure 2. Hardware Data Protection The CAT1024/25 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. In addition, the CAT1025 includes a Write Protection Input which when tied to VCC will disable any write operations to the device. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 Figure 1. RESET Output Timing t GLITCH VTH V RVALID VCC t PURST t RPD t PURST t RPD RESE T RESE T Figure 2: ¯¯¯ Operation and Timing MR t MRW MR t MRD RESET t PURST RESET Doc. No. MD-3008 Rev. O 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 EMBEDDED EEPROM OPERATION The CAT1024 and CAT1025 feature a 2-kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START CONDITION The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of 2 SDA when SCL is HIGH. The CAT1024/25 monitors the SDA and SCL lines and will not respond until this condition is met. STOP CONDITION A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT1024/25 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1024/25 then perform a Read or ¯¯ Write operation depending on the R/W bit. Figure 3. Bus Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR Figure 4. Write Cycle Timing SC L SD A 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1024/25 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT1024/25 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1024/25 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmis– sion and waits for a STOP condition. Figure 5. Start/Stop Timing WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information ¯¯ (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1024/25 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. SDA SCL START BIT STOP BIT Figure 6. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 7: Slave Address Bits Default Configuration 1 0 1 0 0 0 0 R/W Doc. No. MD-3008 Rev. O 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 Page Write The CAT1024/25 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1024/25 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1024/25 in a single write cycle. Figure 8. Byte Write Timing S T A R T S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS DATA S T O P P Figure 9: Page Write Timing S T A R T S A C K A C K A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS (n) DATA n DATA n+1 S T DATA n+15 O P P © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1024/25 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. READ OPERATIONS The READ operation for the CAT1024/25 is initiated in the same manner as the write operation with one exception, ¯¯ the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. WRITE PROTECTION PIN (WP) The Write Protection feature (CAT1025 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1025 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. Figure 10. Immediate Address Read Timing S T A R T S A C K DATA N O A C K S T O P P BUS ACTIVIT Y: MASTER SDA LINE SLAVE ADDRESS SCL 8 9 SDA 8TH BI T DATA OUT NO ACK STOP Doc. No. MD-3008 Rev. O 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 Immediate/Current Address Read The CAT1024 and CAT1025 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1024/1025 receives its slave ¯¯ address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1024 and CAT1025 acknowledges, the Master device sends the START condition and the slave ¯¯ address again, this time with the R/W bit set to one. The CAT1024 and CAT1025 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1024 and CAT1025 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1024 and CAT1025 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1024 and CAT1025 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1024 and CAT1025 address bits so that the entire memory array can be read during one operation. Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K A C K SLAVE ADDRESS BYTE ADDRESS (n) S T A R T S A C K DATA n N O A C K SLAVE ADDRESS S T O P P Figure 12. Sequential Read Timing S T O P P A C K A C K A C K A C K N O A C K Doc. No. MD-3008 Rev. O BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 CAT1024, CAT1025 PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300mils (L) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 b2 c D E e E1 eB PIN # 1 IDENTIFICATION D L TOP VIEW E A A2 A1 b2 L c e b eB SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. Doc. No. MD-3008 Rev. O 14 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 SOIC 8-Lead 150mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0º 1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN # 1 IDENTIFICATION TOP VIEW D h A1 A θ c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 TSSOP 8-Lead (V) (1)(2) b SYMBOL MIN NOM MAX A A1 A2 b c E1 E 1.20 0.05 0.80 0.19 0.09 2.90 6.30 4.30 3.00 6.40 4.40 0.65 BSC 1.00 REF 0.50 0° 0.60 0.75 8° 0.90 0.15 1.05 0.30 0.20 3.10 6.50 4.50 D E E1 e L L1 θ1 e TOP VIEW D c A2 A θ1 A1 SIDE VIEW L1 END VIEW L For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153 Doc. No. MD-3008 Rev. O 16 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 MSOP 8-Lead (Z) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b c D E E1 1.10 0.05 0.75 0.22 0.13 2.90 4.80 2.90 0.40 3.00 4.90 3.00 0.65 BSC 0.60 0.95 REF 0.25 BSC 0º 6º 0.80 0.10 0.85 0.15 0.95 0.38 0.23 3.10 5.00 3.10 E E1 e L L1 L2 θ TOP VIEW D A A2 DETAIL A A1 e SIDE VIEW b c END VIEW θ L2 L L1 DETAIL A For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 17 Doc. No. MD-3008 Rev. O CAT1024, CAT1025 TDFN 8-Pad 3 x 3mm (ZD4) (1)(2) D A e b L E E2 PIN#1 ID PIN#1 INDEX AREA A1 D2 TOP VIEW SIDE VIEW BOTTOM VIEW SYMBOL MIN NOM MAX A A1 A3 b D D2 E E2 e L 0.70 0.00 0.23 2.90 2.20 2.90 1.40 0.20 0.75 0.02 0.20 REF 0.30 3.00 2.30 3.00 1.50 0.65 TYP 0.30 0.80 0.05 A A3 A1 0.37 3.10 2.40 3.10 1.60 0.40 FRONT VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-229. Doc. No. MD-3008 Rev. O 18 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT1024, CAT1025 EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Company ID Device # Suffix 1024 W I Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 1024: 2K 1025: 2K Package L: PDIP W: SOIC Y: TSSOP Z: MSOP ZD4: TDFN 3 x 3mm (5) Reset Threshold Voltage -45: 4.50V – 4.75V -42: 4.25V – 4.50V -30: 3.00V – 3.15V -28: 2.85V – 3.00V -25: 2.55V – 2.70V -30 – G T3 Tape & Reel T: Tape & Reel 2: 2000/Reel (only TDFN) 3: 3000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu Ordering Part Number – CAT1024xx CAT1024LI-45-G CAT1024ZI-45-GT3 CAT1024LI-42-G CAT1024ZI-42-GT3 CAT1024LI-30-G CAT1024ZI-30-GT3 CAT1024LI-28-G CAT1024ZI-28-GT3 CAT1024LI-25-G CAT1024ZI-25-GT3 CAT1024WI-45-GT3 CAT1024ZD4I-45-T2 CAT1024WI-42-GT3 CAT1024ZD4I-42-T2 CAT1024WI-30-GT3 CAT1024ZD4I-30-T2 CAT1024WI-28-GT3 CAT1024ZD4I-28-T2 CAT1024WI-25-GT3 CAT1024ZD4I-25-T2 CAT1024YI-45-GT3 CAT1024YI-42-GT3 CAT1024YI-30-GT3 CAT1024YI-28-GT3 CAT1024YI-25-GT3 Ordering Part Number – CAT1025xx CAT1025LI-45-G CAT1025ZI-45-GT3 CAT1025LI-42-G CAT1025ZI-42-GT3 CAT1025LI-30-G CAT1025ZI-30-GT3 CAT1025LI-28-G CAT1025ZI-28-GT3 CAT1025LI-25-G CAT1025ZI-25-GT3 CAT1025WI-45-GT3 CAT1025ZD4I-45-T2 CAT1025WI-42-GT3 CAT1025ZD4I-42-T2 CAT1025WI-30-GT3 CAT1025ZD4I-30-T2 CAT1025WI-28-GT3 CAT1025ZD4I-28-T2 CAT1025WI-25-GT3 CAT1025ZD4I-25-T2 CAT1025YI-45-GT3 CAT1025YI-42-GT3 CAT1025YI-30-GT3 CAT1025YI-28-GT3 CAT1025YI-25-GT3 Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT1024WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. (5) TDFN not available in NiPdAu (–G) version. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 19 Doc. No. MD-3008 Rev. O REVISION HISTORY Date 11/07/2003 04/12/2004 11/01/2004 11/04/2004 11/11/2004 02/02/2007 11/28/2007 Rev. I J K L M N O Reason Eliminated Automotive temperature range Eliminated data sheet designation Updated Reel Ordering Information Changed SOIC package designators Eliminated 8-pad TDFN (3 x 4.9mm) package Added package outlines Update Pin Configuration Update Feature Update Description Update DC Operating Characteristic Update AC Characteristics Update Example of Ordering Information Update Package Outline Drawings Update Example of Ordering Information Add “MD-“ to document number Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-3008 Revision: O Issue date: 11/28/07